src/gallium/drivers/freedreno/a6xx/fd6_emit.h

   1 /*
   2  * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
   3  * Copyright © 2018 Google, Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  22  * SOFTWARE.
  23  *
  24  * Authors:
  25  *    Rob Clark <robclark@freedesktop.org>
  26  */
  27
  28 #ifndef FD6_EMIT_H
  29 #define FD6_EMIT_H
  30
  31 #include "pipe/p_context.h"
  32
  33 #include "freedreno_context.h"
  34 #include "fd6_context.h"
  35 #include "fd6_format.h"
  36 #include "fd6_program.h"
  37 #include "ir3_gallium.h"
  38
  39 struct fd_ringbuffer;
  40
  41 /* To collect all the state objects to emit in a single CP_SET_DRAW_STATE
  42  * packet, the emit tracks a collection of however many state_group's that
  43  * need to be emit'd.
  44  */
  45 enum fd6_state_id {
  46         FD6_GROUP_PROG_CONFIG,
  47         FD6_GROUP_PROG,
  48         FD6_GROUP_PROG_BINNING,
  49         FD6_GROUP_PROG_INTERP,
  50         FD6_GROUP_PROG_FB_RAST,
  51         FD6_GROUP_LRZ,
  52         FD6_GROUP_LRZ_BINNING,
  53         FD6_GROUP_VTXSTATE,
  54         FD6_GROUP_VBO,
  55         FD6_GROUP_CONST,
  56         FD6_GROUP_VS_DRIVER_PARAMS,
  57         FD6_GROUP_PRIMITIVE_PARAMS,
  58         FD6_GROUP_VS_TEX,
  59         FD6_GROUP_HS_TEX,
  60         FD6_GROUP_DS_TEX,
  61         FD6_GROUP_GS_TEX,
  62         FD6_GROUP_FS_TEX,
  63         FD6_GROUP_IBO,
  64         FD6_GROUP_RASTERIZER,
  65         FD6_GROUP_ZSA,
  66         FD6_GROUP_BLEND,
  67         FD6_GROUP_SCISSOR,
  68         FD6_GROUP_BLEND_COLOR,
  69         FD6_GROUP_SO,
  70 };
  71
  72 #define ENABLE_ALL (CP_SET_DRAW_STATE__0_BINNING | CP_SET_DRAW_STATE__0_GMEM | CP_SET_DRAW_STATE__0_SYSMEM)
  73 #define ENABLE_DRAW (CP_SET_DRAW_STATE__0_GMEM | CP_SET_DRAW_STATE__0_SYSMEM)
  74
  75 struct fd6_state_group {
  76         struct fd_ringbuffer *stateobj;
  77         enum fd6_state_id group_id;
  78         /* enable_mask controls which states the stateobj is evaluated in,
  79          * b0 is binning pass b1 and/or b2 is draw pass
  80          */
  81         uint32_t enable_mask;
  82 };
  83
  84 /* grouped together emit-state for prog/vertex/state emit: */
  85 struct fd6_emit {
  86         struct fd_context *ctx;
  87         const struct fd_vertex_state *vtx;
  88         const struct pipe_draw_info *info;
  89         struct ir3_cache_key key;
  90         enum fd_dirty_3d_state dirty;
  91
  92         uint32_t sprite_coord_enable;  /* bitmask */
  93         bool sprite_coord_mode;
  94         bool rasterflat;
  95         bool no_decode_srgb;
  96         bool primitive_restart;
  97
  98         /* cached to avoid repeated lookups: */
  99         const struct fd6_program_state *prog;
 100
 101         struct ir3_shader_variant *bs;
 102         struct ir3_shader_variant *vs;
 103         struct ir3_shader_variant *hs;
 104         struct ir3_shader_variant *ds;
 105         struct ir3_shader_variant *gs;
 106         struct ir3_shader_variant *fs;
 107
 108         unsigned streamout_mask;
 109
 110         struct fd6_state_group groups[32];
 111         unsigned num_groups;
 112 };
 113
 114 static inline const struct fd6_program_state *
 115 fd6_emit_get_prog(struct fd6_emit *emit)
 116 {
 117         if (!emit->prog) {
 118                 struct fd6_context *fd6_ctx = fd6_context(emit->ctx);
 119                 struct ir3_program_state *s =
 120                                 ir3_cache_lookup(fd6_ctx->shader_cache, &emit->key, &emit->ctx->debug);
 121                 emit->prog = fd6_program_state(s);
 122         }
 123         return emit->prog;
 124 }
 125
 126 static inline void
 127 fd6_emit_take_group(struct fd6_emit *emit, struct fd_ringbuffer *stateobj,
 128                 enum fd6_state_id group_id, unsigned enable_mask)
 129 {
 130         debug_assert(emit->num_groups < ARRAY_SIZE(emit->groups));
 131         struct fd6_state_group *g = &emit->groups[emit->num_groups++];
 132         g->stateobj = stateobj;
 133         g->group_id = group_id;
 134         g->enable_mask = enable_mask;
 135 }
 136
 137 static inline void
 138 fd6_emit_add_group(struct fd6_emit *emit, struct fd_ringbuffer *stateobj,
 139                 enum fd6_state_id group_id, unsigned enable_mask)
 140 {
 141         fd6_emit_take_group(emit, fd_ringbuffer_ref(stateobj), group_id, enable_mask);
 142 }
 143
 144 static inline unsigned
 145 fd6_event_write(struct fd_batch *batch, struct fd_ringbuffer *ring,
 146                 enum vgt_event_type evt, bool timestamp)
 147 {
 148         unsigned seqno = 0;
 149
 150         fd_reset_wfi(batch);
 151
 152         OUT_PKT7(ring, CP_EVENT_WRITE, timestamp ? 4 : 1);
 153         OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(evt));
 154         if (timestamp) {
 155                 struct fd6_context *fd6_ctx = fd6_context(batch->ctx);
 156                 seqno = ++fd6_ctx->seqno;
 157                 OUT_RELOC(ring, control_ptr(fd6_ctx, seqno));  /* ADDR_LO/HI */
 158                 OUT_RING(ring, seqno);
 159         }
 160
 161         return seqno;
 162 }
 163
 164 static inline void
 165 fd6_cache_inv(struct fd_batch *batch, struct fd_ringbuffer *ring)
 166 {
 167         fd6_event_write(batch, ring, CACHE_INVALIDATE, false);
 168 }
 169
 170 static inline void
 171 fd6_cache_flush(struct fd_batch *batch, struct fd_ringbuffer *ring)
 172 {
 173         struct fd6_context *fd6_ctx = fd6_context(batch->ctx);
 174         unsigned seqno;
 175
 176         seqno = fd6_event_write(batch, ring, RB_DONE_TS, true);
 177
 178         OUT_PKT7(ring, CP_WAIT_REG_MEM, 6);
 179         OUT_RING(ring, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ) |
 180                        CP_WAIT_REG_MEM_0_POLL_MEMORY);
 181         OUT_RELOC(ring, control_ptr(fd6_ctx, seqno));
 182         OUT_RING(ring, CP_WAIT_REG_MEM_3_REF(seqno));
 183         OUT_RING(ring, CP_WAIT_REG_MEM_4_MASK(~0));
 184         OUT_RING(ring, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(16));
 185
 186         seqno = fd6_event_write(batch, ring, CACHE_FLUSH_TS, true);
 187
 188         OUT_PKT7(ring, CP_WAIT_MEM_GTE, 4);
 189         OUT_RING(ring, CP_WAIT_MEM_GTE_0_RESERVED(0));
 190         OUT_RELOC(ring, control_ptr(fd6_ctx, seqno));
 191         OUT_RING(ring, CP_WAIT_MEM_GTE_3_REF(seqno));
 192 }
 193
 194 static inline void
 195 fd6_emit_blit(struct fd_batch *batch, struct fd_ringbuffer *ring)
 196 {
 197         emit_marker6(ring, 7);
 198         fd6_event_write(batch, ring, BLIT, false);
 199         emit_marker6(ring, 7);
 200 }
 201
 202 static inline void
 203 fd6_emit_lrz_flush(struct fd_ringbuffer *ring)
 204 {
 205         OUT_PKT7(ring, CP_EVENT_WRITE, 1);
 206         OUT_RING(ring, LRZ_FLUSH);
 207 }
 208
 209 static inline bool
 210 fd6_geom_stage(gl_shader_stage type)
 211 {
 212         switch (type) {
 213         case MESA_SHADER_VERTEX:
 214         case MESA_SHADER_TESS_CTRL:
 215         case MESA_SHADER_TESS_EVAL:
 216         case MESA_SHADER_GEOMETRY:
 217                 return true;
 218         case MESA_SHADER_FRAGMENT:
 219         case MESA_SHADER_COMPUTE:
 220         case MESA_SHADER_KERNEL:
 221                 return false;
 222         default:
 223                 unreachable("bad shader type");
 224         }
 225 }
 226
 227 static inline uint32_t
 228 fd6_stage2opcode(gl_shader_stage type)
 229 {
 230         return fd6_geom_stage(type) ? CP_LOAD_STATE6_GEOM : CP_LOAD_STATE6_FRAG;
 231 }
 232
 233 static inline enum a6xx_state_block
 234 fd6_stage2shadersb(gl_shader_stage type)
 235 {
 236         switch (type) {
 237         case MESA_SHADER_VERTEX:
 238                 return SB6_VS_SHADER;
 239         case MESA_SHADER_TESS_CTRL:
 240                 return SB6_HS_SHADER;
 241         case MESA_SHADER_TESS_EVAL:
 242                 return SB6_DS_SHADER;
 243         case MESA_SHADER_GEOMETRY:
 244                 return SB6_GS_SHADER;
 245         case MESA_SHADER_FRAGMENT:
 246                 return SB6_FS_SHADER;
 247         case MESA_SHADER_COMPUTE:
 248         case MESA_SHADER_KERNEL:
 249                 return SB6_CS_SHADER;
 250         default:
 251                 unreachable("bad shader type");
 252                 return ~0;
 253         }
 254 }
 255
 256 static inline enum a6xx_tess_spacing
 257 fd6_gl2spacing(enum gl_tess_spacing spacing)
 258 {
 259         switch (spacing) {
 260         case TESS_SPACING_EQUAL:
 261                 return TESS_EQUAL;
 262         case TESS_SPACING_FRACTIONAL_ODD:
 263                 return TESS_FRACTIONAL_ODD;
 264         case TESS_SPACING_FRACTIONAL_EVEN:
 265                 return TESS_FRACTIONAL_EVEN;
 266         case TESS_SPACING_UNSPECIFIED:
 267         default:
 268                 unreachable("spacing must be specified");
 269         }
 270 }
 271
 272 bool fd6_emit_textures(struct fd_pipe *pipe, struct fd_ringbuffer *ring,
 273                 enum pipe_shader_type type, struct fd_texture_stateobj *tex,
 274                 unsigned bcolor_offset,
 275                 const struct ir3_shader_variant *v, struct fd_context *ctx);
 276
 277 void fd6_emit_state(struct fd_ringbuffer *ring, struct fd6_emit *emit);
 278
 279 void fd6_emit_cs_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
 280                 struct ir3_shader_variant *cp);
 281
 282 void fd6_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring);
 283
 284 void fd6_emit_init_screen(struct pipe_screen *pscreen);
 285 void fd6_emit_init(struct pipe_context *pctx);
 286
 287 static inline void
 288 fd6_emit_ib(struct fd_ringbuffer *ring, struct fd_ringbuffer *target)
 289 {
 290         emit_marker6(ring, 6);
 291         __OUT_IB5(ring, target);
 292         emit_marker6(ring, 6);
 293 }
 294
 295 #define WRITE(reg, val) do {                                    \
 296                 OUT_PKT4(ring, reg, 1);                                 \
 297                 OUT_RING(ring, val);                                    \
 298         } while (0)
 299
 300
 301 #endif /* FD6_EMIT_H */