src/gallium/drivers/freedreno/a6xx/fd6_emit.h

   1 /*
   2  * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
   3  * Copyright © 2018 Google, Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  22  * SOFTWARE.
  23  *
  24  * Authors:
  25  *    Rob Clark <robclark@freedesktop.org>
  26  */
  27
  28 #ifndef FD6_EMIT_H
  29 #define FD6_EMIT_H
  30
  31 #include "pipe/p_context.h"
  32
  33 #include "freedreno_context.h"
  34 #include "fd6_context.h"
  35 #include "fd6_format.h"
  36 #include "fd6_program.h"
  37 #include "ir3_shader.h"
  38
  39 struct fd_ringbuffer;
  40
  41 /* To collect all the state objects to emit in a single CP_SET_DRAW_STATE
  42  * packet, the emit tracks a collection of however many state_group's that
  43  * need to be emit'd.
  44  */
  45 enum fd6_state_id {
  46         FD6_GROUP_PROG,
  47         FD6_GROUP_PROG_BINNING,
  48         FD6_GROUP_ZSA,
  49         FD6_GROUP_ZSA_BINNING,
  50         FD6_GROUP_VBO,
  51         FD6_GROUP_VBO_BINNING,
  52         FD6_GROUP_VS_CONST,
  53         FD6_GROUP_FS_CONST,
  54         FD6_GROUP_VS_TEX,
  55         FD6_GROUP_FS_TEX,
  56 };
  57
  58 struct fd6_state_group {
  59         struct fd_ringbuffer *stateobj;
  60         enum fd6_state_id group_id;
  61         uint8_t enable_mask;
  62 };
  63
  64 /* grouped together emit-state for prog/vertex/state emit: */
  65 struct fd6_emit {
  66         struct fd_context *ctx;
  67         const struct fd_vertex_state *vtx;
  68         const struct pipe_draw_info *info;
  69         struct ir3_cache_key key;
  70         enum fd_dirty_3d_state dirty;
  71
  72         uint32_t sprite_coord_enable;  /* bitmask */
  73         bool sprite_coord_mode;
  74         bool rasterflat;
  75         bool no_decode_srgb;
  76
  77         /* in binning pass, we don't have real frag shader, so we
  78          * don't know if real draw disqualifies lrz write.  So just
  79          * figure that out up-front and stash it in the emit.
  80          */
  81         bool no_lrz_write;
  82
  83         /* cached to avoid repeated lookups: */
  84         const struct fd6_program_state *prog;
  85
  86         struct ir3_shader_variant *bs;
  87         struct ir3_shader_variant *vs;
  88         struct ir3_shader_variant *fs;
  89
  90         unsigned streamout_mask;
  91
  92         struct fd6_state_group groups[32];
  93         unsigned num_groups;
  94 };
  95
  96 static inline const struct fd6_program_state *
  97 fd6_emit_get_prog(struct fd6_emit *emit)
  98 {
  99         if (!emit->prog) {
 100                 struct fd6_context *fd6_ctx = fd6_context(emit->ctx);
 101                 struct ir3_program_state *s =
 102                                 ir3_cache_lookup(fd6_ctx->shader_cache, &emit->key, &emit->ctx->debug);
 103                 emit->prog = fd6_program_state(s);
 104         }
 105         return emit->prog;
 106 }
 107
 108 static inline void
 109 fd6_emit_add_group(struct fd6_emit *emit, struct fd_ringbuffer *stateobj,
 110                 enum fd6_state_id group_id, unsigned enable_mask)
 111 {
 112         debug_assert(emit->num_groups < ARRAY_SIZE(emit->groups));
 113         struct fd6_state_group *g = &emit->groups[emit->num_groups++];
 114         g->stateobj = fd_ringbuffer_ref(stateobj);
 115         g->group_id = group_id;
 116         g->enable_mask = enable_mask;
 117 }
 118
 119 static inline void
 120 fd6_event_write(struct fd_batch *batch, struct fd_ringbuffer *ring,
 121                 enum vgt_event_type evt, bool timestamp)
 122 {
 123         fd_reset_wfi(batch);
 124
 125         OUT_PKT7(ring, CP_EVENT_WRITE, timestamp ? 4 : 1);
 126         OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(evt));
 127         if (timestamp) {
 128                 struct fd6_context *fd6_ctx = fd6_context(batch->ctx);
 129                 OUT_RELOCW(ring, fd6_ctx->blit_mem, 0, 0, 0);  /* ADDR_LO/HI */
 130                 OUT_RING(ring, ++fd6_ctx->seqno);
 131         }
 132 }
 133
 134 static inline void
 135 fd6_cache_flush(struct fd_batch *batch, struct fd_ringbuffer *ring)
 136 {
 137         fd6_event_write(batch, ring, 0x31, false);
 138 }
 139
 140 static inline void
 141 fd6_emit_blit(struct fd_batch *batch, struct fd_ringbuffer *ring)
 142 {
 143         emit_marker6(ring, 7);
 144         fd6_event_write(batch, ring, BLIT, false);
 145         emit_marker6(ring, 7);
 146 }
 147
 148 static inline void
 149 fd6_emit_lrz_flush(struct fd_ringbuffer *ring)
 150 {
 151         OUT_PKT7(ring, CP_EVENT_WRITE, 1);
 152         OUT_RING(ring, LRZ_FLUSH);
 153 }
 154
 155 static inline enum a6xx_state_block
 156 fd6_stage2shadersb(enum shader_t type)
 157 {
 158         switch (type) {
 159         case SHADER_VERTEX:
 160                 return SB6_VS_SHADER;
 161         case SHADER_FRAGMENT:
 162                 return SB6_FS_SHADER;
 163         case SHADER_COMPUTE:
 164                 return SB6_CS_SHADER;
 165         default:
 166                 unreachable("bad shader type");
 167                 return ~0;
 168         }
 169 }
 170
 171 bool fd6_emit_textures(struct fd_pipe *pipe, struct fd_ringbuffer *ring,
 172                 enum a6xx_state_block sb, struct fd_texture_stateobj *tex,
 173                 unsigned bcolor_offset);
 174
 175 struct fd_ringbuffer * fd6_build_vbo_state(struct fd6_emit *emit, const struct ir3_shader_variant *vp);
 176
 177 void fd6_emit_state(struct fd_ringbuffer *ring, struct fd6_emit *emit);
 178
 179 void fd6_emit_cs_state(struct fd_context *ctx, struct fd_ringbuffer *ring,
 180                 struct ir3_shader_variant *cp);
 181
 182 void fd6_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring);
 183
 184 void fd6_emit_init(struct pipe_context *pctx);
 185
 186 static inline void
 187 fd6_emit_ib(struct fd_ringbuffer *ring, struct fd_ringbuffer *target)
 188 {
 189         emit_marker6(ring, 6);
 190         __OUT_IB5(ring, target);
 191         emit_marker6(ring, 6);
 192 }
 193
 194 #define WRITE(reg, val) do {                                    \
 195                 OUT_PKT4(ring, reg, 1);                                 \
 196                 OUT_RING(ring, val);                                    \
 197         } while (0)
 198
 199
 200 #endif /* FD6_EMIT_H */