2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25 * Rob Clark <robclark@freedesktop.org>
30 #include "pipe/p_state.h"
31 #include "util/u_string.h"
32 #include "util/u_memory.h"
33 #include "util/u_inlines.h"
34 #include "util/format/u_format.h"
36 #include "freedreno_draw.h"
37 #include "freedreno_state.h"
38 #include "freedreno_resource.h"
40 #include "fd6_blitter.h"
42 #include "fd6_context.h"
45 #include "fd6_program.h"
46 #include "fd6_format.h"
47 #include "fd6_resource.h"
52 * Emits the flags registers, suitable for RB_MRT_FLAG_BUFFER,
53 * RB_DEPTH_FLAG_BUFFER, SP_PS_2D_SRC_FLAGS, and RB_BLIT_FLAG_DST.
56 fd6_emit_flag_reference(struct fd_ringbuffer
*ring
, struct fd_resource
*rsc
,
59 if (fd_resource_ubwc_enabled(rsc
, level
)) {
60 OUT_RELOCW(ring
, rsc
->bo
, fd_resource_ubwc_offset(rsc
, level
, layer
), 0, 0);
62 A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(rsc
->layout
.ubwc_slices
[level
].pitch
) |
63 A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(rsc
->layout
.ubwc_size
));
65 OUT_RING(ring
, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_LO */
66 OUT_RING(ring
, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_HI */
67 OUT_RING(ring
, 0x00000000);
72 emit_mrt(struct fd_ringbuffer
*ring
, struct pipe_framebuffer_state
*pfb
,
73 struct fd_gmem_stateobj
*gmem
)
75 unsigned char mrt_comp
[A6XX_MAX_RENDER_TARGETS
] = {0};
76 unsigned srgb_cntl
= 0;
82 for (i
= 0; i
< pfb
->nr_cbufs
; i
++) {
83 enum a6xx_color_fmt format
= 0;
84 enum a3xx_color_swap swap
= WZYX
;
85 bool sint
= false, uint
= false;
86 struct fd_resource
*rsc
= NULL
;
87 struct fdl_slice
*slice
= NULL
;
97 struct pipe_surface
*psurf
= pfb
->cbufs
[i
];
98 enum pipe_format pformat
= psurf
->format
;
99 rsc
= fd_resource(psurf
->texture
);
103 uint32_t base
= gmem
? gmem
->cbuf_base
[i
] : 0;
104 slice
= fd_resource_slice(rsc
, psurf
->u
.tex
.level
);
105 format
= fd6_pipe2color(pformat
);
106 sint
= util_format_is_pure_sint(pformat
);
107 uint
= util_format_is_pure_uint(pformat
);
109 if (util_format_is_srgb(pformat
))
110 srgb_cntl
|= (1 << i
);
112 offset
= fd_resource_offset(rsc
, psurf
->u
.tex
.level
,
113 psurf
->u
.tex
.first_layer
);
115 stride
= slice
->pitch
* rsc
->layout
.cpp
* pfb
->samples
;
116 swap
= rsc
->layout
.tile_mode
? WZYX
: fd6_pipe2swap(pformat
);
118 tile_mode
= fd_resource_tile_mode(psurf
->texture
, psurf
->u
.tex
.level
);
120 if (psurf
->u
.tex
.first_layer
< psurf
->u
.tex
.last_layer
) {
122 if (psurf
->texture
->target
== PIPE_TEXTURE_2D_ARRAY
&& psurf
->texture
->nr_samples
> 0)
123 type
= LAYER_MULTISAMPLE_ARRAY
;
124 else if (psurf
->texture
->target
== PIPE_TEXTURE_2D_ARRAY
)
125 type
= LAYER_2D_ARRAY
;
126 else if (psurf
->texture
->target
== PIPE_TEXTURE_CUBE
)
127 type
= LAYER_CUBEMAP
;
128 else if (psurf
->texture
->target
== PIPE_TEXTURE_3D
)
131 stride
/= pfb
->samples
;
134 debug_assert((offset
+ slice
->size0
) <= fd_bo_size(rsc
->bo
));
137 A6XX_RB_MRT_BUF_INFO(i
,
138 .color_format
= format
,
139 .color_tile_mode
= tile_mode
,
141 A6XX_RB_MRT_PITCH(i
, .a6xx_rb_mrt_pitch
= stride
),
142 A6XX_RB_MRT_ARRAY_PITCH(i
, .a6xx_rb_mrt_array_pitch
= slice
->size0
),
143 A6XX_RB_MRT_BASE(i
, .bo
= rsc
->bo
, .bo_offset
= offset
),
144 A6XX_RB_MRT_BASE_GMEM(i
, .unknown
= base
));
147 A6XX_SP_FS_MRT_REG(i
, .color_format
= format
,
148 .color_sint
= sint
, .color_uint
= uint
));
150 OUT_PKT4(ring
, REG_A6XX_RB_MRT_FLAG_BUFFER(i
), 3);
151 fd6_emit_flag_reference(ring
, rsc
,
152 psurf
->u
.tex
.level
, psurf
->u
.tex
.first_layer
);
155 OUT_REG(ring
, A6XX_RB_SRGB_CNTL(.dword
= srgb_cntl
));
156 OUT_REG(ring
, A6XX_SP_SRGB_CNTL(.dword
= srgb_cntl
));
158 OUT_REG(ring
, A6XX_RB_RENDER_COMPONENTS(
166 .rt7
= mrt_comp
[7]));
168 OUT_REG(ring
, A6XX_SP_FS_RENDER_COMPONENTS(
176 .rt7
= mrt_comp
[7]));
178 OUT_REG(ring
, A6XX_GRAS_LAYER_CNTL(.layered
= layered
, .type
= type
));
182 emit_zs(struct fd_ringbuffer
*ring
, struct pipe_surface
*zsbuf
,
183 struct fd_gmem_stateobj
*gmem
)
186 struct fd_resource
*rsc
= fd_resource(zsbuf
->texture
);
187 enum a6xx_depth_format fmt
= fd6_pipe2depth(zsbuf
->format
);
188 struct fdl_slice
*slice
= fd_resource_slice(rsc
, 0);
189 uint32_t stride
= slice
->pitch
* rsc
->layout
.cpp
;
190 uint32_t size
= slice
->size0
;
191 uint32_t base
= gmem
? gmem
->zsbuf_base
[0] : 0;
192 uint32_t offset
= fd_resource_offset(rsc
, zsbuf
->u
.tex
.level
,
193 zsbuf
->u
.tex
.first_layer
);
195 OUT_PKT4(ring
, REG_A6XX_RB_DEPTH_BUFFER_INFO
, 6);
196 OUT_RING(ring
, A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(fmt
));
197 OUT_RING(ring
, A6XX_RB_DEPTH_BUFFER_PITCH(stride
).value
);
198 OUT_RING(ring
, A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(size
).value
);
199 OUT_RELOCW(ring
, rsc
->bo
, offset
, 0, 0); /* RB_DEPTH_BUFFER_BASE_LO/HI */
200 OUT_RING(ring
, base
); /* RB_DEPTH_BUFFER_BASE_GMEM */
202 OUT_PKT4(ring
, REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO
, 1);
203 OUT_RING(ring
, A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(fmt
));
205 OUT_PKT4(ring
, REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO
, 3);
206 fd6_emit_flag_reference(ring
, rsc
,
207 zsbuf
->u
.tex
.level
, zsbuf
->u
.tex
.first_layer
);
210 OUT_PKT4(ring
, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO
, 5);
211 OUT_RELOCW(ring
, rsc
->lrz
, 0, 0, 0);
212 OUT_RING(ring
, A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH(rsc
->lrz_pitch
));
213 //OUT_RELOCW(ring, rsc->lrz, 0, 0, 0); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO/HI */
214 // XXX a6xx seems to use a different buffer here.. not sure what for..
215 OUT_RING(ring
, 0x00000000);
216 OUT_RING(ring
, 0x00000000);
218 OUT_PKT4(ring
, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO
, 5);
219 OUT_RING(ring
, 0x00000000);
220 OUT_RING(ring
, 0x00000000);
221 OUT_RING(ring
, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
222 OUT_RING(ring
, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO */
223 OUT_RING(ring
, 0x00000000);
226 /* NOTE: blob emits GRAS_LRZ_CNTL plus GRAZ_LRZ_BUFFER_BASE
227 * plus this CP_EVENT_WRITE at the end in it's own IB..
229 OUT_PKT7(ring
, CP_EVENT_WRITE
, 1);
230 OUT_RING(ring
, CP_EVENT_WRITE_0_EVENT(UNK_25
));
233 struct fdl_slice
*slice
= fd_resource_slice(rsc
->stencil
, 0);
234 stride
= slice
->pitch
* rsc
->stencil
->layout
.cpp
;
236 uint32_t base
= gmem
? gmem
->zsbuf_base
[1] : 0;
238 OUT_PKT4(ring
, REG_A6XX_RB_STENCIL_INFO
, 6);
239 OUT_RING(ring
, A6XX_RB_STENCIL_INFO_SEPARATE_STENCIL
);
240 OUT_RING(ring
, A6XX_RB_STENCIL_BUFFER_PITCH(stride
).value
);
241 OUT_RING(ring
, A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(size
).value
);
242 OUT_RELOCW(ring
, rsc
->stencil
->bo
, 0, 0, 0); /* RB_STENCIL_BASE_LO/HI */
243 OUT_RING(ring
, base
); /* RB_STENCIL_BASE_LO */
245 OUT_PKT4(ring
, REG_A6XX_RB_STENCIL_INFO
, 1);
246 OUT_RING(ring
, 0x00000000); /* RB_STENCIL_INFO */
249 OUT_PKT4(ring
, REG_A6XX_RB_DEPTH_BUFFER_INFO
, 6);
250 OUT_RING(ring
, A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH6_NONE
));
251 OUT_RING(ring
, 0x00000000); /* RB_DEPTH_BUFFER_PITCH */
252 OUT_RING(ring
, 0x00000000); /* RB_DEPTH_BUFFER_ARRAY_PITCH */
253 OUT_RING(ring
, 0x00000000); /* RB_DEPTH_BUFFER_BASE_LO */
254 OUT_RING(ring
, 0x00000000); /* RB_DEPTH_BUFFER_BASE_HI */
255 OUT_RING(ring
, 0x00000000); /* RB_DEPTH_BUFFER_BASE_GMEM */
257 OUT_PKT4(ring
, REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO
, 1);
258 OUT_RING(ring
, A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH6_NONE
));
260 OUT_PKT4(ring
, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO
, 5);
261 OUT_RING(ring
, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
262 OUT_RING(ring
, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
263 OUT_RING(ring
, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
264 OUT_RING(ring
, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO */
265 OUT_RING(ring
, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI */
267 OUT_PKT4(ring
, REG_A6XX_RB_STENCIL_INFO
, 1);
268 OUT_RING(ring
, 0x00000000); /* RB_STENCIL_INFO */
273 use_hw_binning(struct fd_batch
*batch
)
275 struct fd_gmem_stateobj
*gmem
= &batch
->ctx
->gmem
;
277 // TODO figure out hw limits for binning
279 return fd_binning_enabled
&& ((gmem
->nbins_x
* gmem
->nbins_y
) >= 2) &&
280 (batch
->num_draws
> 0);
284 patch_fb_read(struct fd_batch
*batch
)
286 struct fd_gmem_stateobj
*gmem
= &batch
->ctx
->gmem
;
288 for (unsigned i
= 0; i
< fd_patch_num_elements(&batch
->fb_read_patches
); i
++) {
289 struct fd_cs_patch
*patch
= fd_patch_element(&batch
->fb_read_patches
, i
);
290 *patch
->cs
= patch
->val
| A6XX_TEX_CONST_2_PITCH(gmem
->bin_w
* gmem
->cbuf_cpp
[0]);
292 util_dynarray_clear(&batch
->fb_read_patches
);
296 update_render_cntl(struct fd_batch
*batch
, struct pipe_framebuffer_state
*pfb
, bool binning
)
298 struct fd_ringbuffer
*ring
= batch
->gmem
;
300 bool depth_ubwc_enable
= false;
301 uint32_t mrts_ubwc_enable
= 0;
305 struct fd_resource
*rsc
= fd_resource(pfb
->zsbuf
->texture
);
306 depth_ubwc_enable
= fd_resource_ubwc_enabled(rsc
, pfb
->zsbuf
->u
.tex
.level
);
309 for (i
= 0; i
< pfb
->nr_cbufs
; i
++) {
313 struct pipe_surface
*psurf
= pfb
->cbufs
[i
];
314 struct fd_resource
*rsc
= fd_resource(psurf
->texture
);
318 if (fd_resource_ubwc_enabled(rsc
, psurf
->u
.tex
.level
))
319 mrts_ubwc_enable
|= 1 << i
;
322 cntl
|= A6XX_RB_RENDER_CNTL_UNK4
;
324 cntl
|= A6XX_RB_RENDER_CNTL_BINNING
;
326 OUT_PKT7(ring
, CP_REG_WRITE
, 3);
328 OUT_RING(ring
, REG_A6XX_RB_RENDER_CNTL
);
329 OUT_RING(ring
, cntl
|
330 COND(depth_ubwc_enable
, A6XX_RB_RENDER_CNTL_FLAG_DEPTH
) |
331 A6XX_RB_RENDER_CNTL_FLAG_MRTS(mrts_ubwc_enable
));
334 #define VSC_DATA_SIZE(pitch) ((pitch) * 32 + 0x100) /* extra size to store VSC_SIZE */
335 #define VSC_DATA2_SIZE(pitch) ((pitch) * 32)
338 update_vsc_pipe(struct fd_batch
*batch
)
340 struct fd_context
*ctx
= batch
->ctx
;
341 struct fd6_context
*fd6_ctx
= fd6_context(ctx
);
342 struct fd_gmem_stateobj
*gmem
= &ctx
->gmem
;
343 struct fd_ringbuffer
*ring
= batch
->gmem
;
347 if (!fd6_ctx
->vsc_data
) {
348 fd6_ctx
->vsc_data
= fd_bo_new(ctx
->screen
->dev
,
349 VSC_DATA_SIZE(fd6_ctx
->vsc_data_pitch
),
350 DRM_FREEDRENO_GEM_TYPE_KMEM
, "vsc_data");
353 if (!fd6_ctx
->vsc_data2
) {
354 fd6_ctx
->vsc_data2
= fd_bo_new(ctx
->screen
->dev
,
355 VSC_DATA2_SIZE(fd6_ctx
->vsc_data2_pitch
),
356 DRM_FREEDRENO_GEM_TYPE_KMEM
, "vsc_data2");
359 OUT_PKT4(ring
, REG_A6XX_VSC_BIN_SIZE
, 3);
360 OUT_RING(ring
, A6XX_VSC_BIN_SIZE_WIDTH(gmem
->bin_w
) |
361 A6XX_VSC_BIN_SIZE_HEIGHT(gmem
->bin_h
));
362 OUT_RELOCW(ring
, fd6_ctx
->vsc_data
,
363 32 * fd6_ctx
->vsc_data_pitch
, 0, 0); /* VSC_SIZE_ADDRESS_LO/HI */
365 OUT_PKT4(ring
, REG_A6XX_VSC_BIN_COUNT
, 1);
366 OUT_RING(ring
, A6XX_VSC_BIN_COUNT_NX(gmem
->nbins_x
) |
367 A6XX_VSC_BIN_COUNT_NY(gmem
->nbins_y
));
369 OUT_PKT4(ring
, REG_A6XX_VSC_PIPE_CONFIG_REG(0), 32);
370 for (i
= 0; i
< 32; i
++) {
371 struct fd_vsc_pipe
*pipe
= &ctx
->vsc_pipe
[i
];
372 OUT_RING(ring
, A6XX_VSC_PIPE_CONFIG_REG_X(pipe
->x
) |
373 A6XX_VSC_PIPE_CONFIG_REG_Y(pipe
->y
) |
374 A6XX_VSC_PIPE_CONFIG_REG_W(pipe
->w
) |
375 A6XX_VSC_PIPE_CONFIG_REG_H(pipe
->h
));
378 OUT_PKT4(ring
, REG_A6XX_VSC_PIPE_DATA2_ADDRESS_LO
, 4);
379 OUT_RELOCW(ring
, fd6_ctx
->vsc_data2
, 0, 0, 0);
380 OUT_RING(ring
, fd6_ctx
->vsc_data2_pitch
);
381 OUT_RING(ring
, fd_bo_size(fd6_ctx
->vsc_data2
));
383 OUT_PKT4(ring
, REG_A6XX_VSC_PIPE_DATA_ADDRESS_LO
, 4);
384 OUT_RELOCW(ring
, fd6_ctx
->vsc_data
, 0, 0, 0);
385 OUT_RING(ring
, fd6_ctx
->vsc_data_pitch
);
386 OUT_RING(ring
, fd_bo_size(fd6_ctx
->vsc_data
));
389 /* TODO we probably have more than 8 scratch regs.. although the first
390 * 8 is what kernel dumps, and it is kinda useful to be able to see
391 * the value in kernel traces
393 #define OVERFLOW_FLAG_REG REG_A6XX_CP_SCRATCH_REG(0)
396 * If overflow is detected, either 0x1 (VSC_DATA overflow) or 0x3
397 * (VSC_DATA2 overflow) plus the size of the overflowed buffer is
398 * written to control->vsc_overflow. This allows the CPU to
399 * detect which buffer overflowed (and, since the current size is
400 * encoded as well, this protects against already-submitted but
401 * not executed batches from fooling the CPU into increasing the
402 * size again unnecessarily).
404 * To conditionally use VSC data in draw pass only if there is no
405 * overflow, we use a scratch reg (OVERFLOW_FLAG_REG) to hold 1
406 * if no overflow, or 0 in case of overflow. The value is inverted
407 * to make the CP_COND_REG_EXEC stuff easier.
410 emit_vsc_overflow_test(struct fd_batch
*batch
)
412 struct fd_ringbuffer
*ring
= batch
->gmem
;
413 struct fd_gmem_stateobj
*gmem
= &batch
->ctx
->gmem
;
414 struct fd6_context
*fd6_ctx
= fd6_context(batch
->ctx
);
416 debug_assert((fd6_ctx
->vsc_data_pitch
& 0x3) == 0);
417 debug_assert((fd6_ctx
->vsc_data2_pitch
& 0x3) == 0);
419 /* Clear vsc_scratch: */
420 OUT_PKT7(ring
, CP_MEM_WRITE
, 3);
421 OUT_RELOCW(ring
, control_ptr(fd6_ctx
, vsc_scratch
));
424 /* Check for overflow, write vsc_scratch if detected: */
425 for (int i
= 0; i
< gmem
->num_vsc_pipes
; i
++) {
426 OUT_PKT7(ring
, CP_COND_WRITE5
, 8);
427 OUT_RING(ring
, CP_COND_WRITE5_0_FUNCTION(WRITE_GE
) |
428 CP_COND_WRITE5_0_WRITE_MEMORY
);
429 OUT_RING(ring
, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_SIZE_REG(i
)));
430 OUT_RING(ring
, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
431 OUT_RING(ring
, CP_COND_WRITE5_3_REF(fd6_ctx
->vsc_data_pitch
));
432 OUT_RING(ring
, CP_COND_WRITE5_4_MASK(~0));
433 OUT_RELOCW(ring
, control_ptr(fd6_ctx
, vsc_scratch
)); /* WRITE_ADDR_LO/HI */
434 OUT_RING(ring
, CP_COND_WRITE5_7_WRITE_DATA(1 + fd6_ctx
->vsc_data_pitch
));
436 OUT_PKT7(ring
, CP_COND_WRITE5
, 8);
437 OUT_RING(ring
, CP_COND_WRITE5_0_FUNCTION(WRITE_GE
) |
438 CP_COND_WRITE5_0_WRITE_MEMORY
);
439 OUT_RING(ring
, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_SIZE2_REG(i
)));
440 OUT_RING(ring
, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
441 OUT_RING(ring
, CP_COND_WRITE5_3_REF(fd6_ctx
->vsc_data2_pitch
));
442 OUT_RING(ring
, CP_COND_WRITE5_4_MASK(~0));
443 OUT_RELOCW(ring
, control_ptr(fd6_ctx
, vsc_scratch
)); /* WRITE_ADDR_LO/HI */
444 OUT_RING(ring
, CP_COND_WRITE5_7_WRITE_DATA(3 + fd6_ctx
->vsc_data2_pitch
));
447 OUT_PKT7(ring
, CP_WAIT_MEM_WRITES
, 0);
449 OUT_PKT7(ring
, CP_WAIT_FOR_ME
, 0);
451 OUT_PKT7(ring
, CP_MEM_TO_REG
, 3);
452 OUT_RING(ring
, CP_MEM_TO_REG_0_REG(OVERFLOW_FLAG_REG
) |
453 CP_MEM_TO_REG_0_CNT(1 - 1));
454 OUT_RELOC(ring
, control_ptr(fd6_ctx
, vsc_scratch
)); /* SRC_LO/HI */
457 * This is a bit awkward, we really want a way to invert the
458 * CP_REG_TEST/CP_COND_REG_EXEC logic, so that we can conditionally
459 * execute cmds to use hwbinning when a bit is *not* set. This
460 * dance is to invert OVERFLOW_FLAG_REG
462 * A CP_NOP packet is used to skip executing the 'else' clause
466 BEGIN_RING(ring
, 10); /* ensure if/else doesn't get split */
468 /* b0 will be set if VSC_DATA or VSC_DATA2 overflow: */
469 OUT_PKT7(ring
, CP_REG_TEST
, 1);
470 OUT_RING(ring
, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG
) |
471 A6XX_CP_REG_TEST_0_BIT(0) |
472 A6XX_CP_REG_TEST_0_UNK25
);
474 OUT_PKT7(ring
, CP_COND_REG_EXEC
, 2);
475 OUT_RING(ring
, 0x10000000);
476 OUT_RING(ring
, 7); /* conditionally execute next 7 dwords */
480 * On overflow, mirror the value to control->vsc_overflow
481 * which CPU is checking to detect overflow (see
482 * check_vsc_overflow())
484 OUT_PKT7(ring
, CP_REG_TO_MEM
, 3);
485 OUT_RING(ring
, CP_REG_TO_MEM_0_REG(OVERFLOW_FLAG_REG
) |
486 CP_REG_TO_MEM_0_CNT(1 - 1));
487 OUT_RELOCW(ring
, control_ptr(fd6_ctx
, vsc_overflow
));
489 OUT_PKT4(ring
, OVERFLOW_FLAG_REG
, 1);
492 OUT_PKT7(ring
, CP_NOP
, 2); /* skip 'else' when 'if' is taken */
494 OUT_PKT4(ring
, OVERFLOW_FLAG_REG
, 1);
500 check_vsc_overflow(struct fd_context
*ctx
)
502 struct fd6_context
*fd6_ctx
= fd6_context(ctx
);
503 struct fd6_control
*control
= fd_bo_map(fd6_ctx
->control_mem
);
504 uint32_t vsc_overflow
= control
->vsc_overflow
;
509 /* clear overflow flag: */
510 control
->vsc_overflow
= 0;
512 unsigned buffer
= vsc_overflow
& 0x3;
513 unsigned size
= vsc_overflow
& ~0x3;
516 /* VSC_PIPE_DATA overflow: */
518 if (size
< fd6_ctx
->vsc_data_pitch
) {
519 /* we've already increased the size, this overflow is
520 * from a batch submitted before resize, but executed
526 fd_bo_del(fd6_ctx
->vsc_data
);
527 fd6_ctx
->vsc_data
= NULL
;
528 fd6_ctx
->vsc_data_pitch
*= 2;
530 debug_printf("resized VSC_DATA_PITCH to: 0x%x\n", fd6_ctx
->vsc_data_pitch
);
532 } else if (buffer
== 0x3) {
533 /* VSC_PIPE_DATA2 overflow: */
535 if (size
< fd6_ctx
->vsc_data2_pitch
) {
536 /* we've already increased the size */
540 fd_bo_del(fd6_ctx
->vsc_data2
);
541 fd6_ctx
->vsc_data2
= NULL
;
542 fd6_ctx
->vsc_data2_pitch
*= 2;
544 debug_printf("resized VSC_DATA2_PITCH to: 0x%x\n", fd6_ctx
->vsc_data2_pitch
);
547 /* NOTE: it's possible, for example, for overflow to corrupt the
548 * control page. I mostly just see this hit if I set initial VSC
549 * buffer size extremely small. Things still seem to recover,
550 * but maybe we should pre-emptively realloc vsc_data/vsc_data2
551 * and hope for different memory placement?
553 DBG("invalid vsc_overflow value: 0x%08x", vsc_overflow
);
558 * Emit conditional CP_INDIRECT_BRANCH based on VSC_STATE[p], ie. the IB
559 * is skipped for tiles that have no visible geometry.
562 emit_conditional_ib(struct fd_batch
*batch
, struct fd_tile
*tile
,
563 struct fd_ringbuffer
*target
)
565 struct fd_ringbuffer
*ring
= batch
->gmem
;
567 if (target
->cur
== target
->start
)
570 emit_marker6(ring
, 6);
572 unsigned count
= fd_ringbuffer_cmd_count(target
);
574 BEGIN_RING(ring
, 5 + 4 * count
); /* ensure conditional doesn't get split */
576 OUT_PKT7(ring
, CP_REG_TEST
, 1);
577 OUT_RING(ring
, A6XX_CP_REG_TEST_0_REG(REG_A6XX_VSC_STATE_REG(tile
->p
)) |
578 A6XX_CP_REG_TEST_0_BIT(tile
->n
) |
579 A6XX_CP_REG_TEST_0_UNK25
);
581 OUT_PKT7(ring
, CP_COND_REG_EXEC
, 2);
582 OUT_RING(ring
, 0x10000000);
583 OUT_RING(ring
, 4 * count
); /* conditionally execute next 4*count dwords */
585 for (unsigned i
= 0; i
< count
; i
++) {
587 OUT_PKT7(ring
, CP_INDIRECT_BUFFER
, 3);
588 dwords
= fd_ringbuffer_emit_reloc_ring_full(ring
, target
, i
) / 4;
590 OUT_RING(ring
, dwords
);
593 emit_marker6(ring
, 6);
597 set_scissor(struct fd_ringbuffer
*ring
, uint32_t x1
, uint32_t y1
, uint32_t x2
, uint32_t y2
)
599 OUT_PKT4(ring
, REG_A6XX_GRAS_SC_WINDOW_SCISSOR_TL
, 2);
600 OUT_RING(ring
, A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X(x1
) |
601 A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(y1
));
602 OUT_RING(ring
, A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X(x2
) |
603 A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(y2
));
605 OUT_PKT4(ring
, REG_A6XX_GRAS_RESOLVE_CNTL_1
, 2);
606 OUT_RING(ring
, A6XX_GRAS_RESOLVE_CNTL_1_X(x1
) |
607 A6XX_GRAS_RESOLVE_CNTL_1_Y(y1
));
608 OUT_RING(ring
, A6XX_GRAS_RESOLVE_CNTL_2_X(x2
) |
609 A6XX_GRAS_RESOLVE_CNTL_2_Y(y2
));
613 set_bin_size(struct fd_ringbuffer
*ring
, uint32_t w
, uint32_t h
, uint32_t flag
)
615 OUT_PKT4(ring
, REG_A6XX_GRAS_BIN_CONTROL
, 1);
616 OUT_RING(ring
, A6XX_GRAS_BIN_CONTROL_BINW(w
) |
617 A6XX_GRAS_BIN_CONTROL_BINH(h
) | flag
);
619 OUT_PKT4(ring
, REG_A6XX_RB_BIN_CONTROL
, 1);
620 OUT_RING(ring
, A6XX_RB_BIN_CONTROL_BINW(w
) |
621 A6XX_RB_BIN_CONTROL_BINH(h
) | flag
);
623 /* no flag for RB_BIN_CONTROL2... */
624 OUT_PKT4(ring
, REG_A6XX_RB_BIN_CONTROL2
, 1);
625 OUT_RING(ring
, A6XX_RB_BIN_CONTROL2_BINW(w
) |
626 A6XX_RB_BIN_CONTROL2_BINH(h
));
630 emit_binning_pass(struct fd_batch
*batch
)
632 struct fd_ringbuffer
*ring
= batch
->gmem
;
633 struct fd_gmem_stateobj
*gmem
= &batch
->ctx
->gmem
;
634 struct fd6_context
*fd6_ctx
= fd6_context(batch
->ctx
);
636 uint32_t x1
= gmem
->minx
;
637 uint32_t y1
= gmem
->miny
;
638 uint32_t x2
= gmem
->minx
+ gmem
->width
- 1;
639 uint32_t y2
= gmem
->miny
+ gmem
->height
- 1;
641 debug_assert(!batch
->tessellation
);
643 set_scissor(ring
, x1
, y1
, x2
, y2
);
645 emit_marker6(ring
, 7);
646 OUT_PKT7(ring
, CP_SET_MARKER
, 1);
647 OUT_RING(ring
, A6XX_CP_SET_MARKER_0_MODE(RM6_BINNING
));
648 emit_marker6(ring
, 7);
650 OUT_PKT7(ring
, CP_SET_VISIBILITY_OVERRIDE
, 1);
653 OUT_PKT7(ring
, CP_SET_MODE
, 1);
658 OUT_PKT4(ring
, REG_A6XX_VFD_MODE_CNTL
, 1);
659 OUT_RING(ring
, A6XX_VFD_MODE_CNTL_BINNING_PASS
);
661 update_vsc_pipe(batch
);
663 OUT_PKT4(ring
, REG_A6XX_PC_UNKNOWN_9805
, 1);
664 OUT_RING(ring
, fd6_ctx
->magic
.PC_UNKNOWN_9805
);
666 OUT_PKT4(ring
, REG_A6XX_SP_UNKNOWN_A0F8
, 1);
667 OUT_RING(ring
, fd6_ctx
->magic
.SP_UNKNOWN_A0F8
);
669 OUT_PKT7(ring
, CP_EVENT_WRITE
, 1);
670 OUT_RING(ring
, UNK_2C
);
672 OUT_PKT4(ring
, REG_A6XX_RB_WINDOW_OFFSET
, 1);
673 OUT_RING(ring
, A6XX_RB_WINDOW_OFFSET_X(0) |
674 A6XX_RB_WINDOW_OFFSET_Y(0));
676 OUT_PKT4(ring
, REG_A6XX_SP_TP_WINDOW_OFFSET
, 1);
677 OUT_RING(ring
, A6XX_SP_TP_WINDOW_OFFSET_X(0) |
678 A6XX_SP_TP_WINDOW_OFFSET_Y(0));
680 /* emit IB to binning drawcmds: */
681 fd6_emit_ib(ring
, batch
->draw
);
685 OUT_PKT7(ring
, CP_SET_DRAW_STATE
, 3);
686 OUT_RING(ring
, CP_SET_DRAW_STATE__0_COUNT(0) |
687 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
688 CP_SET_DRAW_STATE__0_GROUP_ID(0));
689 OUT_RING(ring
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
690 OUT_RING(ring
, CP_SET_DRAW_STATE__2_ADDR_HI(0));
692 OUT_PKT7(ring
, CP_EVENT_WRITE
, 1);
693 OUT_RING(ring
, UNK_2D
);
695 fd6_cache_inv(batch
, ring
);
696 fd6_cache_flush(batch
, ring
);
699 OUT_PKT7(ring
, CP_WAIT_FOR_ME
, 0);
701 emit_vsc_overflow_test(batch
);
703 OUT_PKT7(ring
, CP_SET_VISIBILITY_OVERRIDE
, 1);
706 OUT_PKT7(ring
, CP_SET_MODE
, 1);
711 OUT_PKT4(ring
, REG_A6XX_RB_CCU_CNTL
, 1);
712 OUT_RING(ring
, fd6_ctx
->magic
.RB_CCU_CNTL_gmem
);
716 emit_msaa(struct fd_ringbuffer
*ring
, unsigned nr
)
718 enum a3xx_msaa_samples samples
= fd_msaa_samples(nr
);
720 OUT_PKT4(ring
, REG_A6XX_SP_TP_RAS_MSAA_CNTL
, 2);
721 OUT_RING(ring
, A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(samples
));
722 OUT_RING(ring
, A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(samples
) |
723 COND(samples
== MSAA_ONE
, A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE
));
725 OUT_PKT4(ring
, REG_A6XX_GRAS_RAS_MSAA_CNTL
, 2);
726 OUT_RING(ring
, A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(samples
));
727 OUT_RING(ring
, A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(samples
) |
728 COND(samples
== MSAA_ONE
, A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE
));
730 OUT_PKT4(ring
, REG_A6XX_RB_RAS_MSAA_CNTL
, 2);
731 OUT_RING(ring
, A6XX_RB_RAS_MSAA_CNTL_SAMPLES(samples
));
732 OUT_RING(ring
, A6XX_RB_DEST_MSAA_CNTL_SAMPLES(samples
) |
733 COND(samples
== MSAA_ONE
, A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE
));
735 OUT_PKT4(ring
, REG_A6XX_RB_MSAA_CNTL
, 1);
736 OUT_RING(ring
, A6XX_RB_MSAA_CNTL_SAMPLES(samples
));
739 static void prepare_tile_setup_ib(struct fd_batch
*batch
);
740 static void prepare_tile_fini_ib(struct fd_batch
*batch
);
742 /* before first tile */
744 fd6_emit_tile_init(struct fd_batch
*batch
)
746 struct fd_context
*ctx
= batch
->ctx
;
747 struct fd_ringbuffer
*ring
= batch
->gmem
;
748 struct pipe_framebuffer_state
*pfb
= &batch
->framebuffer
;
749 struct fd_gmem_stateobj
*gmem
= &batch
->ctx
->gmem
;
751 fd6_emit_restore(batch
, ring
);
753 fd6_emit_lrz_flush(ring
);
755 if (batch
->lrz_clear
)
756 fd6_emit_ib(ring
, batch
->lrz_clear
);
758 fd6_cache_inv(batch
, ring
);
760 prepare_tile_setup_ib(batch
);
761 prepare_tile_fini_ib(batch
);
763 OUT_PKT7(ring
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
767 OUT_PKT4(ring
, REG_A6XX_RB_CCU_CNTL
, 1);
768 OUT_RING(ring
, fd6_context(ctx
)->magic
.RB_CCU_CNTL_gmem
);
770 emit_zs(ring
, pfb
->zsbuf
, &ctx
->gmem
);
771 emit_mrt(ring
, pfb
, &ctx
->gmem
);
772 emit_msaa(ring
, pfb
->samples
);
773 patch_fb_read(batch
);
775 if (use_hw_binning(batch
)) {
776 /* enable stream-out during binning pass: */
777 OUT_PKT4(ring
, REG_A6XX_VPC_SO_OVERRIDE
, 1);
780 set_bin_size(ring
, gmem
->bin_w
, gmem
->bin_h
,
781 A6XX_RB_BIN_CONTROL_BINNING_PASS
| 0x6000000);
782 update_render_cntl(batch
, pfb
, true);
783 emit_binning_pass(batch
);
785 /* and disable stream-out for draw pass: */
786 OUT_PKT4(ring
, REG_A6XX_VPC_SO_OVERRIDE
, 1);
787 OUT_RING(ring
, A6XX_VPC_SO_OVERRIDE_SO_DISABLE
);
790 * NOTE: even if we detect VSC overflow and disable use of
791 * visibility stream in draw pass, it is still safe to execute
792 * the reset of these cmds:
795 // NOTE a618 not setting .USE_VIZ .. from a quick check on a630, it
796 // does not appear that this bit changes much (ie. it isn't actually
797 // .USE_VIZ like previous gens)
798 set_bin_size(ring
, gmem
->bin_w
, gmem
->bin_h
,
799 A6XX_RB_BIN_CONTROL_USE_VIZ
| 0x6000000);
801 OUT_PKT4(ring
, REG_A6XX_VFD_MODE_CNTL
, 1);
804 OUT_PKT4(ring
, REG_A6XX_PC_UNKNOWN_9805
, 1);
805 OUT_RING(ring
, fd6_context(ctx
)->magic
.PC_UNKNOWN_9805
);
807 OUT_PKT4(ring
, REG_A6XX_SP_UNKNOWN_A0F8
, 1);
808 OUT_RING(ring
, fd6_context(ctx
)->magic
.SP_UNKNOWN_A0F8
);
810 OUT_PKT7(ring
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
813 /* no binning pass, so enable stream-out for draw pass:: */
814 OUT_PKT4(ring
, REG_A6XX_VPC_SO_OVERRIDE
, 1);
817 set_bin_size(ring
, gmem
->bin_w
, gmem
->bin_h
, 0x6000000);
820 update_render_cntl(batch
, pfb
, false);
824 set_window_offset(struct fd_ringbuffer
*ring
, uint32_t x1
, uint32_t y1
)
826 OUT_PKT4(ring
, REG_A6XX_RB_WINDOW_OFFSET
, 1);
827 OUT_RING(ring
, A6XX_RB_WINDOW_OFFSET_X(x1
) |
828 A6XX_RB_WINDOW_OFFSET_Y(y1
));
830 OUT_PKT4(ring
, REG_A6XX_RB_WINDOW_OFFSET2
, 1);
831 OUT_RING(ring
, A6XX_RB_WINDOW_OFFSET2_X(x1
) |
832 A6XX_RB_WINDOW_OFFSET2_Y(y1
));
834 OUT_PKT4(ring
, REG_A6XX_SP_WINDOW_OFFSET
, 1);
835 OUT_RING(ring
, A6XX_SP_WINDOW_OFFSET_X(x1
) |
836 A6XX_SP_WINDOW_OFFSET_Y(y1
));
838 OUT_PKT4(ring
, REG_A6XX_SP_TP_WINDOW_OFFSET
, 1);
839 OUT_RING(ring
, A6XX_SP_TP_WINDOW_OFFSET_X(x1
) |
840 A6XX_SP_TP_WINDOW_OFFSET_Y(y1
));
843 /* before mem2gmem */
845 fd6_emit_tile_prep(struct fd_batch
*batch
, struct fd_tile
*tile
)
847 struct fd_context
*ctx
= batch
->ctx
;
848 struct fd6_context
*fd6_ctx
= fd6_context(ctx
);
849 struct fd_ringbuffer
*ring
= batch
->gmem
;
851 emit_marker6(ring
, 7);
852 OUT_PKT7(ring
, CP_SET_MARKER
, 1);
853 OUT_RING(ring
, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM
) | 0x10);
854 emit_marker6(ring
, 7);
856 uint32_t x1
= tile
->xoff
;
857 uint32_t y1
= tile
->yoff
;
858 uint32_t x2
= tile
->xoff
+ tile
->bin_w
- 1;
859 uint32_t y2
= tile
->yoff
+ tile
->bin_h
- 1;
861 set_scissor(ring
, x1
, y1
, x2
, y2
);
863 if (use_hw_binning(batch
)) {
864 struct fd_vsc_pipe
*pipe
= &ctx
->vsc_pipe
[tile
->p
];
866 OUT_PKT7(ring
, CP_WAIT_FOR_ME
, 0);
868 OUT_PKT7(ring
, CP_SET_MODE
, 1);
872 * Conditionally execute if no VSC overflow:
875 BEGIN_RING(ring
, 18); /* ensure if/else doesn't get split */
877 OUT_PKT7(ring
, CP_REG_TEST
, 1);
878 OUT_RING(ring
, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG
) |
879 A6XX_CP_REG_TEST_0_BIT(0) |
880 A6XX_CP_REG_TEST_0_UNK25
);
882 OUT_PKT7(ring
, CP_COND_REG_EXEC
, 2);
883 OUT_RING(ring
, 0x10000000);
884 OUT_RING(ring
, 11); /* conditionally execute next 11 dwords */
886 /* if (no overflow) */ {
887 OUT_PKT7(ring
, CP_SET_BIN_DATA5
, 7);
888 OUT_RING(ring
, CP_SET_BIN_DATA5_0_VSC_SIZE(pipe
->w
* pipe
->h
) |
889 CP_SET_BIN_DATA5_0_VSC_N(tile
->n
));
890 OUT_RELOC(ring
, fd6_ctx
->vsc_data
, /* VSC_PIPE[p].DATA_ADDRESS */
891 (tile
->p
* fd6_ctx
->vsc_data_pitch
), 0, 0);
892 OUT_RELOC(ring
, fd6_ctx
->vsc_data
, /* VSC_SIZE_ADDRESS + (p * 4) */
893 (tile
->p
* 4) + (32 * fd6_ctx
->vsc_data_pitch
), 0, 0);
894 OUT_RELOC(ring
, fd6_ctx
->vsc_data2
,
895 (tile
->p
* fd6_ctx
->vsc_data2_pitch
), 0, 0);
897 OUT_PKT7(ring
, CP_SET_VISIBILITY_OVERRIDE
, 1);
900 /* use a NOP packet to skip over the 'else' side: */
901 OUT_PKT7(ring
, CP_NOP
, 2);
903 OUT_PKT7(ring
, CP_SET_VISIBILITY_OVERRIDE
, 1);
907 set_window_offset(ring
, x1
, y1
);
909 struct fd_gmem_stateobj
*gmem
= &batch
->ctx
->gmem
;
910 set_bin_size(ring
, gmem
->bin_w
, gmem
->bin_h
, 0x6000000);
912 OUT_PKT7(ring
, CP_SET_MODE
, 1);
915 OUT_PKT4(ring
, REG_A6XX_RB_UNKNOWN_8804
, 1);
918 OUT_PKT4(ring
, REG_A6XX_SP_TP_UNKNOWN_B304
, 1);
921 OUT_PKT4(ring
, REG_A6XX_GRAS_UNKNOWN_80A4
, 1);
924 set_window_offset(ring
, x1
, y1
);
926 OUT_PKT7(ring
, CP_SET_VISIBILITY_OVERRIDE
, 1);
929 OUT_PKT7(ring
, CP_SET_MODE
, 1);
935 set_blit_scissor(struct fd_batch
*batch
, struct fd_ringbuffer
*ring
)
937 struct pipe_scissor_state blit_scissor
;
938 struct pipe_framebuffer_state
*pfb
= &batch
->framebuffer
;
940 blit_scissor
.minx
= 0;
941 blit_scissor
.miny
= 0;
942 blit_scissor
.maxx
= align(pfb
->width
, batch
->ctx
->screen
->gmem_alignw
);
943 blit_scissor
.maxy
= align(pfb
->height
, batch
->ctx
->screen
->gmem_alignh
);
945 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_SCISSOR_TL
, 2);
947 A6XX_RB_BLIT_SCISSOR_TL_X(blit_scissor
.minx
) |
948 A6XX_RB_BLIT_SCISSOR_TL_Y(blit_scissor
.miny
));
950 A6XX_RB_BLIT_SCISSOR_BR_X(blit_scissor
.maxx
- 1) |
951 A6XX_RB_BLIT_SCISSOR_BR_Y(blit_scissor
.maxy
- 1));
955 emit_blit(struct fd_batch
*batch
,
956 struct fd_ringbuffer
*ring
,
958 struct pipe_surface
*psurf
,
961 struct fdl_slice
*slice
;
962 struct fd_resource
*rsc
= fd_resource(psurf
->texture
);
963 enum pipe_format pfmt
= psurf
->format
;
967 debug_assert(psurf
->u
.tex
.first_layer
== psurf
->u
.tex
.last_layer
);
969 /* separate stencil case: */
972 pfmt
= rsc
->base
.format
;
975 slice
= fd_resource_slice(rsc
, psurf
->u
.tex
.level
);
976 offset
= fd_resource_offset(rsc
, psurf
->u
.tex
.level
,
977 psurf
->u
.tex
.first_layer
);
978 ubwc_enabled
= fd_resource_ubwc_enabled(rsc
, psurf
->u
.tex
.level
);
980 debug_assert(psurf
->u
.tex
.first_layer
== psurf
->u
.tex
.last_layer
);
982 enum a6xx_color_fmt format
= fd6_pipe2color(pfmt
);
983 uint32_t stride
= slice
->pitch
* rsc
->layout
.cpp
;
984 uint32_t size
= slice
->size0
;
985 enum a3xx_color_swap swap
= rsc
->layout
.tile_mode
? WZYX
: fd6_pipe2swap(pfmt
);
986 enum a3xx_msaa_samples samples
=
987 fd_msaa_samples(rsc
->base
.nr_samples
);
988 uint32_t tile_mode
= fd_resource_tile_mode(&rsc
->base
, psurf
->u
.tex
.level
);
990 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_DST_INFO
, 5);
992 A6XX_RB_BLIT_DST_INFO_TILE_MODE(tile_mode
) |
993 A6XX_RB_BLIT_DST_INFO_SAMPLES(samples
) |
994 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(format
) |
995 A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(swap
) |
996 COND(ubwc_enabled
, A6XX_RB_BLIT_DST_INFO_FLAGS
));
997 OUT_RELOCW(ring
, rsc
->bo
, offset
, 0, 0); /* RB_BLIT_DST_LO/HI */
998 OUT_RING(ring
, A6XX_RB_BLIT_DST_PITCH(stride
).value
);
999 OUT_RING(ring
, A6XX_RB_BLIT_DST_ARRAY_PITCH(size
).value
);
1001 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_BASE_GMEM
, 1);
1002 OUT_RING(ring
, base
);
1005 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_FLAG_DST_LO
, 3);
1006 fd6_emit_flag_reference(ring
, rsc
,
1007 psurf
->u
.tex
.level
, psurf
->u
.tex
.first_layer
);
1010 fd6_emit_blit(batch
, ring
);
1014 emit_restore_blit(struct fd_batch
*batch
,
1015 struct fd_ringbuffer
*ring
,
1017 struct pipe_surface
*psurf
,
1021 bool stencil
= false;
1024 case FD_BUFFER_COLOR
:
1025 info
|= A6XX_RB_BLIT_INFO_UNK0
;
1027 case FD_BUFFER_STENCIL
:
1028 info
|= A6XX_RB_BLIT_INFO_UNK0
;
1031 case FD_BUFFER_DEPTH
:
1032 info
|= A6XX_RB_BLIT_INFO_DEPTH
| A6XX_RB_BLIT_INFO_UNK0
;
1036 if (util_format_is_pure_integer(psurf
->format
))
1037 info
|= A6XX_RB_BLIT_INFO_INTEGER
;
1039 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_INFO
, 1);
1040 OUT_RING(ring
, info
| A6XX_RB_BLIT_INFO_GMEM
);
1042 emit_blit(batch
, ring
, base
, psurf
, stencil
);
1046 emit_clears(struct fd_batch
*batch
, struct fd_ringbuffer
*ring
)
1048 struct pipe_framebuffer_state
*pfb
= &batch
->framebuffer
;
1049 struct fd_gmem_stateobj
*gmem
= &batch
->ctx
->gmem
;
1050 enum a3xx_msaa_samples samples
= fd_msaa_samples(pfb
->samples
);
1052 uint32_t buffers
= batch
->fast_cleared
;
1054 if (buffers
& PIPE_CLEAR_COLOR
) {
1056 for (int i
= 0; i
< pfb
->nr_cbufs
; i
++) {
1057 union pipe_color_union
*color
= &batch
->clear_color
[i
];
1058 union util_color uc
= {0};
1063 if (!(buffers
& (PIPE_CLEAR_COLOR0
<< i
)))
1066 enum pipe_format pfmt
= pfb
->cbufs
[i
]->format
;
1068 // XXX I think RB_CLEAR_COLOR_DWn wants to take into account SWAP??
1069 union pipe_color_union swapped
;
1070 switch (fd6_pipe2swap(pfmt
)) {
1072 swapped
.ui
[0] = color
->ui
[0];
1073 swapped
.ui
[1] = color
->ui
[1];
1074 swapped
.ui
[2] = color
->ui
[2];
1075 swapped
.ui
[3] = color
->ui
[3];
1078 swapped
.ui
[2] = color
->ui
[0];
1079 swapped
.ui
[1] = color
->ui
[1];
1080 swapped
.ui
[0] = color
->ui
[2];
1081 swapped
.ui
[3] = color
->ui
[3];
1084 swapped
.ui
[3] = color
->ui
[0];
1085 swapped
.ui
[0] = color
->ui
[1];
1086 swapped
.ui
[1] = color
->ui
[2];
1087 swapped
.ui
[2] = color
->ui
[3];
1090 swapped
.ui
[3] = color
->ui
[0];
1091 swapped
.ui
[2] = color
->ui
[1];
1092 swapped
.ui
[1] = color
->ui
[2];
1093 swapped
.ui
[0] = color
->ui
[3];
1097 if (util_format_is_pure_uint(pfmt
)) {
1098 util_format_write_4ui(pfmt
, swapped
.ui
, 0, &uc
, 0, 0, 0, 1, 1);
1099 } else if (util_format_is_pure_sint(pfmt
)) {
1100 util_format_write_4i(pfmt
, swapped
.i
, 0, &uc
, 0, 0, 0, 1, 1);
1102 util_pack_color(swapped
.f
, pfmt
, &uc
);
1105 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_DST_INFO
, 1);
1106 OUT_RING(ring
, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR
) |
1107 A6XX_RB_BLIT_DST_INFO_SAMPLES(samples
) |
1108 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(fd6_pipe2color(pfmt
)));
1110 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_INFO
, 1);
1111 OUT_RING(ring
, A6XX_RB_BLIT_INFO_GMEM
|
1112 A6XX_RB_BLIT_INFO_CLEAR_MASK(0xf));
1114 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_BASE_GMEM
, 1);
1115 OUT_RING(ring
, gmem
->cbuf_base
[i
]);
1117 OUT_PKT4(ring
, REG_A6XX_RB_UNKNOWN_88D0
, 1);
1120 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0
, 4);
1121 OUT_RING(ring
, uc
.ui
[0]);
1122 OUT_RING(ring
, uc
.ui
[1]);
1123 OUT_RING(ring
, uc
.ui
[2]);
1124 OUT_RING(ring
, uc
.ui
[3]);
1126 fd6_emit_blit(batch
, ring
);
1130 const bool has_depth
= pfb
->zsbuf
;
1131 const bool has_separate_stencil
=
1132 has_depth
&& fd_resource(pfb
->zsbuf
->texture
)->stencil
;
1134 /* First clear depth or combined depth/stencil. */
1135 if ((has_depth
&& (buffers
& PIPE_CLEAR_DEPTH
)) ||
1136 (!has_separate_stencil
&& (buffers
& PIPE_CLEAR_STENCIL
))) {
1137 enum pipe_format pfmt
= pfb
->zsbuf
->format
;
1138 uint32_t clear_value
;
1141 if (has_separate_stencil
) {
1142 pfmt
= util_format_get_depth_only(pfb
->zsbuf
->format
);
1143 clear_value
= util_pack_z(pfmt
, batch
->clear_depth
);
1145 pfmt
= pfb
->zsbuf
->format
;
1146 clear_value
= util_pack_z_stencil(pfmt
, batch
->clear_depth
,
1147 batch
->clear_stencil
);
1150 if (buffers
& PIPE_CLEAR_DEPTH
)
1153 if (!has_separate_stencil
&& (buffers
& PIPE_CLEAR_STENCIL
))
1156 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_DST_INFO
, 1);
1157 OUT_RING(ring
, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR
) |
1158 A6XX_RB_BLIT_DST_INFO_SAMPLES(samples
) |
1159 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(fd6_pipe2color(pfmt
)));
1161 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_INFO
, 1);
1162 OUT_RING(ring
, A6XX_RB_BLIT_INFO_GMEM
|
1163 // XXX UNK0 for separate stencil ??
1164 A6XX_RB_BLIT_INFO_DEPTH
|
1165 A6XX_RB_BLIT_INFO_CLEAR_MASK(mask
));
1167 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_BASE_GMEM
, 1);
1168 OUT_RING(ring
, gmem
->zsbuf_base
[0]);
1170 OUT_PKT4(ring
, REG_A6XX_RB_UNKNOWN_88D0
, 1);
1173 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0
, 1);
1174 OUT_RING(ring
, clear_value
);
1176 fd6_emit_blit(batch
, ring
);
1179 /* Then clear the separate stencil buffer in case of 32 bit depth
1180 * formats with separate stencil. */
1181 if (has_separate_stencil
&& (buffers
& PIPE_CLEAR_STENCIL
)) {
1182 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_DST_INFO
, 1);
1183 OUT_RING(ring
, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR
) |
1184 A6XX_RB_BLIT_DST_INFO_SAMPLES(samples
) |
1185 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(RB6_R8_UINT
));
1187 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_INFO
, 1);
1188 OUT_RING(ring
, A6XX_RB_BLIT_INFO_GMEM
|
1189 //A6XX_RB_BLIT_INFO_UNK0 |
1190 A6XX_RB_BLIT_INFO_DEPTH
|
1191 A6XX_RB_BLIT_INFO_CLEAR_MASK(0x1));
1193 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_BASE_GMEM
, 1);
1194 OUT_RING(ring
, gmem
->zsbuf_base
[1]);
1196 OUT_PKT4(ring
, REG_A6XX_RB_UNKNOWN_88D0
, 1);
1199 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0
, 1);
1200 OUT_RING(ring
, batch
->clear_stencil
& 0xff);
1202 fd6_emit_blit(batch
, ring
);
1207 * transfer from system memory to gmem
1210 emit_restore_blits(struct fd_batch
*batch
, struct fd_ringbuffer
*ring
)
1212 struct fd_context
*ctx
= batch
->ctx
;
1213 struct fd_gmem_stateobj
*gmem
= &ctx
->gmem
;
1214 struct pipe_framebuffer_state
*pfb
= &batch
->framebuffer
;
1216 if (batch
->restore
& FD_BUFFER_COLOR
) {
1218 for (i
= 0; i
< pfb
->nr_cbufs
; i
++) {
1221 if (!(batch
->restore
& (PIPE_CLEAR_COLOR0
<< i
)))
1223 emit_restore_blit(batch
, ring
, gmem
->cbuf_base
[i
], pfb
->cbufs
[i
],
1228 if (batch
->restore
& (FD_BUFFER_DEPTH
| FD_BUFFER_STENCIL
)) {
1229 struct fd_resource
*rsc
= fd_resource(pfb
->zsbuf
->texture
);
1231 if (!rsc
->stencil
|| (batch
->restore
& FD_BUFFER_DEPTH
)) {
1232 emit_restore_blit(batch
, ring
, gmem
->zsbuf_base
[0], pfb
->zsbuf
,
1235 if (rsc
->stencil
&& (batch
->restore
& FD_BUFFER_STENCIL
)) {
1236 emit_restore_blit(batch
, ring
, gmem
->zsbuf_base
[1], pfb
->zsbuf
,
1243 prepare_tile_setup_ib(struct fd_batch
*batch
)
1245 batch
->tile_setup
= fd_submit_new_ringbuffer(batch
->submit
, 0x1000,
1246 FD_RINGBUFFER_STREAMING
);
1248 set_blit_scissor(batch
, batch
->tile_setup
);
1250 emit_restore_blits(batch
, batch
->tile_setup
);
1251 emit_clears(batch
, batch
->tile_setup
);
1255 * transfer from system memory to gmem
1258 fd6_emit_tile_mem2gmem(struct fd_batch
*batch
, struct fd_tile
*tile
)
1262 /* before IB to rendering cmds: */
1264 fd6_emit_tile_renderprep(struct fd_batch
*batch
, struct fd_tile
*tile
)
1266 if (batch
->fast_cleared
|| !use_hw_binning(batch
)) {
1267 fd6_emit_ib(batch
->gmem
, batch
->tile_setup
);
1269 emit_conditional_ib(batch
, tile
, batch
->tile_setup
);
1274 emit_resolve_blit(struct fd_batch
*batch
,
1275 struct fd_ringbuffer
*ring
,
1277 struct pipe_surface
*psurf
,
1281 bool stencil
= false;
1283 if (!fd_resource(psurf
->texture
)->valid
)
1287 case FD_BUFFER_COLOR
:
1289 case FD_BUFFER_STENCIL
:
1290 info
|= A6XX_RB_BLIT_INFO_UNK0
;
1293 case FD_BUFFER_DEPTH
:
1294 info
|= A6XX_RB_BLIT_INFO_DEPTH
;
1298 if (util_format_is_pure_integer(psurf
->format
))
1299 info
|= A6XX_RB_BLIT_INFO_INTEGER
;
1301 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_INFO
, 1);
1302 OUT_RING(ring
, info
);
1304 emit_blit(batch
, ring
, base
, psurf
, stencil
);
1308 * transfer from gmem to system memory (ie. normal RAM)
1312 prepare_tile_fini_ib(struct fd_batch
*batch
)
1314 struct fd_context
*ctx
= batch
->ctx
;
1315 struct fd_gmem_stateobj
*gmem
= &ctx
->gmem
;
1316 struct pipe_framebuffer_state
*pfb
= &batch
->framebuffer
;
1317 struct fd_ringbuffer
*ring
;
1319 batch
->tile_fini
= fd_submit_new_ringbuffer(batch
->submit
, 0x1000,
1320 FD_RINGBUFFER_STREAMING
);
1321 ring
= batch
->tile_fini
;
1323 set_blit_scissor(batch
, ring
);
1325 if (batch
->resolve
& (FD_BUFFER_DEPTH
| FD_BUFFER_STENCIL
)) {
1326 struct fd_resource
*rsc
= fd_resource(pfb
->zsbuf
->texture
);
1328 if (!rsc
->stencil
|| (batch
->resolve
& FD_BUFFER_DEPTH
)) {
1329 emit_resolve_blit(batch
, ring
,
1330 gmem
->zsbuf_base
[0], pfb
->zsbuf
,
1333 if (rsc
->stencil
&& (batch
->resolve
& FD_BUFFER_STENCIL
)) {
1334 emit_resolve_blit(batch
, ring
,
1335 gmem
->zsbuf_base
[1], pfb
->zsbuf
,
1340 if (batch
->resolve
& FD_BUFFER_COLOR
) {
1342 for (i
= 0; i
< pfb
->nr_cbufs
; i
++) {
1345 if (!(batch
->resolve
& (PIPE_CLEAR_COLOR0
<< i
)))
1347 emit_resolve_blit(batch
, ring
, gmem
->cbuf_base
[i
], pfb
->cbufs
[i
],
1354 fd6_emit_tile(struct fd_batch
*batch
, struct fd_tile
*tile
)
1356 if (!use_hw_binning(batch
)) {
1357 fd6_emit_ib(batch
->gmem
, batch
->draw
);
1359 emit_conditional_ib(batch
, tile
, batch
->draw
);
1364 fd6_emit_tile_gmem2mem(struct fd_batch
*batch
, struct fd_tile
*tile
)
1366 struct fd_ringbuffer
*ring
= batch
->gmem
;
1368 if (use_hw_binning(batch
)) {
1369 /* Conditionally execute if no VSC overflow: */
1371 BEGIN_RING(ring
, 7); /* ensure if/else doesn't get split */
1373 OUT_PKT7(ring
, CP_REG_TEST
, 1);
1374 OUT_RING(ring
, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG
) |
1375 A6XX_CP_REG_TEST_0_BIT(0) |
1376 A6XX_CP_REG_TEST_0_UNK25
);
1378 OUT_PKT7(ring
, CP_COND_REG_EXEC
, 2);
1379 OUT_RING(ring
, 0x10000000);
1380 OUT_RING(ring
, 2); /* conditionally execute next 2 dwords */
1382 /* if (no overflow) */ {
1383 OUT_PKT7(ring
, CP_SET_MARKER
, 1);
1384 OUT_RING(ring
, A6XX_CP_SET_MARKER_0_MODE(0x5) | 0x10);
1388 OUT_PKT7(ring
, CP_SET_DRAW_STATE
, 3);
1389 OUT_RING(ring
, CP_SET_DRAW_STATE__0_COUNT(0) |
1390 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
1391 CP_SET_DRAW_STATE__0_GROUP_ID(0));
1392 OUT_RING(ring
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1393 OUT_RING(ring
, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1395 OUT_PKT7(ring
, CP_SKIP_IB2_ENABLE_LOCAL
, 1);
1396 OUT_RING(ring
, 0x0);
1398 emit_marker6(ring
, 7);
1399 OUT_PKT7(ring
, CP_SET_MARKER
, 1);
1400 OUT_RING(ring
, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE
) | 0x10);
1401 emit_marker6(ring
, 7);
1403 if (batch
->fast_cleared
|| !use_hw_binning(batch
)) {
1404 fd6_emit_ib(batch
->gmem
, batch
->tile_fini
);
1406 emit_conditional_ib(batch
, tile
, batch
->tile_fini
);
1409 OUT_PKT7(ring
, CP_SET_MARKER
, 1);
1410 OUT_RING(ring
, A6XX_CP_SET_MARKER_0_MODE(0x7));
1414 fd6_emit_tile_fini(struct fd_batch
*batch
)
1416 struct fd_ringbuffer
*ring
= batch
->gmem
;
1418 OUT_PKT4(ring
, REG_A6XX_GRAS_LRZ_CNTL
, 1);
1419 OUT_RING(ring
, A6XX_GRAS_LRZ_CNTL_ENABLE
| A6XX_GRAS_LRZ_CNTL_UNK3
);
1421 fd6_emit_lrz_flush(ring
);
1423 fd6_event_write(batch
, ring
, CACHE_FLUSH_TS
, true);
1425 if (use_hw_binning(batch
)) {
1426 check_vsc_overflow(batch
->ctx
);
1431 emit_sysmem_clears(struct fd_batch
*batch
, struct fd_ringbuffer
*ring
)
1433 struct fd_context
*ctx
= batch
->ctx
;
1434 struct pipe_framebuffer_state
*pfb
= &batch
->framebuffer
;
1436 uint32_t buffers
= batch
->fast_cleared
;
1438 if (buffers
& PIPE_CLEAR_COLOR
) {
1439 for (int i
= 0; i
< pfb
->nr_cbufs
; i
++) {
1440 union pipe_color_union
*color
= &batch
->clear_color
[i
];
1445 if (!(buffers
& (PIPE_CLEAR_COLOR0
<< i
)))
1448 fd6_clear_surface(ctx
, ring
,
1449 pfb
->cbufs
[i
], pfb
->width
, pfb
->height
, color
);
1452 if (buffers
& (PIPE_CLEAR_DEPTH
| PIPE_CLEAR_STENCIL
)) {
1453 union pipe_color_union value
= {};
1455 const bool has_depth
= pfb
->zsbuf
;
1456 struct pipe_resource
*separate_stencil
=
1457 has_depth
&& fd_resource(pfb
->zsbuf
->texture
)->stencil
?
1458 &fd_resource(pfb
->zsbuf
->texture
)->stencil
->base
: NULL
;
1460 if ((has_depth
&& (buffers
& PIPE_CLEAR_DEPTH
)) ||
1461 (!separate_stencil
&& (buffers
& PIPE_CLEAR_STENCIL
))) {
1462 value
.f
[0] = batch
->clear_depth
;
1463 value
.ui
[1] = batch
->clear_stencil
;
1464 fd6_clear_surface(ctx
, ring
,
1465 pfb
->zsbuf
, pfb
->width
, pfb
->height
, &value
);
1468 if (separate_stencil
&& (buffers
& PIPE_CLEAR_STENCIL
)) {
1469 value
.ui
[0] = batch
->clear_stencil
;
1471 struct pipe_surface stencil_surf
= *pfb
->zsbuf
;
1472 stencil_surf
.texture
= separate_stencil
;
1474 fd6_clear_surface(ctx
, ring
,
1475 &stencil_surf
, pfb
->width
, pfb
->height
, &value
);
1479 fd6_event_write(batch
, ring
, 0x1d, true);
1483 setup_tess_buffers(struct fd_batch
*batch
, struct fd_ringbuffer
*ring
)
1485 struct fd_context
*ctx
= batch
->ctx
;
1487 batch
->tessfactor_bo
= fd_bo_new(ctx
->screen
->dev
,
1488 batch
->tessfactor_size
,
1489 DRM_FREEDRENO_GEM_TYPE_KMEM
, "tessfactor");
1491 batch
->tessparam_bo
= fd_bo_new(ctx
->screen
->dev
,
1492 batch
->tessparam_size
,
1493 DRM_FREEDRENO_GEM_TYPE_KMEM
, "tessparam");
1495 OUT_PKT4(ring
, REG_A6XX_PC_TESSFACTOR_ADDR_LO
, 2);
1496 OUT_RELOCW(ring
, batch
->tessfactor_bo
, 0, 0, 0);
1498 batch
->tess_addrs_constobj
->cur
= batch
->tess_addrs_constobj
->start
;
1499 OUT_RELOCW(batch
->tess_addrs_constobj
, batch
->tessparam_bo
, 0, 0, 0);
1500 OUT_RELOCW(batch
->tess_addrs_constobj
, batch
->tessfactor_bo
, 0, 0, 0);
1504 fd6_emit_sysmem_prep(struct fd_batch
*batch
)
1506 struct pipe_framebuffer_state
*pfb
= &batch
->framebuffer
;
1507 struct fd_ringbuffer
*ring
= batch
->gmem
;
1509 fd6_emit_restore(batch
, ring
);
1511 set_scissor(ring
, 0, 0, pfb
->width
- 1, pfb
->height
- 1);
1513 set_window_offset(ring
, 0, 0);
1515 set_bin_size(ring
, 0, 0, 0xc00000); /* 0xc00000 = BYPASS? */
1517 emit_sysmem_clears(batch
, ring
);
1519 fd6_emit_lrz_flush(ring
);
1521 emit_marker6(ring
, 7);
1522 OUT_PKT7(ring
, CP_SET_MARKER
, 1);
1523 OUT_RING(ring
, A6XX_CP_SET_MARKER_0_MODE(RM6_BYPASS
) | 0x10); /* | 0x10 ? */
1524 emit_marker6(ring
, 7);
1526 if (batch
->tessellation
)
1527 setup_tess_buffers(batch
, ring
);
1529 OUT_PKT7(ring
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1530 OUT_RING(ring
, 0x0);
1532 fd6_event_write(batch
, ring
, PC_CCU_INVALIDATE_COLOR
, false);
1533 fd6_cache_inv(batch
, ring
);
1535 fd_wfi(batch
, ring
);
1536 OUT_PKT4(ring
, REG_A6XX_RB_CCU_CNTL
, 1);
1537 OUT_RING(ring
, fd6_context(batch
->ctx
)->magic
.RB_CCU_CNTL_bypass
);
1539 /* enable stream-out, with sysmem there is only one pass: */
1540 OUT_PKT4(ring
, REG_A6XX_VPC_SO_OVERRIDE
, 1);
1543 OUT_PKT7(ring
, CP_SET_VISIBILITY_OVERRIDE
, 1);
1544 OUT_RING(ring
, 0x1);
1546 emit_zs(ring
, pfb
->zsbuf
, NULL
);
1547 emit_mrt(ring
, pfb
, NULL
);
1548 emit_msaa(ring
, pfb
->samples
);
1550 update_render_cntl(batch
, pfb
, false);
1554 fd6_emit_sysmem_fini(struct fd_batch
*batch
)
1556 struct fd_ringbuffer
*ring
= batch
->gmem
;
1558 OUT_PKT7(ring
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1559 OUT_RING(ring
, 0x0);
1561 fd6_emit_lrz_flush(ring
);
1563 fd6_event_write(batch
, ring
, UNK_1D
, true);
1567 fd6_gmem_init(struct pipe_context
*pctx
)
1569 struct fd_context
*ctx
= fd_context(pctx
);
1571 ctx
->emit_tile_init
= fd6_emit_tile_init
;
1572 ctx
->emit_tile_prep
= fd6_emit_tile_prep
;
1573 ctx
->emit_tile_mem2gmem
= fd6_emit_tile_mem2gmem
;
1574 ctx
->emit_tile_renderprep
= fd6_emit_tile_renderprep
;
1575 ctx
->emit_tile
= fd6_emit_tile
;
1576 ctx
->emit_tile_gmem2mem
= fd6_emit_tile_gmem2mem
;
1577 ctx
->emit_tile_fini
= fd6_emit_tile_fini
;
1578 ctx
->emit_sysmem_prep
= fd6_emit_sysmem_prep
;
1579 ctx
->emit_sysmem_fini
= fd6_emit_sysmem_fini
;