2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25 * Rob Clark <robclark@freedesktop.org>
30 #include "pipe/p_state.h"
31 #include "util/u_string.h"
32 #include "util/u_memory.h"
33 #include "util/u_inlines.h"
34 #include "util/u_format.h"
36 #include "freedreno_draw.h"
37 #include "freedreno_state.h"
38 #include "freedreno_resource.h"
41 #include "fd6_context.h"
44 #include "fd6_program.h"
45 #include "fd6_format.h"
48 /* some bits in common w/ a4xx: */
49 #include "a4xx/fd4_draw.h"
52 emit_mrt(struct fd_ringbuffer
*ring
, struct pipe_framebuffer_state
*pfb
,
53 struct fd_gmem_stateobj
*gmem
)
55 unsigned char mrt_comp
[A6XX_MAX_RENDER_TARGETS
] = {0};
56 unsigned srgb_cntl
= 0;
59 for (i
= 0; i
< pfb
->nr_cbufs
; i
++) {
60 enum a6xx_color_fmt format
= 0;
61 enum a3xx_color_swap swap
= WZYX
;
62 bool sint
= false, uint
= false;
63 struct fd_resource
*rsc
= NULL
;
64 struct fd_resource_slice
*slice
= NULL
;
74 struct pipe_surface
*psurf
= pfb
->cbufs
[i
];
75 enum pipe_format pformat
= psurf
->format
;
76 rsc
= fd_resource(psurf
->texture
);
80 uint32_t base
= gmem
? gmem
->cbuf_base
[i
] : 0;
81 slice
= fd_resource_slice(rsc
, psurf
->u
.tex
.level
);
82 format
= fd6_pipe2color(pformat
);
83 sint
= util_format_is_pure_sint(pformat
);
84 uint
= util_format_is_pure_uint(pformat
);
86 if (util_format_is_srgb(pformat
))
87 srgb_cntl
|= (1 << i
);
89 offset
= fd_resource_offset(rsc
, psurf
->u
.tex
.level
,
90 psurf
->u
.tex
.first_layer
);
92 stride
= slice
->pitch
* rsc
->cpp
* pfb
->samples
;
93 swap
= rsc
->tile_mode
? WZYX
: fd6_pipe2swap(pformat
);
96 fd_resource_level_linear(psurf
->texture
, psurf
->u
.tex
.level
))
97 tile_mode
= TILE6_LINEAR
;
99 tile_mode
= rsc
->tile_mode
;
101 if (rsc
->tile_mode
&&
102 fd_resource_level_linear(psurf
->texture
, psurf
->u
.tex
.level
))
103 tile_mode
= TILE6_LINEAR
;
105 tile_mode
= rsc
->tile_mode
;
107 debug_assert(psurf
->u
.tex
.first_layer
== psurf
->u
.tex
.last_layer
);
108 debug_assert((offset
+ slice
->size0
) <= fd_bo_size(rsc
->bo
));
110 OUT_PKT4(ring
, REG_A6XX_RB_MRT_BUF_INFO(i
), 6);
111 OUT_RING(ring
, A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format
) |
112 A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(tile_mode
) |
113 A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(swap
));
114 OUT_RING(ring
, A6XX_RB_MRT_PITCH(stride
));
115 OUT_RING(ring
, A6XX_RB_MRT_ARRAY_PITCH(slice
->size0
));
116 OUT_RELOCW(ring
, rsc
->bo
, offset
+ rsc
->offset
, 0, 0); /* BASE_LO/HI */
117 OUT_RING(ring
, base
); /* RB_MRT[i].BASE_GMEM */
118 OUT_PKT4(ring
, REG_A6XX_SP_FS_MRT_REG(i
), 1);
119 OUT_RING(ring
, A6XX_SP_FS_MRT_REG_COLOR_FORMAT(format
) |
120 COND(sint
, A6XX_SP_FS_MRT_REG_COLOR_SINT
) |
121 COND(uint
, A6XX_SP_FS_MRT_REG_COLOR_UINT
));
123 OUT_PKT4(ring
, REG_A6XX_RB_MRT_FLAG_BUFFER(i
), 3);
124 if (fd6_ubwc_enabled(rsc
, tile_mode
)) {
125 OUT_RELOCW(ring
, rsc
->bo
, offset
+ rsc
->ubwc_offset
, 0, 0); /* BASE_LO/HI */
126 OUT_RING(ring
, A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(rsc
->ubwc_pitch
) |
127 A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(rsc
->ubwc_size
));
129 OUT_RING(ring
, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_LO */
130 OUT_RING(ring
, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_HI */
131 OUT_RING(ring
, 0x00000000);
135 OUT_PKT4(ring
, REG_A6XX_RB_SRGB_CNTL
, 1);
136 OUT_RING(ring
, srgb_cntl
);
138 OUT_PKT4(ring
, REG_A6XX_SP_SRGB_CNTL
, 1);
139 OUT_RING(ring
, srgb_cntl
);
141 OUT_PKT4(ring
, REG_A6XX_RB_RENDER_COMPONENTS
, 1);
142 OUT_RING(ring
, A6XX_RB_RENDER_COMPONENTS_RT0(mrt_comp
[0]) |
143 A6XX_RB_RENDER_COMPONENTS_RT1(mrt_comp
[1]) |
144 A6XX_RB_RENDER_COMPONENTS_RT2(mrt_comp
[2]) |
145 A6XX_RB_RENDER_COMPONENTS_RT3(mrt_comp
[3]) |
146 A6XX_RB_RENDER_COMPONENTS_RT4(mrt_comp
[4]) |
147 A6XX_RB_RENDER_COMPONENTS_RT5(mrt_comp
[5]) |
148 A6XX_RB_RENDER_COMPONENTS_RT6(mrt_comp
[6]) |
149 A6XX_RB_RENDER_COMPONENTS_RT7(mrt_comp
[7]));
151 OUT_PKT4(ring
, REG_A6XX_SP_FS_RENDER_COMPONENTS
, 1);
153 A6XX_SP_FS_RENDER_COMPONENTS_RT0(mrt_comp
[0]) |
154 A6XX_SP_FS_RENDER_COMPONENTS_RT1(mrt_comp
[1]) |
155 A6XX_SP_FS_RENDER_COMPONENTS_RT2(mrt_comp
[2]) |
156 A6XX_SP_FS_RENDER_COMPONENTS_RT3(mrt_comp
[3]) |
157 A6XX_SP_FS_RENDER_COMPONENTS_RT4(mrt_comp
[4]) |
158 A6XX_SP_FS_RENDER_COMPONENTS_RT5(mrt_comp
[5]) |
159 A6XX_SP_FS_RENDER_COMPONENTS_RT6(mrt_comp
[6]) |
160 A6XX_SP_FS_RENDER_COMPONENTS_RT7(mrt_comp
[7]));
164 emit_zs(struct fd_ringbuffer
*ring
, struct pipe_surface
*zsbuf
,
165 struct fd_gmem_stateobj
*gmem
)
168 struct fd_resource
*rsc
= fd_resource(zsbuf
->texture
);
169 enum a6xx_depth_format fmt
= fd6_pipe2depth(zsbuf
->format
);
170 struct fd_resource_slice
*slice
= fd_resource_slice(rsc
, 0);
171 uint32_t stride
= slice
->pitch
* rsc
->cpp
;
172 uint32_t size
= slice
->size0
;
173 uint32_t base
= gmem
? gmem
->zsbuf_base
[0] : 0;
176 !fd_resource_level_linear(zsbuf
->texture
, zsbuf
->u
.tex
.level
) && rsc
->ubwc_size
;
178 OUT_PKT4(ring
, REG_A6XX_RB_DEPTH_BUFFER_INFO
, 6);
179 OUT_RING(ring
, A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(fmt
));
180 OUT_RING(ring
, A6XX_RB_DEPTH_BUFFER_PITCH(stride
));
181 OUT_RING(ring
, A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(size
));
182 OUT_RELOCW(ring
, rsc
->bo
, rsc
->offset
, 0, 0); /* RB_DEPTH_BUFFER_BASE_LO/HI */
183 OUT_RING(ring
, base
); /* RB_DEPTH_BUFFER_BASE_GMEM */
185 OUT_PKT4(ring
, REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO
, 1);
186 OUT_RING(ring
, A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(fmt
));
188 OUT_PKT4(ring
, REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO
, 3);
190 OUT_RELOCW(ring
, rsc
->bo
, rsc
->ubwc_offset
, 0, 0); /* BASE_LO/HI */
191 OUT_RING(ring
, A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(rsc
->ubwc_pitch
) |
192 A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(rsc
->ubwc_size
));
194 OUT_RING(ring
, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_LO */
195 OUT_RING(ring
, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_HI */
196 OUT_RING(ring
, 0x00000000);
200 OUT_PKT4(ring
, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO
, 5);
201 OUT_RELOCW(ring
, rsc
->lrz
, 0, 0, 0);
202 OUT_RING(ring
, A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH(rsc
->lrz_pitch
));
203 //OUT_RELOCW(ring, rsc->lrz, 0, 0, 0); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO/HI */
204 // XXX a6xx seems to use a different buffer here.. not sure what for..
205 OUT_RING(ring
, 0x00000000);
206 OUT_RING(ring
, 0x00000000);
208 OUT_PKT4(ring
, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO
, 5);
209 OUT_RING(ring
, 0x00000000);
210 OUT_RING(ring
, 0x00000000);
211 OUT_RING(ring
, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
212 OUT_RING(ring
, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO */
213 OUT_RING(ring
, 0x00000000);
217 struct fd_resource_slice
*slice
= fd_resource_slice(rsc
->stencil
, 0);
218 stride
= slice
->pitch
* rsc
->stencil
->cpp
;
220 uint32_t base
= gmem
? gmem
->zsbuf_base
[1] : 0;
222 OUT_PKT4(ring
, REG_A6XX_RB_STENCIL_INFO
, 6);
223 OUT_RING(ring
, A6XX_RB_STENCIL_INFO_SEPARATE_STENCIL
);
224 OUT_RING(ring
, A6XX_RB_STENCIL_BUFFER_PITCH(stride
));
225 OUT_RING(ring
, A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(size
));
226 OUT_RELOCW(ring
, rsc
->stencil
->bo
, 0, 0, 0); /* RB_STENCIL_BASE_LO/HI */
227 OUT_RING(ring
, base
); /* RB_STENCIL_BASE_LO */
229 OUT_PKT4(ring
, REG_A6XX_RB_STENCIL_INFO
, 1);
230 OUT_RING(ring
, 0x00000000); /* RB_STENCIL_INFO */
233 OUT_PKT4(ring
, REG_A6XX_RB_DEPTH_BUFFER_INFO
, 6);
234 OUT_RING(ring
, A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH6_NONE
));
235 OUT_RING(ring
, 0x00000000); /* RB_DEPTH_BUFFER_PITCH */
236 OUT_RING(ring
, 0x00000000); /* RB_DEPTH_BUFFER_ARRAY_PITCH */
237 OUT_RING(ring
, 0x00000000); /* RB_DEPTH_BUFFER_BASE_LO */
238 OUT_RING(ring
, 0x00000000); /* RB_DEPTH_BUFFER_BASE_HI */
239 OUT_RING(ring
, 0x00000000); /* RB_DEPTH_BUFFER_BASE_GMEM */
241 OUT_PKT4(ring
, REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO
, 1);
242 OUT_RING(ring
, A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH6_NONE
));
244 OUT_PKT4(ring
, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO
, 5);
245 OUT_RING(ring
, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
246 OUT_RING(ring
, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
247 OUT_RING(ring
, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
248 OUT_RING(ring
, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO */
249 OUT_RING(ring
, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI */
251 OUT_PKT4(ring
, REG_A6XX_RB_STENCIL_INFO
, 1);
252 OUT_RING(ring
, 0x00000000); /* RB_STENCIL_INFO */
257 use_hw_binning(struct fd_batch
*batch
)
259 struct fd_gmem_stateobj
*gmem
= &batch
->ctx
->gmem
;
261 // TODO figure out hw limits for binning
263 return fd_binning_enabled
&& ((gmem
->nbins_x
* gmem
->nbins_y
) > 2) &&
264 (batch
->num_draws
> 0);
268 patch_fb_read(struct fd_batch
*batch
)
270 struct fd_gmem_stateobj
*gmem
= &batch
->ctx
->gmem
;
272 for (unsigned i
= 0; i
< fd_patch_num_elements(&batch
->fb_read_patches
); i
++) {
273 struct fd_cs_patch
*patch
= fd_patch_element(&batch
->fb_read_patches
, i
);
274 *patch
->cs
= patch
->val
| A6XX_TEX_CONST_2_PITCH(gmem
->bin_w
* gmem
->cbuf_cpp
[0]);
276 util_dynarray_resize(&batch
->fb_read_patches
, 0);
280 patch_draws(struct fd_batch
*batch
, enum pc_di_vis_cull_mode vismode
)
283 for (i
= 0; i
< fd_patch_num_elements(&batch
->draw_patches
); i
++) {
284 struct fd_cs_patch
*patch
= fd_patch_element(&batch
->draw_patches
, i
);
285 *patch
->cs
= patch
->val
| DRAW4(0, 0, 0, vismode
);
287 util_dynarray_resize(&batch
->draw_patches
, 0);
291 update_render_cntl(struct fd_batch
*batch
, struct pipe_framebuffer_state
*pfb
, bool binning
)
293 struct fd_ringbuffer
*ring
= batch
->gmem
;
295 bool depth_ubwc_enable
= false;
296 uint32_t mrts_ubwc_enable
= 0;
300 struct fd_resource
*rsc
= fd_resource(pfb
->zsbuf
->texture
);
302 !fd_resource_level_linear(pfb
->zsbuf
->texture
, pfb
->zsbuf
->u
.tex
.level
) && rsc
->ubwc_size
;
305 for (i
= 0; i
< pfb
->nr_cbufs
; i
++) {
309 struct pipe_surface
*psurf
= pfb
->cbufs
[i
];
310 struct fd_resource
*rsc
= fd_resource(psurf
->texture
);
314 if (fd6_ubwc_enabled(rsc
, rsc
->tile_mode
))
315 mrts_ubwc_enable
|= 1 << i
;
318 cntl
|= A6XX_RB_RENDER_CNTL_UNK4
;
320 cntl
|= A6XX_RB_RENDER_CNTL_BINNING
;
322 OUT_PKT7(ring
, CP_REG_WRITE
, 3);
324 OUT_RING(ring
, REG_A6XX_RB_RENDER_CNTL
);
325 OUT_RING(ring
, cntl
|
326 COND(depth_ubwc_enable
, A6XX_RB_RENDER_CNTL_FLAG_DEPTH
) |
327 A6XX_RB_RENDER_CNTL_FLAG_MRTS(mrts_ubwc_enable
));
331 update_vsc_pipe(struct fd_batch
*batch
)
333 struct fd_context
*ctx
= batch
->ctx
;
334 struct fd6_context
*fd6_ctx
= fd6_context(ctx
);
335 struct fd_gmem_stateobj
*gmem
= &ctx
->gmem
;
336 struct fd_ringbuffer
*ring
= batch
->gmem
;
339 OUT_PKT4(ring
, REG_A6XX_VSC_BIN_SIZE
, 3);
340 OUT_RING(ring
, A6XX_VSC_BIN_SIZE_WIDTH(gmem
->bin_w
) |
341 A6XX_VSC_BIN_SIZE_HEIGHT(gmem
->bin_h
));
342 OUT_RELOCW(ring
, fd6_ctx
->vsc_data
,
343 32 * A6XX_VSC_DATA_PITCH
, 0, 0); /* VSC_SIZE_ADDRESS_LO/HI */
345 OUT_PKT4(ring
, REG_A6XX_VSC_BIN_COUNT
, 1);
346 OUT_RING(ring
, A6XX_VSC_BIN_COUNT_NX(gmem
->nbins_x
) |
347 A6XX_VSC_BIN_COUNT_NY(gmem
->nbins_y
));
349 OUT_PKT4(ring
, REG_A6XX_VSC_PIPE_CONFIG_REG(0), 32);
350 for (i
= 0; i
< 32; i
++) {
351 struct fd_vsc_pipe
*pipe
= &ctx
->vsc_pipe
[i
];
352 OUT_RING(ring
, A6XX_VSC_PIPE_CONFIG_REG_X(pipe
->x
) |
353 A6XX_VSC_PIPE_CONFIG_REG_Y(pipe
->y
) |
354 A6XX_VSC_PIPE_CONFIG_REG_W(pipe
->w
) |
355 A6XX_VSC_PIPE_CONFIG_REG_H(pipe
->h
));
358 OUT_PKT4(ring
, REG_A6XX_VSC_PIPE_DATA2_ADDRESS_LO
, 4);
359 OUT_RELOCW(ring
, fd6_ctx
->vsc_data2
, 0, 0, 0);
360 OUT_RING(ring
, A6XX_VSC_DATA2_PITCH
);
361 OUT_RING(ring
, fd_bo_size(fd6_ctx
->vsc_data2
));
363 OUT_PKT4(ring
, REG_A6XX_VSC_PIPE_DATA_ADDRESS_LO
, 4);
364 OUT_RELOCW(ring
, fd6_ctx
->vsc_data
, 0, 0, 0);
365 OUT_RING(ring
, A6XX_VSC_DATA_PITCH
);
366 OUT_RING(ring
, fd_bo_size(fd6_ctx
->vsc_data
));
370 set_scissor(struct fd_ringbuffer
*ring
, uint32_t x1
, uint32_t y1
, uint32_t x2
, uint32_t y2
)
372 OUT_PKT4(ring
, REG_A6XX_GRAS_SC_WINDOW_SCISSOR_TL
, 2);
373 OUT_RING(ring
, A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X(x1
) |
374 A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(y1
));
375 OUT_RING(ring
, A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X(x2
) |
376 A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(y2
));
378 OUT_PKT4(ring
, REG_A6XX_GRAS_RESOLVE_CNTL_1
, 2);
379 OUT_RING(ring
, A6XX_GRAS_RESOLVE_CNTL_1_X(x1
) |
380 A6XX_GRAS_RESOLVE_CNTL_1_Y(y1
));
381 OUT_RING(ring
, A6XX_GRAS_RESOLVE_CNTL_2_X(x2
) |
382 A6XX_GRAS_RESOLVE_CNTL_2_Y(y2
));
386 set_bin_size(struct fd_ringbuffer
*ring
, uint32_t w
, uint32_t h
, uint32_t flag
)
388 OUT_PKT4(ring
, REG_A6XX_GRAS_BIN_CONTROL
, 1);
389 OUT_RING(ring
, A6XX_GRAS_BIN_CONTROL_BINW(w
) |
390 A6XX_GRAS_BIN_CONTROL_BINH(h
) | flag
);
392 OUT_PKT4(ring
, REG_A6XX_RB_BIN_CONTROL
, 1);
393 OUT_RING(ring
, A6XX_RB_BIN_CONTROL_BINW(w
) |
394 A6XX_RB_BIN_CONTROL_BINH(h
) | flag
);
396 /* no flag for RB_BIN_CONTROL2... */
397 OUT_PKT4(ring
, REG_A6XX_RB_BIN_CONTROL2
, 1);
398 OUT_RING(ring
, A6XX_RB_BIN_CONTROL2_BINW(w
) |
399 A6XX_RB_BIN_CONTROL2_BINH(h
));
403 emit_binning_pass(struct fd_batch
*batch
)
405 struct fd_context
*ctx
= batch
->ctx
;
406 struct fd_ringbuffer
*ring
= batch
->gmem
;
407 struct fd_gmem_stateobj
*gmem
= &batch
->ctx
->gmem
;
409 uint32_t x1
= gmem
->minx
;
410 uint32_t y1
= gmem
->miny
;
411 uint32_t x2
= gmem
->minx
+ gmem
->width
- 1;
412 uint32_t y2
= gmem
->miny
+ gmem
->height
- 1;
414 set_scissor(ring
, x1
, y1
, x2
, y2
);
416 emit_marker6(ring
, 7);
417 OUT_PKT7(ring
, CP_SET_MARKER
, 1);
418 OUT_RING(ring
, A2XX_CP_SET_MARKER_0_MODE(RM6_BINNING
));
419 emit_marker6(ring
, 7);
421 OUT_PKT7(ring
, CP_SET_VISIBILITY_OVERRIDE
, 1);
424 OUT_PKT7(ring
, CP_SET_MODE
, 1);
429 OUT_PKT4(ring
, REG_A6XX_VFD_MODE_CNTL
, 1);
430 OUT_RING(ring
, A6XX_VFD_MODE_CNTL_BINNING_PASS
);
432 update_vsc_pipe(batch
);
434 OUT_PKT4(ring
, REG_A6XX_PC_UNKNOWN_9805
, 1);
437 OUT_PKT4(ring
, REG_A6XX_SP_UNKNOWN_A0F8
, 1);
440 OUT_PKT7(ring
, CP_EVENT_WRITE
, 1);
441 OUT_RING(ring
, UNK_2C
);
443 OUT_PKT4(ring
, REG_A6XX_RB_WINDOW_OFFSET
, 1);
444 OUT_RING(ring
, A6XX_RB_WINDOW_OFFSET_X(0) |
445 A6XX_RB_WINDOW_OFFSET_Y(0));
447 OUT_PKT4(ring
, REG_A6XX_SP_TP_WINDOW_OFFSET
, 1);
448 OUT_RING(ring
, A6XX_SP_TP_WINDOW_OFFSET_X(0) |
449 A6XX_SP_TP_WINDOW_OFFSET_Y(0));
451 /* emit IB to binning drawcmds: */
452 fd6_emit_ib(ring
, batch
->draw
);
456 OUT_PKT7(ring
, CP_SET_DRAW_STATE
, 3);
457 OUT_RING(ring
, CP_SET_DRAW_STATE__0_COUNT(0) |
458 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
459 CP_SET_DRAW_STATE__0_GROUP_ID(0));
460 OUT_RING(ring
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
461 OUT_RING(ring
, CP_SET_DRAW_STATE__2_ADDR_HI(0));
463 OUT_PKT7(ring
, CP_EVENT_WRITE
, 1);
464 OUT_RING(ring
, UNK_2D
);
466 OUT_PKT7(ring
, CP_EVENT_WRITE
, 4);
467 OUT_RING(ring
, CACHE_FLUSH_TS
);
468 OUT_RELOCW(ring
, fd6_context(ctx
)->blit_mem
, 0, 0, 0); /* ADDR_LO/HI */
469 OUT_RING(ring
, 0x00000000);
475 emit_msaa(struct fd_ringbuffer
*ring
, unsigned nr
)
477 enum a3xx_msaa_samples samples
= fd_msaa_samples(nr
);
479 OUT_PKT4(ring
, REG_A6XX_SP_TP_RAS_MSAA_CNTL
, 2);
480 OUT_RING(ring
, A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(samples
));
481 OUT_RING(ring
, A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(samples
) |
482 COND(samples
== MSAA_ONE
, A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE
));
484 OUT_PKT4(ring
, REG_A6XX_GRAS_RAS_MSAA_CNTL
, 2);
485 OUT_RING(ring
, A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(samples
));
486 OUT_RING(ring
, A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(samples
) |
487 COND(samples
== MSAA_ONE
, A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE
));
489 OUT_PKT4(ring
, REG_A6XX_RB_RAS_MSAA_CNTL
, 2);
490 OUT_RING(ring
, A6XX_RB_RAS_MSAA_CNTL_SAMPLES(samples
));
491 OUT_RING(ring
, A6XX_RB_DEST_MSAA_CNTL_SAMPLES(samples
) |
492 COND(samples
== MSAA_ONE
, A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE
));
494 OUT_PKT4(ring
, REG_A6XX_RB_MSAA_CNTL
, 1);
495 OUT_RING(ring
, A6XX_RB_MSAA_CNTL_SAMPLES(samples
));
498 static void prepare_tile_setup_ib(struct fd_batch
*batch
);
499 static void prepare_tile_fini_ib(struct fd_batch
*batch
);
501 /* before first tile */
503 fd6_emit_tile_init(struct fd_batch
*batch
)
505 struct fd_context
*ctx
= batch
->ctx
;
506 struct fd_ringbuffer
*ring
= batch
->gmem
;
507 struct pipe_framebuffer_state
*pfb
= &batch
->framebuffer
;
508 struct fd_gmem_stateobj
*gmem
= &batch
->ctx
->gmem
;
510 fd6_emit_restore(batch
, ring
);
512 fd6_emit_lrz_flush(ring
);
514 if (batch
->lrz_clear
)
515 fd6_emit_ib(ring
, batch
->lrz_clear
);
517 fd6_cache_inv(batch
, ring
);
519 prepare_tile_setup_ib(batch
);
520 prepare_tile_fini_ib(batch
);
522 OUT_PKT7(ring
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
525 /* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */
527 OUT_PKT4(ring
, REG_A6XX_RB_CCU_CNTL
, 1);
528 OUT_RING(ring
, 0x7c400004); /* RB_CCU_CNTL */
530 emit_zs(ring
, pfb
->zsbuf
, &ctx
->gmem
);
531 emit_mrt(ring
, pfb
, &ctx
->gmem
);
532 emit_msaa(ring
, pfb
->samples
);
533 patch_fb_read(batch
);
535 if (use_hw_binning(batch
)) {
536 set_bin_size(ring
, gmem
->bin_w
, gmem
->bin_h
,
537 A6XX_RB_BIN_CONTROL_BINNING_PASS
| 0x6000000);
538 update_render_cntl(batch
, pfb
, true);
539 emit_binning_pass(batch
);
540 patch_draws(batch
, USE_VISIBILITY
);
542 set_bin_size(ring
, gmem
->bin_w
, gmem
->bin_h
,
543 A6XX_RB_BIN_CONTROL_USE_VIZ
| 0x6000000);
545 OUT_PKT4(ring
, REG_A6XX_VFD_MODE_CNTL
, 1);
548 set_bin_size(ring
, gmem
->bin_w
, gmem
->bin_h
, 0x6000000);
549 patch_draws(batch
, IGNORE_VISIBILITY
);
552 update_render_cntl(batch
, pfb
, false);
556 set_window_offset(struct fd_ringbuffer
*ring
, uint32_t x1
, uint32_t y1
)
558 OUT_PKT4(ring
, REG_A6XX_RB_WINDOW_OFFSET
, 1);
559 OUT_RING(ring
, A6XX_RB_WINDOW_OFFSET_X(x1
) |
560 A6XX_RB_WINDOW_OFFSET_Y(y1
));
562 OUT_PKT4(ring
, REG_A6XX_RB_WINDOW_OFFSET2
, 1);
563 OUT_RING(ring
, A6XX_RB_WINDOW_OFFSET2_X(x1
) |
564 A6XX_RB_WINDOW_OFFSET2_Y(y1
));
566 OUT_PKT4(ring
, REG_A6XX_SP_WINDOW_OFFSET
, 1);
567 OUT_RING(ring
, A6XX_SP_WINDOW_OFFSET_X(x1
) |
568 A6XX_SP_WINDOW_OFFSET_Y(y1
));
570 OUT_PKT4(ring
, REG_A6XX_SP_TP_WINDOW_OFFSET
, 1);
571 OUT_RING(ring
, A6XX_SP_TP_WINDOW_OFFSET_X(x1
) |
572 A6XX_SP_TP_WINDOW_OFFSET_Y(y1
));
575 /* before mem2gmem */
577 fd6_emit_tile_prep(struct fd_batch
*batch
, struct fd_tile
*tile
)
579 struct fd_context
*ctx
= batch
->ctx
;
580 struct fd6_context
*fd6_ctx
= fd6_context(ctx
);
581 struct fd_ringbuffer
*ring
= batch
->gmem
;
583 OUT_PKT7(ring
, CP_SET_MARKER
, 1);
584 OUT_RING(ring
, A2XX_CP_SET_MARKER_0_MODE(0x7));
586 emit_marker6(ring
, 7);
587 OUT_PKT7(ring
, CP_SET_MARKER
, 1);
588 OUT_RING(ring
, A2XX_CP_SET_MARKER_0_MODE(RM6_GMEM
) | 0x10);
589 emit_marker6(ring
, 7);
591 uint32_t x1
= tile
->xoff
;
592 uint32_t y1
= tile
->yoff
;
593 uint32_t x2
= tile
->xoff
+ tile
->bin_w
- 1;
594 uint32_t y2
= tile
->yoff
+ tile
->bin_h
- 1;
596 set_scissor(ring
, x1
, y1
, x2
, y2
);
598 set_window_offset(ring
, x1
, y1
);
600 OUT_PKT4(ring
, REG_A6XX_VPC_SO_OVERRIDE
, 1);
601 OUT_RING(ring
, A6XX_VPC_SO_OVERRIDE_SO_DISABLE
);
603 if (use_hw_binning(batch
)) {
604 struct fd_vsc_pipe
*pipe
= &ctx
->vsc_pipe
[tile
->p
];
606 OUT_PKT7(ring
, CP_WAIT_FOR_ME
, 0);
608 OUT_PKT7(ring
, CP_SET_VISIBILITY_OVERRIDE
, 1);
611 OUT_PKT7(ring
, CP_SET_MODE
, 1);
614 OUT_PKT7(ring
, CP_SET_BIN_DATA5
, 7);
615 OUT_RING(ring
, CP_SET_BIN_DATA5_0_VSC_SIZE(pipe
->w
* pipe
->h
) |
616 CP_SET_BIN_DATA5_0_VSC_N(tile
->n
));
617 OUT_RELOC(ring
, fd6_ctx
->vsc_data
, /* VSC_PIPE[p].DATA_ADDRESS */
618 (tile
->p
* A6XX_VSC_DATA_PITCH
), 0, 0);
619 OUT_RELOC(ring
, fd6_ctx
->vsc_data
, /* VSC_SIZE_ADDRESS + (p * 4) */
620 (tile
->p
* 4) + (32 * A6XX_VSC_DATA_PITCH
), 0, 0);
621 OUT_RELOC(ring
, fd6_ctx
->vsc_data2
,
622 (tile
->p
* A6XX_VSC_DATA2_PITCH
), 0, 0);
624 OUT_PKT7(ring
, CP_SET_VISIBILITY_OVERRIDE
, 1);
627 OUT_PKT7(ring
, CP_SET_MODE
, 1);
633 set_blit_scissor(struct fd_batch
*batch
, struct fd_ringbuffer
*ring
)
635 struct pipe_scissor_state blit_scissor
;
636 struct pipe_framebuffer_state
*pfb
= &batch
->framebuffer
;
638 blit_scissor
.minx
= batch
->max_scissor
.minx
;
639 blit_scissor
.miny
= batch
->max_scissor
.miny
;
640 blit_scissor
.maxx
= MIN2(pfb
->width
, batch
->max_scissor
.maxx
);
641 blit_scissor
.maxy
= MIN2(pfb
->height
, batch
->max_scissor
.maxy
);
643 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_SCISSOR_TL
, 2);
645 A6XX_RB_BLIT_SCISSOR_TL_X(blit_scissor
.minx
) |
646 A6XX_RB_BLIT_SCISSOR_TL_Y(blit_scissor
.miny
));
648 A6XX_RB_BLIT_SCISSOR_BR_X(blit_scissor
.maxx
- 1) |
649 A6XX_RB_BLIT_SCISSOR_BR_Y(blit_scissor
.maxy
- 1));
653 emit_blit(struct fd_batch
*batch
,
654 struct fd_ringbuffer
*ring
,
656 struct pipe_surface
*psurf
,
659 struct fd_resource_slice
*slice
;
660 struct fd_resource
*rsc
= fd_resource(psurf
->texture
);
661 enum pipe_format pfmt
= psurf
->format
;
664 /* separate stencil case: */
667 pfmt
= rsc
->base
.format
;
670 slice
= fd_resource_slice(rsc
, psurf
->u
.tex
.level
);
671 offset
= fd_resource_offset(rsc
, psurf
->u
.tex
.level
,
672 psurf
->u
.tex
.first_layer
);
674 debug_assert(psurf
->u
.tex
.first_layer
== psurf
->u
.tex
.last_layer
);
676 enum a6xx_color_fmt format
= fd6_pipe2color(pfmt
);
677 uint32_t stride
= slice
->pitch
* rsc
->cpp
;
678 uint32_t size
= slice
->size0
;
679 enum a3xx_color_swap swap
= rsc
->tile_mode
? WZYX
: fd6_pipe2swap(pfmt
);
680 enum a3xx_msaa_samples samples
=
681 fd_msaa_samples(rsc
->base
.nr_samples
);
684 if (rsc
->tile_mode
&&
685 fd_resource_level_linear(&rsc
->base
, psurf
->u
.tex
.level
))
686 tile_mode
= TILE6_LINEAR
;
688 tile_mode
= rsc
->tile_mode
;
690 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_DST_INFO
, 5);
692 A6XX_RB_BLIT_DST_INFO_TILE_MODE(tile_mode
) |
693 A6XX_RB_BLIT_DST_INFO_SAMPLES(samples
) |
694 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(format
) |
695 A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(swap
) |
696 COND(fd6_ubwc_enabled(rsc
, tile_mode
), A6XX_RB_BLIT_DST_INFO_FLAGS
));
697 OUT_RELOCW(ring
, rsc
->bo
, offset
+ rsc
->offset
, 0, 0); /* RB_BLIT_DST_LO/HI */
698 OUT_RING(ring
, A6XX_RB_BLIT_DST_PITCH(stride
));
699 OUT_RING(ring
, A6XX_RB_BLIT_DST_ARRAY_PITCH(size
));
701 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_BASE_GMEM
, 1);
702 OUT_RING(ring
, base
);
704 if (fd6_ubwc_enabled(rsc
, tile_mode
)) {
705 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_FLAG_DST_LO
, 3);
706 OUT_RELOCW(ring
, rsc
->bo
, offset
+ rsc
->ubwc_offset
, 0, 0);
707 OUT_RING(ring
, A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(rsc
->ubwc_pitch
) |
708 A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(rsc
->ubwc_size
));
711 fd6_emit_blit(batch
, ring
);
715 emit_restore_blit(struct fd_batch
*batch
,
716 struct fd_ringbuffer
*ring
,
718 struct pipe_surface
*psurf
,
722 bool stencil
= false;
725 case FD_BUFFER_COLOR
:
726 info
|= A6XX_RB_BLIT_INFO_UNK0
;
728 case FD_BUFFER_STENCIL
:
729 info
|= A6XX_RB_BLIT_INFO_UNK0
;
732 case FD_BUFFER_DEPTH
:
733 info
|= A6XX_RB_BLIT_INFO_DEPTH
| A6XX_RB_BLIT_INFO_UNK0
;
737 if (util_format_is_pure_integer(psurf
->format
))
738 info
|= A6XX_RB_BLIT_INFO_INTEGER
;
740 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_INFO
, 1);
741 OUT_RING(ring
, info
| A6XX_RB_BLIT_INFO_GMEM
);
743 emit_blit(batch
, ring
, base
, psurf
, stencil
);
747 emit_clears(struct fd_batch
*batch
, struct fd_ringbuffer
*ring
)
749 struct pipe_framebuffer_state
*pfb
= &batch
->framebuffer
;
750 struct fd_gmem_stateobj
*gmem
= &batch
->ctx
->gmem
;
751 enum a3xx_msaa_samples samples
= fd_msaa_samples(pfb
->samples
);
753 uint32_t buffers
= batch
->fast_cleared
;
755 if (buffers
& PIPE_CLEAR_COLOR
) {
757 for (int i
= 0; i
< pfb
->nr_cbufs
; i
++) {
758 union pipe_color_union
*color
= &batch
->clear_color
[i
];
759 union util_color uc
= {0};
764 if (!(buffers
& (PIPE_CLEAR_COLOR0
<< i
)))
767 enum pipe_format pfmt
= pfb
->cbufs
[i
]->format
;
769 // XXX I think RB_CLEAR_COLOR_DWn wants to take into account SWAP??
770 union pipe_color_union swapped
;
771 switch (fd6_pipe2swap(pfmt
)) {
773 swapped
.ui
[0] = color
->ui
[0];
774 swapped
.ui
[1] = color
->ui
[1];
775 swapped
.ui
[2] = color
->ui
[2];
776 swapped
.ui
[3] = color
->ui
[3];
779 swapped
.ui
[2] = color
->ui
[0];
780 swapped
.ui
[1] = color
->ui
[1];
781 swapped
.ui
[0] = color
->ui
[2];
782 swapped
.ui
[3] = color
->ui
[3];
785 swapped
.ui
[3] = color
->ui
[0];
786 swapped
.ui
[0] = color
->ui
[1];
787 swapped
.ui
[1] = color
->ui
[2];
788 swapped
.ui
[2] = color
->ui
[3];
791 swapped
.ui
[3] = color
->ui
[0];
792 swapped
.ui
[2] = color
->ui
[1];
793 swapped
.ui
[1] = color
->ui
[2];
794 swapped
.ui
[0] = color
->ui
[3];
798 if (util_format_is_pure_uint(pfmt
)) {
799 util_format_write_4ui(pfmt
, swapped
.ui
, 0, &uc
, 0, 0, 0, 1, 1);
800 } else if (util_format_is_pure_sint(pfmt
)) {
801 util_format_write_4i(pfmt
, swapped
.i
, 0, &uc
, 0, 0, 0, 1, 1);
803 util_pack_color(swapped
.f
, pfmt
, &uc
);
806 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_DST_INFO
, 1);
807 OUT_RING(ring
, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR
) |
808 A6XX_RB_BLIT_DST_INFO_SAMPLES(samples
) |
809 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(fd6_pipe2color(pfmt
)));
811 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_INFO
, 1);
812 OUT_RING(ring
, A6XX_RB_BLIT_INFO_GMEM
|
813 A6XX_RB_BLIT_INFO_CLEAR_MASK(0xf));
815 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_BASE_GMEM
, 1);
816 OUT_RING(ring
, gmem
->cbuf_base
[i
]);
818 OUT_PKT4(ring
, REG_A6XX_RB_UNKNOWN_88D0
, 1);
821 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0
, 4);
822 OUT_RING(ring
, uc
.ui
[0]);
823 OUT_RING(ring
, uc
.ui
[1]);
824 OUT_RING(ring
, uc
.ui
[2]);
825 OUT_RING(ring
, uc
.ui
[3]);
827 fd6_emit_blit(batch
, ring
);
831 const bool has_depth
= pfb
->zsbuf
;
832 const bool has_separate_stencil
=
833 has_depth
&& fd_resource(pfb
->zsbuf
->texture
)->stencil
;
835 /* First clear depth or combined depth/stencil. */
836 if ((has_depth
&& (buffers
& PIPE_CLEAR_DEPTH
)) ||
837 (!has_separate_stencil
&& (buffers
& PIPE_CLEAR_STENCIL
))) {
838 enum pipe_format pfmt
= pfb
->zsbuf
->format
;
839 uint32_t clear_value
;
842 if (has_separate_stencil
) {
843 pfmt
= util_format_get_depth_only(pfb
->zsbuf
->format
);
844 clear_value
= util_pack_z(pfmt
, batch
->clear_depth
);
846 pfmt
= pfb
->zsbuf
->format
;
847 clear_value
= util_pack_z_stencil(pfmt
, batch
->clear_depth
,
848 batch
->clear_stencil
);
851 if (buffers
& PIPE_CLEAR_DEPTH
)
854 if (!has_separate_stencil
&& (buffers
& PIPE_CLEAR_STENCIL
))
857 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_DST_INFO
, 1);
858 OUT_RING(ring
, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR
) |
859 A6XX_RB_BLIT_DST_INFO_SAMPLES(samples
) |
860 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(fd6_pipe2color(pfmt
)));
862 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_INFO
, 1);
863 OUT_RING(ring
, A6XX_RB_BLIT_INFO_GMEM
|
864 // XXX UNK0 for separate stencil ??
865 A6XX_RB_BLIT_INFO_DEPTH
|
866 A6XX_RB_BLIT_INFO_CLEAR_MASK(mask
));
868 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_BASE_GMEM
, 1);
869 OUT_RING(ring
, gmem
->zsbuf_base
[0]);
871 OUT_PKT4(ring
, REG_A6XX_RB_UNKNOWN_88D0
, 1);
874 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0
, 1);
875 OUT_RING(ring
, clear_value
);
877 fd6_emit_blit(batch
, ring
);
880 /* Then clear the separate stencil buffer in case of 32 bit depth
881 * formats with separate stencil. */
882 if (has_separate_stencil
&& (buffers
& PIPE_CLEAR_STENCIL
)) {
883 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_DST_INFO
, 1);
884 OUT_RING(ring
, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR
) |
885 A6XX_RB_BLIT_DST_INFO_SAMPLES(samples
) |
886 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(RB6_R8_UINT
));
888 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_INFO
, 1);
889 OUT_RING(ring
, A6XX_RB_BLIT_INFO_GMEM
|
890 //A6XX_RB_BLIT_INFO_UNK0 |
891 A6XX_RB_BLIT_INFO_DEPTH
|
892 A6XX_RB_BLIT_INFO_CLEAR_MASK(0x1));
894 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_BASE_GMEM
, 1);
895 OUT_RING(ring
, gmem
->zsbuf_base
[1]);
897 OUT_PKT4(ring
, REG_A6XX_RB_UNKNOWN_88D0
, 1);
900 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0
, 1);
901 OUT_RING(ring
, batch
->clear_stencil
& 0xff);
903 fd6_emit_blit(batch
, ring
);
908 * transfer from system memory to gmem
911 emit_restore_blits(struct fd_batch
*batch
, struct fd_ringbuffer
*ring
)
913 struct fd_context
*ctx
= batch
->ctx
;
914 struct fd_gmem_stateobj
*gmem
= &ctx
->gmem
;
915 struct pipe_framebuffer_state
*pfb
= &batch
->framebuffer
;
917 if (batch
->restore
& FD_BUFFER_COLOR
) {
919 for (i
= 0; i
< pfb
->nr_cbufs
; i
++) {
922 if (!(batch
->restore
& (PIPE_CLEAR_COLOR0
<< i
)))
924 emit_restore_blit(batch
, ring
, gmem
->cbuf_base
[i
], pfb
->cbufs
[i
],
929 if (batch
->restore
& (FD_BUFFER_DEPTH
| FD_BUFFER_STENCIL
)) {
930 struct fd_resource
*rsc
= fd_resource(pfb
->zsbuf
->texture
);
932 if (!rsc
->stencil
|| (batch
->restore
& FD_BUFFER_DEPTH
)) {
933 emit_restore_blit(batch
, ring
, gmem
->zsbuf_base
[0], pfb
->zsbuf
,
936 if (rsc
->stencil
&& (batch
->restore
& FD_BUFFER_STENCIL
)) {
937 emit_restore_blit(batch
, ring
, gmem
->zsbuf_base
[1], pfb
->zsbuf
,
944 prepare_tile_setup_ib(struct fd_batch
*batch
)
946 batch
->tile_setup
= fd_submit_new_ringbuffer(batch
->submit
, 0x1000,
947 FD_RINGBUFFER_STREAMING
);
949 set_blit_scissor(batch
, batch
->tile_setup
);
951 emit_restore_blits(batch
, batch
->tile_setup
);
952 emit_clears(batch
, batch
->tile_setup
);
956 * transfer from system memory to gmem
959 fd6_emit_tile_mem2gmem(struct fd_batch
*batch
, struct fd_tile
*tile
)
963 /* before IB to rendering cmds: */
965 fd6_emit_tile_renderprep(struct fd_batch
*batch
, struct fd_tile
*tile
)
967 fd6_emit_ib(batch
->gmem
, batch
->tile_setup
);
971 emit_resolve_blit(struct fd_batch
*batch
,
972 struct fd_ringbuffer
*ring
,
974 struct pipe_surface
*psurf
,
978 bool stencil
= false;
980 if (!fd_resource(psurf
->texture
)->valid
)
984 case FD_BUFFER_COLOR
:
986 case FD_BUFFER_STENCIL
:
987 info
|= A6XX_RB_BLIT_INFO_UNK0
;
990 case FD_BUFFER_DEPTH
:
991 info
|= A6XX_RB_BLIT_INFO_DEPTH
;
995 if (util_format_is_pure_integer(psurf
->format
))
996 info
|= A6XX_RB_BLIT_INFO_INTEGER
;
998 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_INFO
, 1);
999 OUT_RING(ring
, info
);
1001 emit_blit(batch
, ring
, base
, psurf
, stencil
);
1005 * transfer from gmem to system memory (ie. normal RAM)
1009 prepare_tile_fini_ib(struct fd_batch
*batch
)
1011 struct fd_context
*ctx
= batch
->ctx
;
1012 struct fd_gmem_stateobj
*gmem
= &ctx
->gmem
;
1013 struct pipe_framebuffer_state
*pfb
= &batch
->framebuffer
;
1014 struct fd_ringbuffer
*ring
;
1016 batch
->tile_fini
= fd_submit_new_ringbuffer(batch
->submit
, 0x1000,
1017 FD_RINGBUFFER_STREAMING
);
1018 ring
= batch
->tile_fini
;
1020 if (use_hw_binning(batch
)) {
1021 OUT_PKT7(ring
, CP_SET_MARKER
, 1);
1022 OUT_RING(ring
, A2XX_CP_SET_MARKER_0_MODE(0x5) | 0x10);
1025 OUT_PKT7(ring
, CP_SET_DRAW_STATE
, 3);
1026 OUT_RING(ring
, CP_SET_DRAW_STATE__0_COUNT(0) |
1027 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
1028 CP_SET_DRAW_STATE__0_GROUP_ID(0));
1029 OUT_RING(ring
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1030 OUT_RING(ring
, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1032 OUT_PKT7(ring
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1033 OUT_RING(ring
, 0x0);
1035 emit_marker6(ring
, 7);
1036 OUT_PKT7(ring
, CP_SET_MARKER
, 1);
1037 OUT_RING(ring
, A2XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE
) | 0x10);
1038 emit_marker6(ring
, 7);
1040 set_blit_scissor(batch
, ring
);
1042 if (batch
->resolve
& (FD_BUFFER_DEPTH
| FD_BUFFER_STENCIL
)) {
1043 struct fd_resource
*rsc
= fd_resource(pfb
->zsbuf
->texture
);
1045 if (!rsc
->stencil
|| (batch
->resolve
& FD_BUFFER_DEPTH
)) {
1046 emit_resolve_blit(batch
, ring
,
1047 gmem
->zsbuf_base
[0], pfb
->zsbuf
,
1050 if (rsc
->stencil
&& (batch
->resolve
& FD_BUFFER_STENCIL
)) {
1051 emit_resolve_blit(batch
, ring
,
1052 gmem
->zsbuf_base
[1], pfb
->zsbuf
,
1057 if (batch
->resolve
& FD_BUFFER_COLOR
) {
1059 for (i
= 0; i
< pfb
->nr_cbufs
; i
++) {
1062 if (!(batch
->resolve
& (PIPE_CLEAR_COLOR0
<< i
)))
1064 emit_resolve_blit(batch
, ring
, gmem
->cbuf_base
[i
], pfb
->cbufs
[i
],
1071 fd6_emit_tile_gmem2mem(struct fd_batch
*batch
, struct fd_tile
*tile
)
1073 fd6_emit_ib(batch
->gmem
, batch
->tile_fini
);
1077 fd6_emit_tile_fini(struct fd_batch
*batch
)
1079 struct fd_ringbuffer
*ring
= batch
->gmem
;
1081 OUT_PKT4(ring
, REG_A6XX_GRAS_LRZ_CNTL
, 1);
1082 OUT_RING(ring
, A6XX_GRAS_LRZ_CNTL_ENABLE
| A6XX_GRAS_LRZ_CNTL_UNK3
);
1084 fd6_emit_lrz_flush(ring
);
1086 fd6_event_write(batch
, ring
, CACHE_FLUSH_TS
, true);
1090 fd6_emit_sysmem_prep(struct fd_batch
*batch
)
1092 struct pipe_framebuffer_state
*pfb
= &batch
->framebuffer
;
1093 struct fd_ringbuffer
*ring
= batch
->gmem
;
1095 fd6_emit_restore(batch
, ring
);
1097 fd6_emit_lrz_flush(ring
);
1099 emit_marker6(ring
, 7);
1100 OUT_PKT7(ring
, CP_SET_MARKER
, 1);
1101 OUT_RING(ring
, A2XX_CP_SET_MARKER_0_MODE(RM6_BYPASS
) | 0x10); /* | 0x10 ? */
1102 emit_marker6(ring
, 7);
1104 OUT_PKT7(ring
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1105 OUT_RING(ring
, 0x0);
1107 fd6_event_write(batch
, ring
, PC_CCU_INVALIDATE_COLOR
, false);
1108 fd6_cache_inv(batch
, ring
);
1111 OUT_PKT4(ring
, REG_A6XX_PC_POWER_CNTL
, 1);
1112 OUT_RING(ring
, 0x00000003); /* PC_POWER_CNTL */
1116 OUT_PKT4(ring
, REG_A6XX_VFD_POWER_CNTL
, 1);
1117 OUT_RING(ring
, 0x00000003); /* VFD_POWER_CNTL */
1120 /* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */
1121 fd_wfi(batch
, ring
);
1122 OUT_PKT4(ring
, REG_A6XX_RB_CCU_CNTL
, 1);
1123 OUT_RING(ring
, 0x10000000); /* RB_CCU_CNTL */
1125 set_scissor(ring
, 0, 0, pfb
->width
- 1, pfb
->height
- 1);
1127 set_window_offset(ring
, 0, 0);
1129 set_bin_size(ring
, 0, 0, 0xc00000); /* 0xc00000 = BYPASS? */
1131 OUT_PKT7(ring
, CP_SET_VISIBILITY_OVERRIDE
, 1);
1132 OUT_RING(ring
, 0x1);
1134 patch_draws(batch
, IGNORE_VISIBILITY
);
1136 emit_zs(ring
, pfb
->zsbuf
, NULL
);
1137 emit_mrt(ring
, pfb
, NULL
);
1138 emit_msaa(ring
, pfb
->samples
);
1140 update_render_cntl(batch
, pfb
, false);
1144 fd6_emit_sysmem_fini(struct fd_batch
*batch
)
1146 struct fd_ringbuffer
*ring
= batch
->gmem
;
1148 OUT_PKT7(ring
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1149 OUT_RING(ring
, 0x0);
1151 fd6_emit_lrz_flush(ring
);
1153 fd6_event_write(batch
, ring
, UNK_1D
, true);
1157 fd6_gmem_init(struct pipe_context
*pctx
)
1159 struct fd_context
*ctx
= fd_context(pctx
);
1161 ctx
->emit_tile_init
= fd6_emit_tile_init
;
1162 ctx
->emit_tile_prep
= fd6_emit_tile_prep
;
1163 ctx
->emit_tile_mem2gmem
= fd6_emit_tile_mem2gmem
;
1164 ctx
->emit_tile_renderprep
= fd6_emit_tile_renderprep
;
1165 ctx
->emit_tile_gmem2mem
= fd6_emit_tile_gmem2mem
;
1166 ctx
->emit_tile_fini
= fd6_emit_tile_fini
;
1167 ctx
->emit_sysmem_prep
= fd6_emit_sysmem_prep
;
1168 ctx
->emit_sysmem_fini
= fd6_emit_sysmem_fini
;