projects / mesa.git / blob
? search:


fa1090d0eaf81e8ab728824f578f473d95cc0502
[mesa.git] / src / gallium / drivers / freedreno / a6xx / fd6_gmem.c
1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 * Authors:
25 * Rob Clark <robclark@freedesktop.org>
26 */
27
28 #include <stdio.h>
29
30 #include "pipe/p_state.h"
31 #include "util/u_string.h"
32 #include "util/u_memory.h"
33 #include "util/u_inlines.h"
34 #include "util/u_format.h"
35
36 #include "freedreno_draw.h"
37 #include "freedreno_state.h"
38 #include "freedreno_resource.h"
39
40 #include "fd6_gmem.h"
41 #include "fd6_context.h"
42 #include "fd6_draw.h"
43 #include "fd6_emit.h"
44 #include "fd6_program.h"
45 #include "fd6_format.h"
46 #include "fd6_zsa.h"
47
48 /* some bits in common w/ a4xx: */
49 #include "a4xx/fd4_draw.h"
50
51 static void
52 emit_mrt(struct fd_ringbuffer *ring, struct pipe_framebuffer_state *pfb,
53 struct fd_gmem_stateobj *gmem)
54 {
55 unsigned char mrt_comp[A6XX_MAX_RENDER_TARGETS] = {0};
56 unsigned srgb_cntl = 0;
57 unsigned i;
58
59 for (i = 0; i < pfb->nr_cbufs; i++) {
60 enum a6xx_color_fmt format = 0;
61 enum a3xx_color_swap swap = WZYX;
62 bool sint = false, uint = false;
63 struct fd_resource *rsc = NULL;
64 struct fd_resource_slice *slice = NULL;
65 uint32_t stride = 0;
66 uint32_t offset = 0;
67 uint32_t tile_mode;
68
69 if (!pfb->cbufs[i])
70 continue;
71
72 mrt_comp[i] = 0xf;
73
74 struct pipe_surface *psurf = pfb->cbufs[i];
75 enum pipe_format pformat = psurf->format;
76 rsc = fd_resource(psurf->texture);
77 if (!rsc->bo)
78 continue;
79
80 uint32_t base = gmem ? gmem->cbuf_base[i] : 0;
81 slice = fd_resource_slice(rsc, psurf->u.tex.level);
82 format = fd6_pipe2color(pformat);
83 sint = util_format_is_pure_sint(pformat);
84 uint = util_format_is_pure_uint(pformat);
85
86 if (util_format_is_srgb(pformat))
87 srgb_cntl |= (1 << i);
88
89 offset = fd_resource_offset(rsc, psurf->u.tex.level,
90 psurf->u.tex.first_layer);
91
92 stride = slice->pitch * rsc->cpp * pfb->samples;
93 swap = rsc->tile_mode ? WZYX : fd6_pipe2swap(pformat);
94
95 if (rsc->tile_mode &&
96 fd_resource_level_linear(psurf->texture, psurf->u.tex.level))
97 tile_mode = TILE6_LINEAR;
98 else
99 tile_mode = rsc->tile_mode;
100
101 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
102 debug_assert((offset + slice->size0) <= fd_bo_size(rsc->bo));
103
104 OUT_PKT4(ring, REG_A6XX_RB_MRT_BUF_INFO(i), 6);
105 OUT_RING(ring, A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format) |
106 A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(tile_mode) |
107 A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(swap));
108 OUT_RING(ring, A6XX_RB_MRT_PITCH(stride));
109 OUT_RING(ring, A6XX_RB_MRT_ARRAY_PITCH(slice->size0));
110 OUT_RELOCW(ring, rsc->bo, offset, 0, 0); /* BASE_LO/HI */
111 OUT_RING(ring, base); /* RB_MRT[i].BASE_GMEM */
112 OUT_PKT4(ring, REG_A6XX_SP_FS_MRT_REG(i), 1);
113 OUT_RING(ring, A6XX_SP_FS_MRT_REG_COLOR_FORMAT(format) |
114 COND(sint, A6XX_SP_FS_MRT_REG_COLOR_SINT) |
115 COND(uint, A6XX_SP_FS_MRT_REG_COLOR_UINT));
116
117 #if 0
118 /* when we support UBWC, these would be the system memory
119 * addr/pitch/etc:
120 */
121 OUT_PKT4(ring, REG_A6XX_RB_MRT_FLAG_BUFFER(i), 4);
122 OUT_RING(ring, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_LO */
123 OUT_RING(ring, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_HI */
124 OUT_RING(ring, A6XX_RB_MRT_FLAG_BUFFER_PITCH(0));
125 OUT_RING(ring, A6XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(0));
126 #endif
127 }
128
129 OUT_PKT4(ring, REG_A6XX_RB_SRGB_CNTL, 1);
130 OUT_RING(ring, srgb_cntl);
131
132 OUT_PKT4(ring, REG_A6XX_SP_SRGB_CNTL, 1);
133 OUT_RING(ring, srgb_cntl);
134
135 OUT_PKT4(ring, REG_A6XX_RB_RENDER_COMPONENTS, 1);
136 OUT_RING(ring, A6XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
137 A6XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
138 A6XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
139 A6XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
140 A6XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
141 A6XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
142 A6XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
143 A6XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
144
145 OUT_PKT4(ring, REG_A6XX_SP_FS_RENDER_COMPONENTS, 1);
146 OUT_RING(ring,
147 A6XX_SP_FS_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
148 A6XX_SP_FS_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
149 A6XX_SP_FS_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
150 A6XX_SP_FS_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
151 A6XX_SP_FS_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
152 A6XX_SP_FS_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
153 A6XX_SP_FS_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
154 A6XX_SP_FS_RENDER_COMPONENTS_RT7(mrt_comp[7]));
155 }
156
157 static void
158 emit_zs(struct fd_ringbuffer *ring, struct pipe_surface *zsbuf,
159 struct fd_gmem_stateobj *gmem)
160 {
161 if (zsbuf) {
162 struct fd_resource *rsc = fd_resource(zsbuf->texture);
163 enum a6xx_depth_format fmt = fd6_pipe2depth(zsbuf->format);
164 struct fd_resource_slice *slice = fd_resource_slice(rsc, 0);
165 uint32_t stride = slice->pitch * rsc->cpp;
166 uint32_t size = slice->size0;
167 uint32_t base = gmem ? gmem->zsbuf_base[0] : 0;
168
169 OUT_PKT4(ring, REG_A6XX_RB_DEPTH_BUFFER_INFO, 6);
170 OUT_RING(ring, A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(fmt));
171 OUT_RING(ring, A6XX_RB_DEPTH_BUFFER_PITCH(stride));
172 OUT_RING(ring, A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(size));
173 OUT_RELOCW(ring, rsc->bo, 0, 0, 0); /* RB_DEPTH_BUFFER_BASE_LO/HI */
174 OUT_RING(ring, base); /* RB_DEPTH_BUFFER_BASE_GMEM */
175
176 OUT_PKT4(ring, REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO, 1);
177 OUT_RING(ring, A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(fmt));
178
179 OUT_PKT4(ring, REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO, 3);
180 OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
181 OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
182 OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_PITCH */
183
184 if (rsc->lrz) {
185 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO, 5);
186 OUT_RELOCW(ring, rsc->lrz, 0, 0, 0);
187 OUT_RING(ring, A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH(rsc->lrz_pitch));
188 //OUT_RELOCW(ring, rsc->lrz, 0, 0, 0); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO/HI */
189 // XXX a6xx seems to use a different buffer here.. not sure what for..
190 OUT_RING(ring, 0x00000000);
191 OUT_RING(ring, 0x00000000);
192 } else {
193 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO, 5);
194 OUT_RING(ring, 0x00000000);
195 OUT_RING(ring, 0x00000000);
196 OUT_RING(ring, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
197 OUT_RING(ring, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO */
198 OUT_RING(ring, 0x00000000);
199 }
200
201 if (rsc->stencil) {
202 struct fd_resource_slice *slice = fd_resource_slice(rsc->stencil, 0);
203 stride = slice->pitch * rsc->stencil->cpp;
204 size = slice->size0;
205 uint32_t base = gmem ? gmem->zsbuf_base[1] : 0;
206
207 OUT_PKT4(ring, REG_A6XX_RB_STENCIL_INFO, 6);
208 OUT_RING(ring, A6XX_RB_STENCIL_INFO_SEPARATE_STENCIL);
209 OUT_RING(ring, A6XX_RB_STENCIL_BUFFER_PITCH(stride));
210 OUT_RING(ring, A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(size));
211 OUT_RELOCW(ring, rsc->stencil->bo, 0, 0, 0); /* RB_STENCIL_BASE_LO/HI */
212 OUT_RING(ring, base); /* RB_STENCIL_BASE_LO */
213 } else {
214 OUT_PKT4(ring, REG_A6XX_RB_STENCIL_INFO, 1);
215 OUT_RING(ring, 0x00000000); /* RB_STENCIL_INFO */
216 }
217 } else {
218 OUT_PKT4(ring, REG_A6XX_RB_DEPTH_BUFFER_INFO, 6);
219 OUT_RING(ring, A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH6_NONE));
220 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_PITCH */
221 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_ARRAY_PITCH */
222 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_BASE_LO */
223 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_BASE_HI */
224 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_BASE_GMEM */
225
226 OUT_PKT4(ring, REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO, 1);
227 OUT_RING(ring, A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH6_NONE));
228
229 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO, 5);
230 OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
231 OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
232 OUT_RING(ring, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
233 OUT_RING(ring, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO */
234 OUT_RING(ring, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI */
235
236 OUT_PKT4(ring, REG_A6XX_RB_STENCIL_INFO, 1);
237 OUT_RING(ring, 0x00000000); /* RB_STENCIL_INFO */
238 }
239 }
240
241 static bool
242 use_hw_binning(struct fd_batch *batch)
243 {
244 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
245
246 // TODO figure out hw limits for binning
247
248 return fd_binning_enabled && ((gmem->nbins_x * gmem->nbins_y) > 2) &&
249 (batch->num_draws > 0);
250 }
251
252 static void
253 patch_draws(struct fd_batch *batch, enum pc_di_vis_cull_mode vismode)
254 {
255 unsigned i;
256 for (i = 0; i < fd_patch_num_elements(&batch->draw_patches); i++) {
257 struct fd_cs_patch *patch = fd_patch_element(&batch->draw_patches, i);
258 *patch->cs = patch->val | DRAW4(0, 0, 0, vismode);
259 }
260 util_dynarray_resize(&batch->draw_patches, 0);
261 }
262
263 static void
264 update_render_cntl(struct fd_batch *batch, bool binning)
265 {
266 struct fd_ringbuffer *ring = batch->gmem;
267 uint32_t cntl = 0;
268
269 cntl |= A6XX_RB_RENDER_CNTL_UNK4;
270 if (binning)
271 cntl |= A6XX_RB_RENDER_CNTL_BINNING;
272
273 OUT_PKT7(ring, CP_REG_WRITE, 3);
274 OUT_RING(ring, 0x2);
275 OUT_RING(ring, REG_A6XX_RB_RENDER_CNTL);
276 OUT_RING(ring, cntl);
277 }
278
279 static void
280 update_vsc_pipe(struct fd_batch *batch)
281 {
282 struct fd_context *ctx = batch->ctx;
283 struct fd6_context *fd6_ctx = fd6_context(ctx);
284 struct fd_gmem_stateobj *gmem = &ctx->gmem;
285 struct fd_ringbuffer *ring = batch->gmem;
286 int i;
287
288 OUT_PKT4(ring, REG_A6XX_VSC_BIN_SIZE, 3);
289 OUT_RING(ring, A6XX_VSC_BIN_SIZE_WIDTH(gmem->bin_w) |
290 A6XX_VSC_BIN_SIZE_HEIGHT(gmem->bin_h));
291 OUT_RELOCW(ring, fd6_ctx->vsc_data,
292 32 * A6XX_VSC_DATA_PITCH, 0, 0); /* VSC_SIZE_ADDRESS_LO/HI */
293
294 OUT_PKT4(ring, REG_A6XX_VSC_BIN_COUNT, 1);
295 OUT_RING(ring, A6XX_VSC_BIN_COUNT_NX(gmem->nbins_x) |
296 A6XX_VSC_BIN_COUNT_NY(gmem->nbins_y));
297
298 OUT_PKT4(ring, REG_A6XX_VSC_PIPE_CONFIG_REG(0), 32);
299 for (i = 0; i < 32; i++) {
300 struct fd_vsc_pipe *pipe = &ctx->vsc_pipe[i];
301 OUT_RING(ring, A6XX_VSC_PIPE_CONFIG_REG_X(pipe->x) |
302 A6XX_VSC_PIPE_CONFIG_REG_Y(pipe->y) |
303 A6XX_VSC_PIPE_CONFIG_REG_W(pipe->w) |
304 A6XX_VSC_PIPE_CONFIG_REG_H(pipe->h));
305 }
306
307 OUT_PKT4(ring, REG_A6XX_VSC_PIPE_DATA2_ADDRESS_LO, 4);
308 OUT_RELOCW(ring, fd6_ctx->vsc_data2, 0, 0, 0);
309 OUT_RING(ring, A6XX_VSC_DATA2_PITCH);
310 OUT_RING(ring, fd_bo_size(fd6_ctx->vsc_data2));
311
312 OUT_PKT4(ring, REG_A6XX_VSC_PIPE_DATA_ADDRESS_LO, 4);
313 OUT_RELOCW(ring, fd6_ctx->vsc_data, 0, 0, 0);
314 OUT_RING(ring, A6XX_VSC_DATA_PITCH);
315 OUT_RING(ring, fd_bo_size(fd6_ctx->vsc_data));
316 }
317
318 static void
319 set_scissor(struct fd_ringbuffer *ring, uint32_t x1, uint32_t y1, uint32_t x2, uint32_t y2)
320 {
321 OUT_PKT4(ring, REG_A6XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
322 OUT_RING(ring, A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X(x1) |
323 A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(y1));
324 OUT_RING(ring, A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X(x2) |
325 A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(y2));
326
327 OUT_PKT4(ring, REG_A6XX_GRAS_RESOLVE_CNTL_1, 2);
328 OUT_RING(ring, A6XX_GRAS_RESOLVE_CNTL_1_X(x1) |
329 A6XX_GRAS_RESOLVE_CNTL_1_Y(y1));
330 OUT_RING(ring, A6XX_GRAS_RESOLVE_CNTL_2_X(x2) |
331 A6XX_GRAS_RESOLVE_CNTL_2_Y(y2));
332 }
333
334 static void
335 set_bin_size(struct fd_ringbuffer *ring, uint32_t w, uint32_t h, uint32_t flag)
336 {
337 OUT_PKT4(ring, REG_A6XX_GRAS_BIN_CONTROL, 1);
338 OUT_RING(ring, A6XX_GRAS_BIN_CONTROL_BINW(w) |
339 A6XX_GRAS_BIN_CONTROL_BINH(h) | flag);
340
341 OUT_PKT4(ring, REG_A6XX_RB_BIN_CONTROL, 1);
342 OUT_RING(ring, A6XX_RB_BIN_CONTROL_BINW(w) |
343 A6XX_RB_BIN_CONTROL_BINH(h) | flag);
344
345 /* no flag for RB_BIN_CONTROL2... */
346 OUT_PKT4(ring, REG_A6XX_RB_BIN_CONTROL2, 1);
347 OUT_RING(ring, A6XX_RB_BIN_CONTROL2_BINW(w) |
348 A6XX_RB_BIN_CONTROL2_BINH(h));
349 }
350
351 static void
352 emit_binning_pass(struct fd_batch *batch)
353 {
354 struct fd_context *ctx = batch->ctx;
355 struct fd_ringbuffer *ring = batch->gmem;
356 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
357
358 uint32_t x1 = gmem->minx;
359 uint32_t y1 = gmem->miny;
360 uint32_t x2 = gmem->minx + gmem->width - 1;
361 uint32_t y2 = gmem->miny + gmem->height - 1;
362
363 set_scissor(ring, x1, y1, x2, y2);
364
365 emit_marker6(ring, 7);
366 OUT_PKT7(ring, CP_SET_MARKER, 1);
367 OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(RM6_BINNING));
368 emit_marker6(ring, 7);
369
370 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
371 OUT_RING(ring, 0x1);
372
373 OUT_PKT7(ring, CP_SET_MODE, 1);
374 OUT_RING(ring, 0x1);
375
376 OUT_WFI5(ring);
377
378 OUT_PKT4(ring, REG_A6XX_VFD_MODE_CNTL, 1);
379 OUT_RING(ring, A6XX_VFD_MODE_CNTL_BINNING_PASS);
380
381 update_vsc_pipe(batch);
382
383 OUT_PKT4(ring, REG_A6XX_PC_UNKNOWN_9805, 1);
384 OUT_RING(ring, 0x1);
385
386 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A0F8, 1);
387 OUT_RING(ring, 0x1);
388
389 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
390 OUT_RING(ring, UNK_2C);
391
392 OUT_PKT4(ring, REG_A6XX_RB_WINDOW_OFFSET, 1);
393 OUT_RING(ring, A6XX_RB_WINDOW_OFFSET_X(0) |
394 A6XX_RB_WINDOW_OFFSET_Y(0));
395
396 OUT_PKT4(ring, REG_A6XX_SP_TP_WINDOW_OFFSET, 1);
397 OUT_RING(ring, A6XX_SP_TP_WINDOW_OFFSET_X(0) |
398 A6XX_SP_TP_WINDOW_OFFSET_Y(0));
399
400 /* emit IB to binning drawcmds: */
401 fd6_emit_ib(ring, batch->draw);
402
403 fd_reset_wfi(batch);
404
405 OUT_PKT7(ring, CP_SET_DRAW_STATE, 3);
406 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
407 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
408 CP_SET_DRAW_STATE__0_GROUP_ID(0));
409 OUT_RING(ring, CP_SET_DRAW_STATE__1_ADDR_LO(0));
410 OUT_RING(ring, CP_SET_DRAW_STATE__2_ADDR_HI(0));
411
412 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
413 OUT_RING(ring, UNK_2D);
414
415 OUT_PKT7(ring, CP_EVENT_WRITE, 4);
416 OUT_RING(ring, CACHE_FLUSH_TS);
417 OUT_RELOCW(ring, fd6_context(ctx)->blit_mem, 0, 0, 0); /* ADDR_LO/HI */
418 OUT_RING(ring, 0x00000000);
419
420 fd_wfi(batch, ring);
421 }
422
423 static void
424 emit_msaa(struct fd_ringbuffer *ring, unsigned nr)
425 {
426 enum a3xx_msaa_samples samples = fd_msaa_samples(nr);
427
428 OUT_PKT4(ring, REG_A6XX_SP_TP_RAS_MSAA_CNTL, 2);
429 OUT_RING(ring, A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(samples));
430 OUT_RING(ring, A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(samples) |
431 COND(samples == MSAA_ONE, A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE));
432
433 OUT_PKT4(ring, REG_A6XX_GRAS_RAS_MSAA_CNTL, 2);
434 OUT_RING(ring, A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(samples));
435 OUT_RING(ring, A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(samples) |
436 COND(samples == MSAA_ONE, A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE));
437
438 OUT_PKT4(ring, REG_A6XX_RB_RAS_MSAA_CNTL, 2);
439 OUT_RING(ring, A6XX_RB_RAS_MSAA_CNTL_SAMPLES(samples));
440 OUT_RING(ring, A6XX_RB_DEST_MSAA_CNTL_SAMPLES(samples) |
441 COND(samples == MSAA_ONE, A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE));
442
443 OUT_PKT4(ring, REG_A6XX_RB_MSAA_CNTL, 1);
444 OUT_RING(ring, A6XX_RB_MSAA_CNTL_SAMPLES(samples));
445 }
446
447 static void prepare_tile_setup_ib(struct fd_batch *batch);
448 static void prepare_tile_fini_ib(struct fd_batch *batch);
449
450 /* before first tile */
451 static void
452 fd6_emit_tile_init(struct fd_batch *batch)
453 {
454 struct fd_context *ctx = batch->ctx;
455 struct fd_ringbuffer *ring = batch->gmem;
456 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
457 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
458
459 fd6_emit_restore(batch, ring);
460
461 fd6_emit_lrz_flush(ring);
462
463 if (batch->lrz_clear)
464 fd6_emit_ib(ring, batch->lrz_clear);
465
466 fd6_cache_inv(batch, ring);
467
468 prepare_tile_setup_ib(batch);
469 prepare_tile_fini_ib(batch);
470
471 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
472 OUT_RING(ring, 0x0);
473
474 /* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */
475 fd_wfi(batch, ring);
476 OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
477 OUT_RING(ring, 0x7c400004); /* RB_CCU_CNTL */
478
479 emit_zs(ring, pfb->zsbuf, &ctx->gmem);
480 emit_mrt(ring, pfb, &ctx->gmem);
481 emit_msaa(ring, pfb->samples);
482
483 if (use_hw_binning(batch)) {
484 set_bin_size(ring, gmem->bin_w, gmem->bin_h,
485 A6XX_RB_BIN_CONTROL_BINNING_PASS | 0x6000000);
486 update_render_cntl(batch, true);
487 emit_binning_pass(batch);
488 patch_draws(batch, USE_VISIBILITY);
489
490 set_bin_size(ring, gmem->bin_w, gmem->bin_h,
491 A6XX_RB_BIN_CONTROL_USE_VIZ | 0x6000000);
492
493 OUT_PKT4(ring, REG_A6XX_VFD_MODE_CNTL, 1);
494 OUT_RING(ring, 0x0);
495 } else {
496 set_bin_size(ring, gmem->bin_w, gmem->bin_h, 0x6000000);
497 patch_draws(batch, IGNORE_VISIBILITY);
498 }
499
500 update_render_cntl(batch, false);
501 }
502
503 static void
504 set_window_offset(struct fd_ringbuffer *ring, uint32_t x1, uint32_t y1)
505 {
506 OUT_PKT4(ring, REG_A6XX_RB_WINDOW_OFFSET, 1);
507 OUT_RING(ring, A6XX_RB_WINDOW_OFFSET_X(x1) |
508 A6XX_RB_WINDOW_OFFSET_Y(y1));
509
510 OUT_PKT4(ring, REG_A6XX_RB_WINDOW_OFFSET2, 1);
511 OUT_RING(ring, A6XX_RB_WINDOW_OFFSET2_X(x1) |
512 A6XX_RB_WINDOW_OFFSET2_Y(y1));
513
514 OUT_PKT4(ring, REG_A6XX_SP_WINDOW_OFFSET, 1);
515 OUT_RING(ring, A6XX_SP_WINDOW_OFFSET_X(x1) |
516 A6XX_SP_WINDOW_OFFSET_Y(y1));
517
518 OUT_PKT4(ring, REG_A6XX_SP_TP_WINDOW_OFFSET, 1);
519 OUT_RING(ring, A6XX_SP_TP_WINDOW_OFFSET_X(x1) |
520 A6XX_SP_TP_WINDOW_OFFSET_Y(y1));
521 }
522
523 /* before mem2gmem */
524 static void
525 fd6_emit_tile_prep(struct fd_batch *batch, struct fd_tile *tile)
526 {
527 struct fd_context *ctx = batch->ctx;
528 struct fd6_context *fd6_ctx = fd6_context(ctx);
529 struct fd_ringbuffer *ring = batch->gmem;
530
531 OUT_PKT7(ring, CP_SET_MARKER, 1);
532 OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(0x7));
533
534 emit_marker6(ring, 7);
535 OUT_PKT7(ring, CP_SET_MARKER, 1);
536 OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(RM6_GMEM) | 0x10);
537 emit_marker6(ring, 7);
538
539 uint32_t x1 = tile->xoff;
540 uint32_t y1 = tile->yoff;
541 uint32_t x2 = tile->xoff + tile->bin_w - 1;
542 uint32_t y2 = tile->yoff + tile->bin_h - 1;
543
544 set_scissor(ring, x1, y1, x2, y2);
545
546 set_window_offset(ring, x1, y1);
547
548 OUT_PKT4(ring, REG_A6XX_VPC_SO_OVERRIDE, 1);
549 OUT_RING(ring, A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
550
551 if (use_hw_binning(batch)) {
552 struct fd_vsc_pipe *pipe = &ctx->vsc_pipe[tile->p];
553
554 OUT_PKT7(ring, CP_WAIT_FOR_ME, 0);
555
556 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
557 OUT_RING(ring, 0x0);
558
559 OUT_PKT7(ring, CP_SET_MODE, 1);
560 OUT_RING(ring, 0x0);
561
562 OUT_PKT7(ring, CP_SET_BIN_DATA5, 7);
563 OUT_RING(ring, CP_SET_BIN_DATA5_0_VSC_SIZE(pipe->w * pipe->h) |
564 CP_SET_BIN_DATA5_0_VSC_N(tile->n));
565 OUT_RELOC(ring, fd6_ctx->vsc_data, /* VSC_PIPE[p].DATA_ADDRESS */
566 (tile->p * A6XX_VSC_DATA_PITCH), 0, 0);
567 OUT_RELOC(ring, fd6_ctx->vsc_data, /* VSC_SIZE_ADDRESS + (p * 4) */
568 (tile->p * 4) + (32 * A6XX_VSC_DATA_PITCH), 0, 0);
569 OUT_RELOC(ring, fd6_ctx->vsc_data2,
570 (tile->p * A6XX_VSC_DATA2_PITCH), 0, 0);
571 } else {
572 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
573 OUT_RING(ring, 0x1);
574
575 OUT_PKT7(ring, CP_SET_MODE, 1);
576 OUT_RING(ring, 0x0);
577 }
578 }
579
580 static void
581 set_blit_scissor(struct fd_batch *batch, struct fd_ringbuffer *ring)
582 {
583 struct pipe_scissor_state blit_scissor;
584 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
585
586 blit_scissor.minx = batch->max_scissor.minx;
587 blit_scissor.miny = batch->max_scissor.miny;
588 blit_scissor.maxx = MIN2(pfb->width, batch->max_scissor.maxx);
589 blit_scissor.maxy = MIN2(pfb->height, batch->max_scissor.maxy);
590
591 OUT_PKT4(ring, REG_A6XX_RB_BLIT_SCISSOR_TL, 2);
592 OUT_RING(ring,
593 A6XX_RB_BLIT_SCISSOR_TL_X(blit_scissor.minx) |
594 A6XX_RB_BLIT_SCISSOR_TL_Y(blit_scissor.miny));
595 OUT_RING(ring,
596 A6XX_RB_BLIT_SCISSOR_BR_X(blit_scissor.maxx - 1) |
597 A6XX_RB_BLIT_SCISSOR_BR_Y(blit_scissor.maxy - 1));
598 }
599
600 static void
601 emit_blit(struct fd_batch *batch,
602 struct fd_ringbuffer *ring,
603 uint32_t base,
604 struct pipe_surface *psurf,
605 bool stencil)
606 {
607 struct fd_resource_slice *slice;
608 struct fd_resource *rsc = fd_resource(psurf->texture);
609 enum pipe_format pfmt = psurf->format;
610 uint32_t offset;
611
612 /* separate stencil case: */
613 if (stencil) {
614 rsc = rsc->stencil;
615 pfmt = rsc->base.format;
616 }
617
618 slice = fd_resource_slice(rsc, psurf->u.tex.level);
619 offset = fd_resource_offset(rsc, psurf->u.tex.level,
620 psurf->u.tex.first_layer);
621
622 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
623
624 enum a6xx_color_fmt format = fd6_pipe2color(pfmt);
625 uint32_t stride = slice->pitch * rsc->cpp;
626 uint32_t size = slice->size0;
627 enum a3xx_color_swap swap = rsc->tile_mode ? WZYX : fd6_pipe2swap(pfmt);
628 enum a3xx_msaa_samples samples =
629 fd_msaa_samples(rsc->base.nr_samples);
630 uint32_t tile_mode;
631
632 if (rsc->tile_mode &&
633 fd_resource_level_linear(&rsc->base, psurf->u.tex.level))
634 tile_mode = TILE6_LINEAR;
635 else
636 tile_mode = rsc->tile_mode;
637
638 OUT_PKT4(ring, REG_A6XX_RB_BLIT_DST_INFO, 5);
639 OUT_RING(ring,
640 A6XX_RB_BLIT_DST_INFO_TILE_MODE(tile_mode) |
641 A6XX_RB_BLIT_DST_INFO_SAMPLES(samples) |
642 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(format) |
643 A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(swap));
644 OUT_RELOCW(ring, rsc->bo, offset, 0, 0); /* RB_BLIT_DST_LO/HI */
645 OUT_RING(ring, A6XX_RB_BLIT_DST_PITCH(stride));
646 OUT_RING(ring, A6XX_RB_BLIT_DST_ARRAY_PITCH(size));
647
648 OUT_PKT4(ring, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
649 OUT_RING(ring, base);
650
651 fd6_emit_blit(batch, ring);
652 }
653
654 static void
655 emit_restore_blit(struct fd_batch *batch,
656 struct fd_ringbuffer *ring,
657 uint32_t base,
658 struct pipe_surface *psurf,
659 unsigned buffer)
660 {
661 uint32_t info = 0;
662 bool stencil = false;
663
664 switch (buffer) {
665 case FD_BUFFER_COLOR:
666 info |= A6XX_RB_BLIT_INFO_UNK0;
667 break;
668 case FD_BUFFER_STENCIL:
669 info |= A6XX_RB_BLIT_INFO_UNK0;
670 stencil = true;
671 break;
672 case FD_BUFFER_DEPTH:
673 info |= A6XX_RB_BLIT_INFO_DEPTH | A6XX_RB_BLIT_INFO_UNK0;
674 break;
675 }
676
677 if (util_format_is_pure_integer(psurf->format))
678 info |= A6XX_RB_BLIT_INFO_INTEGER;
679
680 OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
681 OUT_RING(ring, info | A6XX_RB_BLIT_INFO_GMEM);
682
683 emit_blit(batch, ring, base, psurf, stencil);
684 }
685
686 static void
687 emit_clears(struct fd_batch *batch, struct fd_ringbuffer *ring)
688 {
689 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
690 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
691 enum a3xx_msaa_samples samples = fd_msaa_samples(pfb->samples);
692
693 uint32_t buffers = batch->fast_cleared;
694
695 if (buffers & PIPE_CLEAR_COLOR) {
696
697 for (int i = 0; i < pfb->nr_cbufs; i++) {
698 union pipe_color_union *color = &batch->clear_color[i];
699 union util_color uc = {0};
700
701 if (!pfb->cbufs[i])
702 continue;
703
704 if (!(buffers & (PIPE_CLEAR_COLOR0 << i)))
705 continue;
706
707 enum pipe_format pfmt = pfb->cbufs[i]->format;
708
709 // XXX I think RB_CLEAR_COLOR_DWn wants to take into account SWAP??
710 union pipe_color_union swapped;
711 switch (fd6_pipe2swap(pfmt)) {
712 case WZYX:
713 swapped.ui[0] = color->ui[0];
714 swapped.ui[1] = color->ui[1];
715 swapped.ui[2] = color->ui[2];
716 swapped.ui[3] = color->ui[3];
717 break;
718 case WXYZ:
719 swapped.ui[2] = color->ui[0];
720 swapped.ui[1] = color->ui[1];
721 swapped.ui[0] = color->ui[2];
722 swapped.ui[3] = color->ui[3];
723 break;
724 case ZYXW:
725 swapped.ui[3] = color->ui[0];
726 swapped.ui[0] = color->ui[1];
727 swapped.ui[1] = color->ui[2];
728 swapped.ui[2] = color->ui[3];
729 break;
730 case XYZW:
731 swapped.ui[3] = color->ui[0];
732 swapped.ui[2] = color->ui[1];
733 swapped.ui[1] = color->ui[2];
734 swapped.ui[0] = color->ui[3];
735 break;
736 }
737
738 if (util_format_is_pure_uint(pfmt)) {
739 util_format_write_4ui(pfmt, swapped.ui, 0, &uc, 0, 0, 0, 1, 1);
740 } else if (util_format_is_pure_sint(pfmt)) {
741 util_format_write_4i(pfmt, swapped.i, 0, &uc, 0, 0, 0, 1, 1);
742 } else {
743 util_pack_color(swapped.f, pfmt, &uc);
744 }
745
746 OUT_PKT4(ring, REG_A6XX_RB_BLIT_DST_INFO, 1);
747 OUT_RING(ring, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR) |
748 A6XX_RB_BLIT_DST_INFO_SAMPLES(samples) |
749 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(fd6_pipe2color(pfmt)));
750
751 OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
752 OUT_RING(ring, A6XX_RB_BLIT_INFO_GMEM |
753 A6XX_RB_BLIT_INFO_CLEAR_MASK(0xf));
754
755 OUT_PKT4(ring, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
756 OUT_RING(ring, gmem->cbuf_base[i]);
757
758 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_88D0, 1);
759 OUT_RING(ring, 0);
760
761 OUT_PKT4(ring, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 4);
762 OUT_RING(ring, uc.ui[0]);
763 OUT_RING(ring, uc.ui[1]);
764 OUT_RING(ring, uc.ui[2]);
765 OUT_RING(ring, uc.ui[3]);
766
767 fd6_emit_blit(batch, ring);
768 }
769 }
770
771 const bool has_depth = pfb->zsbuf;
772 const bool has_separate_stencil =
773 has_depth && fd_resource(pfb->zsbuf->texture)->stencil;
774
775 /* First clear depth or combined depth/stencil. */
776 if ((has_depth && (buffers & PIPE_CLEAR_DEPTH)) ||
777 (!has_separate_stencil && (buffers & PIPE_CLEAR_STENCIL))) {
778 enum pipe_format pfmt = pfb->zsbuf->format;
779 uint32_t clear_value;
780 uint32_t mask = 0;
781
782 if (has_separate_stencil) {
783 pfmt = util_format_get_depth_only(pfb->zsbuf->format);
784 clear_value = util_pack_z(pfmt, batch->clear_depth);
785 } else {
786 pfmt = pfb->zsbuf->format;
787 clear_value = util_pack_z_stencil(pfmt, batch->clear_depth,
788 batch->clear_stencil);
789 }
790
791 if (buffers & PIPE_CLEAR_DEPTH)
792 mask |= 0x1;
793
794 if (!has_separate_stencil && (buffers & PIPE_CLEAR_STENCIL))
795 mask |= 0x2;
796
797 OUT_PKT4(ring, REG_A6XX_RB_BLIT_DST_INFO, 1);
798 OUT_RING(ring, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR) |
799 A6XX_RB_BLIT_DST_INFO_SAMPLES(samples) |
800 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(fd6_pipe2color(pfmt)));
801
802 OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
803 OUT_RING(ring, A6XX_RB_BLIT_INFO_GMEM |
804 // XXX UNK0 for separate stencil ??
805 A6XX_RB_BLIT_INFO_DEPTH |
806 A6XX_RB_BLIT_INFO_CLEAR_MASK(mask));
807
808 OUT_PKT4(ring, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
809 OUT_RING(ring, gmem->zsbuf_base[0]);
810
811 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_88D0, 1);
812 OUT_RING(ring, 0);
813
814 OUT_PKT4(ring, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 1);
815 OUT_RING(ring, clear_value);
816
817 fd6_emit_blit(batch, ring);
818 }
819
820 /* Then clear the separate stencil buffer in case of 32 bit depth
821 * formats with separate stencil. */
822 if (has_separate_stencil && (buffers & PIPE_CLEAR_STENCIL)) {
823 OUT_PKT4(ring, REG_A6XX_RB_BLIT_DST_INFO, 1);
824 OUT_RING(ring, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR) |
825 A6XX_RB_BLIT_DST_INFO_SAMPLES(samples) |
826 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(RB6_R8_UINT));
827
828 OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
829 OUT_RING(ring, A6XX_RB_BLIT_INFO_GMEM |
830 //A6XX_RB_BLIT_INFO_UNK0 |
831 A6XX_RB_BLIT_INFO_DEPTH |
832 A6XX_RB_BLIT_INFO_CLEAR_MASK(0x1));
833
834 OUT_PKT4(ring, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
835 OUT_RING(ring, gmem->zsbuf_base[1]);
836
837 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_88D0, 1);
838 OUT_RING(ring, 0);
839
840 OUT_PKT4(ring, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 1);
841 OUT_RING(ring, batch->clear_stencil & 0xff);
842
843 fd6_emit_blit(batch, ring);
844 }
845 }
846
847 /*
848 * transfer from system memory to gmem
849 */
850 static void
851 emit_restore_blits(struct fd_batch *batch, struct fd_ringbuffer *ring)
852 {
853 struct fd_context *ctx = batch->ctx;
854 struct fd_gmem_stateobj *gmem = &ctx->gmem;
855 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
856
857 if (batch->restore & FD_BUFFER_COLOR) {
858 unsigned i;
859 for (i = 0; i < pfb->nr_cbufs; i++) {
860 if (!pfb->cbufs[i])
861 continue;
862 if (!(batch->restore & (PIPE_CLEAR_COLOR0 << i)))
863 continue;
864 emit_restore_blit(batch, ring, gmem->cbuf_base[i], pfb->cbufs[i],
865 FD_BUFFER_COLOR);
866 }
867 }
868
869 if (batch->restore & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
870 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
871
872 if (!rsc->stencil || (batch->restore & FD_BUFFER_DEPTH)) {
873 emit_restore_blit(batch, ring, gmem->zsbuf_base[0], pfb->zsbuf,
874 FD_BUFFER_DEPTH);
875 }
876 if (rsc->stencil && (batch->restore & FD_BUFFER_STENCIL)) {
877 emit_restore_blit(batch, ring, gmem->zsbuf_base[1], pfb->zsbuf,
878 FD_BUFFER_STENCIL);
879 }
880 }
881 }
882
883 static void
884 prepare_tile_setup_ib(struct fd_batch *batch)
885 {
886 batch->tile_setup = fd_submit_new_ringbuffer(batch->submit, 0x1000,
887 FD_RINGBUFFER_STREAMING);
888
889 set_blit_scissor(batch, batch->tile_setup);
890
891 emit_restore_blits(batch, batch->tile_setup);
892 emit_clears(batch, batch->tile_setup);
893 }
894
895 /*
896 * transfer from system memory to gmem
897 */
898 static void
899 fd6_emit_tile_mem2gmem(struct fd_batch *batch, struct fd_tile *tile)
900 {
901 }
902
903 /* before IB to rendering cmds: */
904 static void
905 fd6_emit_tile_renderprep(struct fd_batch *batch, struct fd_tile *tile)
906 {
907 fd6_emit_ib(batch->gmem, batch->tile_setup);
908 }
909
910 static void
911 emit_resolve_blit(struct fd_batch *batch,
912 struct fd_ringbuffer *ring,
913 uint32_t base,
914 struct pipe_surface *psurf,
915 unsigned buffer)
916 {
917 uint32_t info = 0;
918 bool stencil = false;
919
920 if (!fd_resource(psurf->texture)->valid)
921 return;
922
923 switch (buffer) {
924 case FD_BUFFER_COLOR:
925 break;
926 case FD_BUFFER_STENCIL:
927 info |= A6XX_RB_BLIT_INFO_UNK0;
928 stencil = true;
929 break;
930 case FD_BUFFER_DEPTH:
931 info |= A6XX_RB_BLIT_INFO_DEPTH;
932 break;
933 }
934
935 if (util_format_is_pure_integer(psurf->format))
936 info |= A6XX_RB_BLIT_INFO_INTEGER;
937
938 OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
939 OUT_RING(ring, info);
940
941 emit_blit(batch, ring, base, psurf, stencil);
942 }
943
944 /*
945 * transfer from gmem to system memory (ie. normal RAM)
946 */
947
948 static void
949 prepare_tile_fini_ib(struct fd_batch *batch)
950 {
951 struct fd_context *ctx = batch->ctx;
952 struct fd_gmem_stateobj *gmem = &ctx->gmem;
953 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
954 struct fd_ringbuffer *ring;
955
956 batch->tile_fini = fd_submit_new_ringbuffer(batch->submit, 0x1000,
957 FD_RINGBUFFER_STREAMING);
958 ring = batch->tile_fini;
959
960 if (use_hw_binning(batch)) {
961 OUT_PKT7(ring, CP_SET_MARKER, 1);
962 OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(0x5) | 0x10);
963 }
964
965 OUT_PKT7(ring, CP_SET_DRAW_STATE, 3);
966 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
967 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
968 CP_SET_DRAW_STATE__0_GROUP_ID(0));
969 OUT_RING(ring, CP_SET_DRAW_STATE__1_ADDR_LO(0));
970 OUT_RING(ring, CP_SET_DRAW_STATE__2_ADDR_HI(0));
971
972 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
973 OUT_RING(ring, 0x0);
974
975 emit_marker6(ring, 7);
976 OUT_PKT7(ring, CP_SET_MARKER, 1);
977 OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE) | 0x10);
978 emit_marker6(ring, 7);
979
980 set_blit_scissor(batch, ring);
981
982 if (batch->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
983 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
984
985 if (!rsc->stencil || (batch->resolve & FD_BUFFER_DEPTH)) {
986 emit_resolve_blit(batch, ring,
987 gmem->zsbuf_base[0], pfb->zsbuf,
988 FD_BUFFER_DEPTH);
989 }
990 if (rsc->stencil && (batch->resolve & FD_BUFFER_STENCIL)) {
991 emit_resolve_blit(batch, ring,
992 gmem->zsbuf_base[1], pfb->zsbuf,
993 FD_BUFFER_STENCIL);
994 }
995 }
996
997 if (batch->resolve & FD_BUFFER_COLOR) {
998 unsigned i;
999 for (i = 0; i < pfb->nr_cbufs; i++) {
1000 if (!pfb->cbufs[i])
1001 continue;
1002 if (!(batch->resolve & (PIPE_CLEAR_COLOR0 << i)))
1003 continue;
1004 emit_resolve_blit(batch, ring, gmem->cbuf_base[i], pfb->cbufs[i],
1005 FD_BUFFER_COLOR);
1006 }
1007 }
1008 }
1009
1010 static void
1011 fd6_emit_tile_gmem2mem(struct fd_batch *batch, struct fd_tile *tile)
1012 {
1013 fd6_emit_ib(batch->gmem, batch->tile_fini);
1014 }
1015
1016 static void
1017 fd6_emit_tile_fini(struct fd_batch *batch)
1018 {
1019 struct fd_ringbuffer *ring = batch->gmem;
1020
1021 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_CNTL, 1);
1022 OUT_RING(ring, A6XX_GRAS_LRZ_CNTL_ENABLE | A6XX_GRAS_LRZ_CNTL_UNK3);
1023
1024 fd6_emit_lrz_flush(ring);
1025
1026 fd6_event_write(batch, ring, CACHE_FLUSH_TS, true);
1027 }
1028
1029 static void
1030 fd6_emit_sysmem_prep(struct fd_batch *batch)
1031 {
1032 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
1033 struct fd_ringbuffer *ring = batch->gmem;
1034
1035 fd6_emit_restore(batch, ring);
1036
1037 fd6_emit_lrz_flush(ring);
1038
1039 emit_marker6(ring, 7);
1040 OUT_PKT7(ring, CP_SET_MARKER, 1);
1041 OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(RM6_BYPASS) | 0x10); /* | 0x10 ? */
1042 emit_marker6(ring, 7);
1043
1044 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1045 OUT_RING(ring, 0x0);
1046
1047 fd6_event_write(batch, ring, PC_CCU_INVALIDATE_COLOR, false);
1048 fd6_cache_inv(batch, ring);
1049
1050 #if 0
1051 OUT_PKT4(ring, REG_A6XX_PC_POWER_CNTL, 1);
1052 OUT_RING(ring, 0x00000003); /* PC_POWER_CNTL */
1053 #endif
1054
1055 #if 0
1056 OUT_PKT4(ring, REG_A6XX_VFD_POWER_CNTL, 1);
1057 OUT_RING(ring, 0x00000003); /* VFD_POWER_CNTL */
1058 #endif
1059
1060 /* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */
1061 fd_wfi(batch, ring);
1062 OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
1063 OUT_RING(ring, 0x10000000); /* RB_CCU_CNTL */
1064
1065 set_scissor(ring, 0, 0, pfb->width - 1, pfb->height - 1);
1066
1067 set_window_offset(ring, 0, 0);
1068
1069 set_bin_size(ring, 0, 0, 0xc00000); /* 0xc00000 = BYPASS? */
1070
1071 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
1072 OUT_RING(ring, 0x1);
1073
1074 patch_draws(batch, IGNORE_VISIBILITY);
1075
1076 emit_zs(ring, pfb->zsbuf, NULL);
1077 emit_mrt(ring, pfb, NULL);
1078 emit_msaa(ring, pfb->samples);
1079 }
1080
1081 static void
1082 fd6_emit_sysmem_fini(struct fd_batch *batch)
1083 {
1084 struct fd_ringbuffer *ring = batch->gmem;
1085
1086 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1087 OUT_RING(ring, 0x0);
1088
1089 fd6_emit_lrz_flush(ring);
1090
1091 fd6_event_write(batch, ring, UNK_1D, true);
1092 }
1093
1094 void
1095 fd6_gmem_init(struct pipe_context *pctx)
1096 {
1097 struct fd_context *ctx = fd_context(pctx);
1098
1099 ctx->emit_tile_init = fd6_emit_tile_init;
1100 ctx->emit_tile_prep = fd6_emit_tile_prep;
1101 ctx->emit_tile_mem2gmem = fd6_emit_tile_mem2gmem;
1102 ctx->emit_tile_renderprep = fd6_emit_tile_renderprep;
1103 ctx->emit_tile_gmem2mem = fd6_emit_tile_gmem2mem;
1104 ctx->emit_tile_fini = fd6_emit_tile_fini;
1105 ctx->emit_sysmem_prep = fd6_emit_sysmem_prep;
1106 ctx->emit_sysmem_fini = fd6_emit_sysmem_fini;
1107 }