2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25 * Rob Clark <robclark@freedesktop.org>
30 #include "pipe/p_state.h"
31 #include "util/u_string.h"
32 #include "util/u_memory.h"
33 #include "util/u_inlines.h"
34 #include "util/format/u_format.h"
36 #include "freedreno_draw.h"
37 #include "freedreno_log.h"
38 #include "freedreno_state.h"
39 #include "freedreno_resource.h"
41 #include "fd6_blitter.h"
43 #include "fd6_context.h"
46 #include "fd6_program.h"
47 #include "fd6_format.h"
48 #include "fd6_resource.h"
53 * Emits the flags registers, suitable for RB_MRT_FLAG_BUFFER,
54 * RB_DEPTH_FLAG_BUFFER, SP_PS_2D_SRC_FLAGS, and RB_BLIT_FLAG_DST.
57 fd6_emit_flag_reference(struct fd_ringbuffer
*ring
, struct fd_resource
*rsc
,
60 if (fd_resource_ubwc_enabled(rsc
, level
)) {
61 OUT_RELOC(ring
, rsc
->bo
, fd_resource_ubwc_offset(rsc
, level
, layer
), 0, 0);
63 A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(rsc
->layout
.ubwc_slices
[level
].pitch
) |
64 A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(rsc
->layout
.ubwc_layer_size
>> 2));
66 OUT_RING(ring
, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_LO */
67 OUT_RING(ring
, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_HI */
68 OUT_RING(ring
, 0x00000000);
73 emit_mrt(struct fd_ringbuffer
*ring
, struct pipe_framebuffer_state
*pfb
,
74 const struct fd_gmem_stateobj
*gmem
)
76 unsigned char mrt_comp
[A6XX_MAX_RENDER_TARGETS
] = {0};
77 unsigned srgb_cntl
= 0;
80 unsigned max_layer_index
= 0;
82 for (i
= 0; i
< pfb
->nr_cbufs
; i
++) {
83 enum a6xx_format format
= 0;
84 enum a3xx_color_swap swap
= WZYX
;
85 bool sint
= false, uint
= false;
86 struct fd_resource
*rsc
= NULL
;
87 struct fdl_slice
*slice
= NULL
;
97 struct pipe_surface
*psurf
= pfb
->cbufs
[i
];
98 enum pipe_format pformat
= psurf
->format
;
99 rsc
= fd_resource(psurf
->texture
);
103 uint32_t base
= gmem
? gmem
->cbuf_base
[i
] : 0;
104 slice
= fd_resource_slice(rsc
, psurf
->u
.tex
.level
);
105 format
= fd6_pipe2color(pformat
);
106 sint
= util_format_is_pure_sint(pformat
);
107 uint
= util_format_is_pure_uint(pformat
);
109 if (util_format_is_srgb(pformat
))
110 srgb_cntl
|= (1 << i
);
112 offset
= fd_resource_offset(rsc
, psurf
->u
.tex
.level
,
113 psurf
->u
.tex
.first_layer
);
115 stride
= slice
->pitch
;
116 swap
= fd6_resource_swap(rsc
, pformat
);
118 tile_mode
= fd_resource_tile_mode(psurf
->texture
, psurf
->u
.tex
.level
);
119 max_layer_index
= psurf
->u
.tex
.last_layer
- psurf
->u
.tex
.first_layer
;
121 debug_assert((offset
+ slice
->size0
) <= fd_bo_size(rsc
->bo
));
124 A6XX_RB_MRT_BUF_INFO(i
,
125 .color_format
= format
,
126 .color_tile_mode
= tile_mode
,
128 A6XX_RB_MRT_PITCH(i
, .a6xx_rb_mrt_pitch
= stride
),
129 A6XX_RB_MRT_ARRAY_PITCH(i
, .a6xx_rb_mrt_array_pitch
= slice
->size0
),
130 A6XX_RB_MRT_BASE(i
, .bo
= rsc
->bo
, .bo_offset
= offset
),
131 A6XX_RB_MRT_BASE_GMEM(i
, .unknown
= base
));
134 A6XX_SP_FS_MRT_REG(i
, .color_format
= format
,
135 .color_sint
= sint
, .color_uint
= uint
));
137 OUT_PKT4(ring
, REG_A6XX_RB_MRT_FLAG_BUFFER(i
), 3);
138 fd6_emit_flag_reference(ring
, rsc
,
139 psurf
->u
.tex
.level
, psurf
->u
.tex
.first_layer
);
142 OUT_REG(ring
, A6XX_RB_SRGB_CNTL(.dword
= srgb_cntl
));
143 OUT_REG(ring
, A6XX_SP_SRGB_CNTL(.dword
= srgb_cntl
));
145 OUT_REG(ring
, A6XX_RB_RENDER_COMPONENTS(
153 .rt7
= mrt_comp
[7]));
155 OUT_REG(ring
, A6XX_SP_FS_RENDER_COMPONENTS(
163 .rt7
= mrt_comp
[7]));
165 OUT_REG(ring
, A6XX_GRAS_MAX_LAYER_INDEX(max_layer_index
));
169 emit_zs(struct fd_ringbuffer
*ring
, struct pipe_surface
*zsbuf
,
170 const struct fd_gmem_stateobj
*gmem
)
173 struct fd_resource
*rsc
= fd_resource(zsbuf
->texture
);
174 enum a6xx_depth_format fmt
= fd6_pipe2depth(zsbuf
->format
);
175 struct fdl_slice
*slice
= fd_resource_slice(rsc
, 0);
176 uint32_t stride
= slice
->pitch
;
177 uint32_t size
= slice
->size0
;
178 uint32_t base
= gmem
? gmem
->zsbuf_base
[0] : 0;
179 uint32_t offset
= fd_resource_offset(rsc
, zsbuf
->u
.tex
.level
,
180 zsbuf
->u
.tex
.first_layer
);
183 A6XX_RB_DEPTH_BUFFER_INFO(.depth_format
= fmt
),
184 A6XX_RB_DEPTH_BUFFER_PITCH(.a6xx_rb_depth_buffer_pitch
= stride
),
185 A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(.a6xx_rb_depth_buffer_array_pitch
= size
),
186 A6XX_RB_DEPTH_BUFFER_BASE(.bo
= rsc
->bo
, .bo_offset
= offset
),
187 A6XX_RB_DEPTH_BUFFER_BASE_GMEM(.dword
= base
));
189 OUT_REG(ring
, A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format
= fmt
));
191 OUT_PKT4(ring
, REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO
, 3);
192 fd6_emit_flag_reference(ring
, rsc
,
193 zsbuf
->u
.tex
.level
, zsbuf
->u
.tex
.first_layer
);
197 A6XX_GRAS_LRZ_BUFFER_BASE(.bo
= rsc
->lrz
),
198 A6XX_GRAS_LRZ_BUFFER_PITCH(.pitch
= rsc
->lrz_pitch
),
199 // XXX a6xx seems to use a different buffer here.. not sure what for..
200 A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO(0),
201 A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI(0));
203 OUT_PKT4(ring
, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO
, 5);
204 OUT_RING(ring
, 0x00000000);
205 OUT_RING(ring
, 0x00000000);
206 OUT_RING(ring
, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
207 OUT_RING(ring
, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO */
208 OUT_RING(ring
, 0x00000000);
211 /* NOTE: blob emits GRAS_LRZ_CNTL plus GRAZ_LRZ_BUFFER_BASE
212 * plus this CP_EVENT_WRITE at the end in it's own IB..
214 OUT_PKT7(ring
, CP_EVENT_WRITE
, 1);
215 OUT_RING(ring
, CP_EVENT_WRITE_0_EVENT(UNK_25
));
218 struct fdl_slice
*slice
= fd_resource_slice(rsc
->stencil
, 0);
219 stride
= slice
->pitch
;
221 uint32_t base
= gmem
? gmem
->zsbuf_base
[1] : 0;
224 A6XX_RB_STENCIL_INFO(.separate_stencil
= true),
225 A6XX_RB_STENCIL_BUFFER_PITCH(.a6xx_rb_stencil_buffer_pitch
= stride
),
226 A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(.a6xx_rb_stencil_buffer_array_pitch
= size
),
227 A6XX_RB_STENCIL_BUFFER_BASE(.bo
= rsc
->stencil
->bo
),
228 A6XX_RB_STENCIL_BUFFER_BASE_GMEM(.dword
= base
));
230 OUT_REG(ring
, A6XX_RB_STENCIL_INFO(0));
233 OUT_PKT4(ring
, REG_A6XX_RB_DEPTH_BUFFER_INFO
, 6);
234 OUT_RING(ring
, A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH6_NONE
));
235 OUT_RING(ring
, 0x00000000); /* RB_DEPTH_BUFFER_PITCH */
236 OUT_RING(ring
, 0x00000000); /* RB_DEPTH_BUFFER_ARRAY_PITCH */
237 OUT_RING(ring
, 0x00000000); /* RB_DEPTH_BUFFER_BASE_LO */
238 OUT_RING(ring
, 0x00000000); /* RB_DEPTH_BUFFER_BASE_HI */
239 OUT_RING(ring
, 0x00000000); /* RB_DEPTH_BUFFER_BASE_GMEM */
241 OUT_REG(ring
, A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format
= DEPTH6_NONE
));
243 OUT_PKT4(ring
, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO
, 5);
244 OUT_RING(ring
, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
245 OUT_RING(ring
, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
246 OUT_RING(ring
, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
247 OUT_RING(ring
, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO */
248 OUT_RING(ring
, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI */
250 OUT_REG(ring
, A6XX_RB_STENCIL_INFO(0));
255 use_hw_binning(struct fd_batch
*batch
)
257 const struct fd_gmem_stateobj
*gmem
= batch
->gmem_state
;
259 // TODO figure out hw limits for binning
261 return fd_binning_enabled
&& ((gmem
->nbins_x
* gmem
->nbins_y
) >= 2) &&
262 (batch
->num_draws
> 0);
266 patch_fb_read(struct fd_batch
*batch
)
268 const struct fd_gmem_stateobj
*gmem
= batch
->gmem_state
;
270 for (unsigned i
= 0; i
< fd_patch_num_elements(&batch
->fb_read_patches
); i
++) {
271 struct fd_cs_patch
*patch
= fd_patch_element(&batch
->fb_read_patches
, i
);
272 *patch
->cs
= patch
->val
| A6XX_TEX_CONST_2_PITCH(gmem
->bin_w
* gmem
->cbuf_cpp
[0]);
274 util_dynarray_clear(&batch
->fb_read_patches
);
278 update_render_cntl(struct fd_batch
*batch
, struct pipe_framebuffer_state
*pfb
, bool binning
)
280 struct fd_ringbuffer
*ring
= batch
->gmem
;
282 bool depth_ubwc_enable
= false;
283 uint32_t mrts_ubwc_enable
= 0;
287 struct fd_resource
*rsc
= fd_resource(pfb
->zsbuf
->texture
);
288 depth_ubwc_enable
= fd_resource_ubwc_enabled(rsc
, pfb
->zsbuf
->u
.tex
.level
);
291 for (i
= 0; i
< pfb
->nr_cbufs
; i
++) {
295 struct pipe_surface
*psurf
= pfb
->cbufs
[i
];
296 struct fd_resource
*rsc
= fd_resource(psurf
->texture
);
300 if (fd_resource_ubwc_enabled(rsc
, psurf
->u
.tex
.level
))
301 mrts_ubwc_enable
|= 1 << i
;
304 cntl
|= A6XX_RB_RENDER_CNTL_UNK4
;
306 cntl
|= A6XX_RB_RENDER_CNTL_BINNING
;
308 OUT_PKT7(ring
, CP_REG_WRITE
, 3);
309 OUT_RING(ring
, CP_REG_WRITE_0_TRACKER(TRACK_RENDER_CNTL
));
310 OUT_RING(ring
, REG_A6XX_RB_RENDER_CNTL
);
311 OUT_RING(ring
, cntl
|
312 COND(depth_ubwc_enable
, A6XX_RB_RENDER_CNTL_FLAG_DEPTH
) |
313 A6XX_RB_RENDER_CNTL_FLAG_MRTS(mrts_ubwc_enable
));
316 /* extra size to store VSC_DRAW_STRM_SIZE: */
317 #define VSC_DRAW_STRM_SIZE(pitch) ((pitch) * 32 + 0x100)
318 #define VSC_PRIM_STRM_SIZE(pitch) ((pitch) * 32)
321 update_vsc_pipe(struct fd_batch
*batch
)
323 struct fd_context
*ctx
= batch
->ctx
;
324 struct fd6_context
*fd6_ctx
= fd6_context(ctx
);
325 const struct fd_gmem_stateobj
*gmem
= batch
->gmem_state
;
326 struct fd_ringbuffer
*ring
= batch
->gmem
;
329 if (batch
->draw_strm_bits
/8 > fd6_ctx
->vsc_draw_strm_pitch
) {
330 if (fd6_ctx
->vsc_draw_strm
)
331 fd_bo_del(fd6_ctx
->vsc_draw_strm
);
332 fd6_ctx
->vsc_draw_strm
= NULL
;
333 /* Note: probably only need to align to 0x40, but aligning stronger
334 * reduces the odds that we will have to realloc again on the next
337 fd6_ctx
->vsc_draw_strm_pitch
= align(batch
->draw_strm_bits
/8, 0x4000);
338 debug_printf("pre-resize VSC_DRAW_STRM_PITCH to: 0x%x\n",
339 fd6_ctx
->vsc_draw_strm_pitch
);
342 if (batch
->prim_strm_bits
/8 > fd6_ctx
->vsc_prim_strm_pitch
) {
343 if (fd6_ctx
->vsc_prim_strm
)
344 fd_bo_del(fd6_ctx
->vsc_prim_strm
);
345 fd6_ctx
->vsc_prim_strm
= NULL
;
346 fd6_ctx
->vsc_prim_strm_pitch
= align(batch
->prim_strm_bits
/8, 0x4000);
347 debug_printf("pre-resize VSC_PRIM_STRM_PITCH to: 0x%x\n",
348 fd6_ctx
->vsc_prim_strm_pitch
);
351 if (!fd6_ctx
->vsc_draw_strm
) {
352 fd6_ctx
->vsc_draw_strm
= fd_bo_new(ctx
->screen
->dev
,
353 VSC_DRAW_STRM_SIZE(fd6_ctx
->vsc_draw_strm_pitch
),
354 DRM_FREEDRENO_GEM_TYPE_KMEM
, "vsc_draw_strm");
357 if (!fd6_ctx
->vsc_prim_strm
) {
358 fd6_ctx
->vsc_prim_strm
= fd_bo_new(ctx
->screen
->dev
,
359 VSC_PRIM_STRM_SIZE(fd6_ctx
->vsc_prim_strm_pitch
),
360 DRM_FREEDRENO_GEM_TYPE_KMEM
, "vsc_prim_strm");
364 A6XX_VSC_BIN_SIZE(.width
= gmem
->bin_w
, .height
= gmem
->bin_h
),
365 A6XX_VSC_DRAW_STRM_SIZE_ADDRESS(
366 .bo
= fd6_ctx
->vsc_draw_strm
,
367 .bo_offset
= 32 * fd6_ctx
->vsc_draw_strm_pitch
));
369 OUT_REG(ring
, A6XX_VSC_BIN_COUNT(.nx
= gmem
->nbins_x
,
370 .ny
= gmem
->nbins_y
));
372 OUT_PKT4(ring
, REG_A6XX_VSC_PIPE_CONFIG_REG(0), 32);
373 for (i
= 0; i
< 32; i
++) {
374 const struct fd_vsc_pipe
*pipe
= &gmem
->vsc_pipe
[i
];
375 OUT_RING(ring
, A6XX_VSC_PIPE_CONFIG_REG_X(pipe
->x
) |
376 A6XX_VSC_PIPE_CONFIG_REG_Y(pipe
->y
) |
377 A6XX_VSC_PIPE_CONFIG_REG_W(pipe
->w
) |
378 A6XX_VSC_PIPE_CONFIG_REG_H(pipe
->h
));
382 A6XX_VSC_PRIM_STRM_ADDRESS(.bo
= fd6_ctx
->vsc_prim_strm
),
383 A6XX_VSC_PRIM_STRM_PITCH(.dword
= fd6_ctx
->vsc_prim_strm_pitch
),
384 A6XX_VSC_PRIM_STRM_ARRAY_PITCH(.dword
= fd_bo_size(fd6_ctx
->vsc_prim_strm
)));
387 A6XX_VSC_DRAW_STRM_ADDRESS(.bo
= fd6_ctx
->vsc_draw_strm
),
388 A6XX_VSC_DRAW_STRM_PITCH(.dword
= fd6_ctx
->vsc_draw_strm_pitch
),
389 A6XX_VSC_DRAW_STRM_ARRAY_PITCH(.dword
= fd_bo_size(fd6_ctx
->vsc_draw_strm
)));
392 /* TODO we probably have more than 8 scratch regs.. although the first
393 * 8 is what kernel dumps, and it is kinda useful to be able to see
394 * the value in kernel traces
396 #define OVERFLOW_FLAG_REG REG_A6XX_CP_SCRATCH_REG(0)
399 * If overflow is detected, either 0x1 (VSC_DRAW_STRM overflow) or 0x3
400 * (VSC_PRIM_STRM overflow) plus the size of the overflowed buffer is
401 * written to control->vsc_overflow. This allows the CPU to
402 * detect which buffer overflowed (and, since the current size is
403 * encoded as well, this protects against already-submitted but
404 * not executed batches from fooling the CPU into increasing the
405 * size again unnecessarily).
407 * To conditionally use VSC data in draw pass only if there is no
408 * overflow, we use a scratch reg (OVERFLOW_FLAG_REG) to hold 1
409 * if no overflow, or 0 in case of overflow. The value is inverted
410 * to make the CP_COND_REG_EXEC stuff easier.
413 emit_vsc_overflow_test(struct fd_batch
*batch
)
415 struct fd_ringbuffer
*ring
= batch
->gmem
;
416 const struct fd_gmem_stateobj
*gmem
= batch
->gmem_state
;
417 struct fd6_context
*fd6_ctx
= fd6_context(batch
->ctx
);
419 debug_assert((fd6_ctx
->vsc_draw_strm_pitch
& 0x3) == 0);
420 debug_assert((fd6_ctx
->vsc_prim_strm_pitch
& 0x3) == 0);
422 /* Clear vsc_scratch: */
423 OUT_PKT7(ring
, CP_MEM_WRITE
, 3);
424 OUT_RELOC(ring
, control_ptr(fd6_ctx
, vsc_scratch
));
427 /* Check for overflow, write vsc_scratch if detected: */
428 for (int i
= 0; i
< gmem
->num_vsc_pipes
; i
++) {
429 OUT_PKT7(ring
, CP_COND_WRITE5
, 8);
430 OUT_RING(ring
, CP_COND_WRITE5_0_FUNCTION(WRITE_GE
) |
431 CP_COND_WRITE5_0_WRITE_MEMORY
);
432 OUT_RING(ring
, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_DRAW_STRM_SIZE_REG(i
)));
433 OUT_RING(ring
, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
434 OUT_RING(ring
, CP_COND_WRITE5_3_REF(fd6_ctx
->vsc_draw_strm_pitch
));
435 OUT_RING(ring
, CP_COND_WRITE5_4_MASK(~0));
436 OUT_RELOC(ring
, control_ptr(fd6_ctx
, vsc_scratch
)); /* WRITE_ADDR_LO/HI */
437 OUT_RING(ring
, CP_COND_WRITE5_7_WRITE_DATA(1 + fd6_ctx
->vsc_draw_strm_pitch
));
439 OUT_PKT7(ring
, CP_COND_WRITE5
, 8);
440 OUT_RING(ring
, CP_COND_WRITE5_0_FUNCTION(WRITE_GE
) |
441 CP_COND_WRITE5_0_WRITE_MEMORY
);
442 OUT_RING(ring
, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_PRIM_STRM_SIZE_REG(i
)));
443 OUT_RING(ring
, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
444 OUT_RING(ring
, CP_COND_WRITE5_3_REF(fd6_ctx
->vsc_prim_strm_pitch
));
445 OUT_RING(ring
, CP_COND_WRITE5_4_MASK(~0));
446 OUT_RELOC(ring
, control_ptr(fd6_ctx
, vsc_scratch
)); /* WRITE_ADDR_LO/HI */
447 OUT_RING(ring
, CP_COND_WRITE5_7_WRITE_DATA(3 + fd6_ctx
->vsc_prim_strm_pitch
));
450 OUT_PKT7(ring
, CP_WAIT_MEM_WRITES
, 0);
452 OUT_PKT7(ring
, CP_WAIT_FOR_ME
, 0);
454 OUT_PKT7(ring
, CP_MEM_TO_REG
, 3);
455 OUT_RING(ring
, CP_MEM_TO_REG_0_REG(OVERFLOW_FLAG_REG
) |
456 CP_MEM_TO_REG_0_CNT(0));
457 OUT_RELOC(ring
, control_ptr(fd6_ctx
, vsc_scratch
)); /* SRC_LO/HI */
460 * This is a bit awkward, we really want a way to invert the
461 * CP_REG_TEST/CP_COND_REG_EXEC logic, so that we can conditionally
462 * execute cmds to use hwbinning when a bit is *not* set. This
463 * dance is to invert OVERFLOW_FLAG_REG
465 * A CP_NOP packet is used to skip executing the 'else' clause
469 BEGIN_RING(ring
, 10); /* ensure if/else doesn't get split */
471 /* b0 will be set if VSC_DRAW_STRM or VSC_PRIM_STRM overflow: */
472 OUT_PKT7(ring
, CP_REG_TEST
, 1);
473 OUT_RING(ring
, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG
) |
474 A6XX_CP_REG_TEST_0_BIT(0) |
475 A6XX_CP_REG_TEST_0_WAIT_FOR_ME
);
477 OUT_PKT7(ring
, CP_COND_REG_EXEC
, 2);
478 OUT_RING(ring
, CP_COND_REG_EXEC_0_MODE(PRED_TEST
));
479 OUT_RING(ring
, CP_COND_REG_EXEC_1_DWORDS(7));
483 * On overflow, mirror the value to control->vsc_overflow
484 * which CPU is checking to detect overflow (see
485 * check_vsc_overflow())
487 OUT_PKT7(ring
, CP_REG_TO_MEM
, 3);
488 OUT_RING(ring
, CP_REG_TO_MEM_0_REG(OVERFLOW_FLAG_REG
) |
489 CP_REG_TO_MEM_0_CNT(1 - 1));
490 OUT_RELOC(ring
, control_ptr(fd6_ctx
, vsc_overflow
));
492 OUT_PKT4(ring
, OVERFLOW_FLAG_REG
, 1);
495 OUT_PKT7(ring
, CP_NOP
, 2); /* skip 'else' when 'if' is taken */
497 OUT_PKT4(ring
, OVERFLOW_FLAG_REG
, 1);
503 check_vsc_overflow(struct fd_context
*ctx
)
505 struct fd6_context
*fd6_ctx
= fd6_context(ctx
);
506 struct fd6_control
*control
= fd_bo_map(fd6_ctx
->control_mem
);
507 uint32_t vsc_overflow
= control
->vsc_overflow
;
512 /* clear overflow flag: */
513 control
->vsc_overflow
= 0;
515 unsigned buffer
= vsc_overflow
& 0x3;
516 unsigned size
= vsc_overflow
& ~0x3;
519 /* VSC_DRAW_STRM overflow: */
521 if (size
< fd6_ctx
->vsc_draw_strm_pitch
) {
522 /* we've already increased the size, this overflow is
523 * from a batch submitted before resize, but executed
529 fd_bo_del(fd6_ctx
->vsc_draw_strm
);
530 fd6_ctx
->vsc_draw_strm
= NULL
;
531 fd6_ctx
->vsc_draw_strm_pitch
*= 2;
533 debug_printf("resized VSC_DRAW_STRM_PITCH to: 0x%x\n",
534 fd6_ctx
->vsc_draw_strm_pitch
);
536 } else if (buffer
== 0x3) {
537 /* VSC_PRIM_STRM overflow: */
539 if (size
< fd6_ctx
->vsc_prim_strm_pitch
) {
540 /* we've already increased the size */
544 fd_bo_del(fd6_ctx
->vsc_prim_strm
);
545 fd6_ctx
->vsc_prim_strm
= NULL
;
546 fd6_ctx
->vsc_prim_strm_pitch
*= 2;
548 debug_printf("resized VSC_PRIM_STRM_PITCH to: 0x%x\n",
549 fd6_ctx
->vsc_prim_strm_pitch
);
552 /* NOTE: it's possible, for example, for overflow to corrupt the
553 * control page. I mostly just see this hit if I set initial VSC
554 * buffer size extremely small. Things still seem to recover,
555 * but maybe we should pre-emptively realloc vsc_data/vsc_data2
556 * and hope for different memory placement?
558 DBG("invalid vsc_overflow value: 0x%08x", vsc_overflow
);
563 * Emit conditional CP_INDIRECT_BRANCH based on VSC_STATE[p], ie. the IB
564 * is skipped for tiles that have no visible geometry.
567 emit_conditional_ib(struct fd_batch
*batch
, const struct fd_tile
*tile
,
568 struct fd_ringbuffer
*target
)
570 struct fd_ringbuffer
*ring
= batch
->gmem
;
572 if (target
->cur
== target
->start
)
575 emit_marker6(ring
, 6);
577 unsigned count
= fd_ringbuffer_cmd_count(target
);
579 BEGIN_RING(ring
, 5 + 4 * count
); /* ensure conditional doesn't get split */
581 OUT_PKT7(ring
, CP_REG_TEST
, 1);
582 OUT_RING(ring
, A6XX_CP_REG_TEST_0_REG(REG_A6XX_VSC_STATE_REG(tile
->p
)) |
583 A6XX_CP_REG_TEST_0_BIT(tile
->n
) |
584 A6XX_CP_REG_TEST_0_WAIT_FOR_ME
);
586 OUT_PKT7(ring
, CP_COND_REG_EXEC
, 2);
587 OUT_RING(ring
, CP_COND_REG_EXEC_0_MODE(PRED_TEST
));
588 OUT_RING(ring
, CP_COND_REG_EXEC_1_DWORDS(4 * count
));
590 for (unsigned i
= 0; i
< count
; i
++) {
592 OUT_PKT7(ring
, CP_INDIRECT_BUFFER
, 3);
593 dwords
= fd_ringbuffer_emit_reloc_ring_full(ring
, target
, i
) / 4;
595 OUT_RING(ring
, dwords
);
598 emit_marker6(ring
, 6);
602 set_scissor(struct fd_ringbuffer
*ring
, uint32_t x1
, uint32_t y1
, uint32_t x2
, uint32_t y2
)
605 A6XX_GRAS_SC_WINDOW_SCISSOR_TL(.x
= x1
, .y
= y1
),
606 A6XX_GRAS_SC_WINDOW_SCISSOR_BR(.x
= x2
, .y
= y2
));
609 A6XX_GRAS_RESOLVE_CNTL_1(.x
= x1
, .y
= y1
),
610 A6XX_GRAS_RESOLVE_CNTL_2(.x
= x2
, .y
= y2
));
614 set_bin_size(struct fd_ringbuffer
*ring
, uint32_t w
, uint32_t h
, uint32_t flag
)
616 OUT_REG(ring
, A6XX_GRAS_BIN_CONTROL(.binw
= w
, .binh
= h
, .dword
= flag
));
617 OUT_REG(ring
, A6XX_RB_BIN_CONTROL(.binw
= w
, .binh
= h
, .dword
= flag
));
618 /* no flag for RB_BIN_CONTROL2... */
619 OUT_REG(ring
, A6XX_RB_BIN_CONTROL2(.binw
= w
, .binh
= h
));
623 emit_binning_pass(struct fd_batch
*batch
)
625 struct fd_ringbuffer
*ring
= batch
->gmem
;
626 const struct fd_gmem_stateobj
*gmem
= batch
->gmem_state
;
627 struct fd6_context
*fd6_ctx
= fd6_context(batch
->ctx
);
629 debug_assert(!batch
->tessellation
);
631 set_scissor(ring
, 0, 0, gmem
->width
- 1, gmem
->height
- 1);
633 emit_marker6(ring
, 7);
634 OUT_PKT7(ring
, CP_SET_MARKER
, 1);
635 OUT_RING(ring
, A6XX_CP_SET_MARKER_0_MODE(RM6_BINNING
));
636 emit_marker6(ring
, 7);
638 OUT_PKT7(ring
, CP_SET_VISIBILITY_OVERRIDE
, 1);
641 OUT_PKT7(ring
, CP_SET_MODE
, 1);
646 OUT_REG(ring
, A6XX_VFD_MODE_CNTL(.binning_pass
= true));
648 update_vsc_pipe(batch
);
650 OUT_PKT4(ring
, REG_A6XX_PC_UNKNOWN_9805
, 1);
651 OUT_RING(ring
, fd6_ctx
->magic
.PC_UNKNOWN_9805
);
653 OUT_PKT4(ring
, REG_A6XX_SP_UNKNOWN_A0F8
, 1);
654 OUT_RING(ring
, fd6_ctx
->magic
.SP_UNKNOWN_A0F8
);
656 OUT_PKT7(ring
, CP_EVENT_WRITE
, 1);
657 OUT_RING(ring
, UNK_2C
);
659 OUT_PKT4(ring
, REG_A6XX_RB_WINDOW_OFFSET
, 1);
660 OUT_RING(ring
, A6XX_RB_WINDOW_OFFSET_X(0) |
661 A6XX_RB_WINDOW_OFFSET_Y(0));
663 OUT_PKT4(ring
, REG_A6XX_SP_TP_WINDOW_OFFSET
, 1);
664 OUT_RING(ring
, A6XX_SP_TP_WINDOW_OFFSET_X(0) |
665 A6XX_SP_TP_WINDOW_OFFSET_Y(0));
667 /* emit IB to binning drawcmds: */
668 fd_log(batch
, "GMEM: START BINNING IB");
669 fd6_emit_ib(ring
, batch
->draw
);
670 fd_log(batch
, "GMEM: END BINNING IB");
674 OUT_PKT7(ring
, CP_SET_DRAW_STATE
, 3);
675 OUT_RING(ring
, CP_SET_DRAW_STATE__0_COUNT(0) |
676 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
677 CP_SET_DRAW_STATE__0_GROUP_ID(0));
678 OUT_RING(ring
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
679 OUT_RING(ring
, CP_SET_DRAW_STATE__2_ADDR_HI(0));
681 OUT_PKT7(ring
, CP_EVENT_WRITE
, 1);
682 OUT_RING(ring
, UNK_2D
);
684 fd6_cache_inv(batch
, ring
);
685 fd6_cache_flush(batch
, ring
);
688 OUT_PKT7(ring
, CP_WAIT_FOR_ME
, 0);
690 fd_log(batch
, "START VSC OVERFLOW TEST");
691 emit_vsc_overflow_test(batch
);
692 fd_log(batch
, "END VSC OVERFLOW TEST");
694 OUT_PKT7(ring
, CP_SET_VISIBILITY_OVERRIDE
, 1);
697 OUT_PKT7(ring
, CP_SET_MODE
, 1);
702 OUT_PKT4(ring
, REG_A6XX_RB_CCU_CNTL
, 1);
703 OUT_RING(ring
, fd6_ctx
->magic
.RB_CCU_CNTL_gmem
);
707 emit_msaa(struct fd_ringbuffer
*ring
, unsigned nr
)
709 enum a3xx_msaa_samples samples
= fd_msaa_samples(nr
);
711 OUT_PKT4(ring
, REG_A6XX_SP_TP_RAS_MSAA_CNTL
, 2);
712 OUT_RING(ring
, A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(samples
));
713 OUT_RING(ring
, A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(samples
) |
714 COND(samples
== MSAA_ONE
, A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE
));
716 OUT_PKT4(ring
, REG_A6XX_GRAS_RAS_MSAA_CNTL
, 2);
717 OUT_RING(ring
, A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(samples
));
718 OUT_RING(ring
, A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(samples
) |
719 COND(samples
== MSAA_ONE
, A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE
));
721 OUT_PKT4(ring
, REG_A6XX_RB_RAS_MSAA_CNTL
, 2);
722 OUT_RING(ring
, A6XX_RB_RAS_MSAA_CNTL_SAMPLES(samples
));
723 OUT_RING(ring
, A6XX_RB_DEST_MSAA_CNTL_SAMPLES(samples
) |
724 COND(samples
== MSAA_ONE
, A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE
));
726 OUT_PKT4(ring
, REG_A6XX_RB_MSAA_CNTL
, 1);
727 OUT_RING(ring
, A6XX_RB_MSAA_CNTL_SAMPLES(samples
));
730 static void prepare_tile_setup_ib(struct fd_batch
*batch
);
731 static void prepare_tile_fini_ib(struct fd_batch
*batch
);
733 /* before first tile */
735 fd6_emit_tile_init(struct fd_batch
*batch
)
737 struct fd_context
*ctx
= batch
->ctx
;
738 struct fd_ringbuffer
*ring
= batch
->gmem
;
739 struct pipe_framebuffer_state
*pfb
= &batch
->framebuffer
;
740 const struct fd_gmem_stateobj
*gmem
= batch
->gmem_state
;
742 fd6_emit_restore(batch
, ring
);
744 fd6_emit_lrz_flush(ring
);
746 if (batch
->lrz_clear
) {
747 fd_log(batch
, "START LRZ CLEAR");
748 fd6_emit_ib(ring
, batch
->lrz_clear
);
749 fd_log(batch
, "END LRZ CLEAR");
752 fd6_cache_inv(batch
, ring
);
754 prepare_tile_setup_ib(batch
);
755 prepare_tile_fini_ib(batch
);
757 OUT_PKT7(ring
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
760 /* blob controls "local" in IB2, but I think that is not required */
761 OUT_PKT7(ring
, CP_SKIP_IB2_ENABLE_LOCAL
, 1);
765 OUT_PKT4(ring
, REG_A6XX_RB_CCU_CNTL
, 1);
766 OUT_RING(ring
, fd6_context(ctx
)->magic
.RB_CCU_CNTL_gmem
);
768 emit_zs(ring
, pfb
->zsbuf
, batch
->gmem_state
);
769 emit_mrt(ring
, pfb
, batch
->gmem_state
);
770 emit_msaa(ring
, pfb
->samples
);
771 patch_fb_read(batch
);
773 if (use_hw_binning(batch
)) {
774 /* enable stream-out during binning pass: */
775 OUT_PKT4(ring
, REG_A6XX_VPC_SO_OVERRIDE
, 1);
778 set_bin_size(ring
, gmem
->bin_w
, gmem
->bin_h
,
779 A6XX_RB_BIN_CONTROL_BINNING_PASS
| 0x6000000);
780 update_render_cntl(batch
, pfb
, true);
781 emit_binning_pass(batch
);
783 /* and disable stream-out for draw pass: */
784 OUT_PKT4(ring
, REG_A6XX_VPC_SO_OVERRIDE
, 1);
785 OUT_RING(ring
, A6XX_VPC_SO_OVERRIDE_SO_DISABLE
);
788 * NOTE: even if we detect VSC overflow and disable use of
789 * visibility stream in draw pass, it is still safe to execute
790 * the reset of these cmds:
793 // NOTE a618 not setting .USE_VIZ .. from a quick check on a630, it
794 // does not appear that this bit changes much (ie. it isn't actually
795 // .USE_VIZ like previous gens)
796 set_bin_size(ring
, gmem
->bin_w
, gmem
->bin_h
,
797 A6XX_RB_BIN_CONTROL_USE_VIZ
| 0x6000000);
799 OUT_PKT4(ring
, REG_A6XX_VFD_MODE_CNTL
, 1);
802 OUT_PKT4(ring
, REG_A6XX_PC_UNKNOWN_9805
, 1);
803 OUT_RING(ring
, fd6_context(ctx
)->magic
.PC_UNKNOWN_9805
);
805 OUT_PKT4(ring
, REG_A6XX_SP_UNKNOWN_A0F8
, 1);
806 OUT_RING(ring
, fd6_context(ctx
)->magic
.SP_UNKNOWN_A0F8
);
808 OUT_PKT7(ring
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
811 /* no binning pass, so enable stream-out for draw pass:: */
812 OUT_PKT4(ring
, REG_A6XX_VPC_SO_OVERRIDE
, 1);
815 set_bin_size(ring
, gmem
->bin_w
, gmem
->bin_h
, 0x6000000);
818 update_render_cntl(batch
, pfb
, false);
822 set_window_offset(struct fd_ringbuffer
*ring
, uint32_t x1
, uint32_t y1
)
824 OUT_PKT4(ring
, REG_A6XX_RB_WINDOW_OFFSET
, 1);
825 OUT_RING(ring
, A6XX_RB_WINDOW_OFFSET_X(x1
) |
826 A6XX_RB_WINDOW_OFFSET_Y(y1
));
828 OUT_PKT4(ring
, REG_A6XX_RB_WINDOW_OFFSET2
, 1);
829 OUT_RING(ring
, A6XX_RB_WINDOW_OFFSET2_X(x1
) |
830 A6XX_RB_WINDOW_OFFSET2_Y(y1
));
832 OUT_PKT4(ring
, REG_A6XX_SP_WINDOW_OFFSET
, 1);
833 OUT_RING(ring
, A6XX_SP_WINDOW_OFFSET_X(x1
) |
834 A6XX_SP_WINDOW_OFFSET_Y(y1
));
836 OUT_PKT4(ring
, REG_A6XX_SP_TP_WINDOW_OFFSET
, 1);
837 OUT_RING(ring
, A6XX_SP_TP_WINDOW_OFFSET_X(x1
) |
838 A6XX_SP_TP_WINDOW_OFFSET_Y(y1
));
841 /* before mem2gmem */
843 fd6_emit_tile_prep(struct fd_batch
*batch
, const struct fd_tile
*tile
)
845 struct fd_context
*ctx
= batch
->ctx
;
846 const struct fd_gmem_stateobj
*gmem
= batch
->gmem_state
;
847 struct fd6_context
*fd6_ctx
= fd6_context(ctx
);
848 struct fd_ringbuffer
*ring
= batch
->gmem
;
850 emit_marker6(ring
, 7);
851 OUT_PKT7(ring
, CP_SET_MARKER
, 1);
852 OUT_RING(ring
, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM
));
853 emit_marker6(ring
, 7);
855 uint32_t x1
= tile
->xoff
;
856 uint32_t y1
= tile
->yoff
;
857 uint32_t x2
= tile
->xoff
+ tile
->bin_w
- 1;
858 uint32_t y2
= tile
->yoff
+ tile
->bin_h
- 1;
860 set_scissor(ring
, x1
, y1
, x2
, y2
);
862 if (use_hw_binning(batch
)) {
863 const struct fd_vsc_pipe
*pipe
= &gmem
->vsc_pipe
[tile
->p
];
865 OUT_PKT7(ring
, CP_WAIT_FOR_ME
, 0);
867 OUT_PKT7(ring
, CP_SET_MODE
, 1);
871 * Conditionally execute if no VSC overflow:
874 BEGIN_RING(ring
, 18); /* ensure if/else doesn't get split */
876 OUT_PKT7(ring
, CP_REG_TEST
, 1);
877 OUT_RING(ring
, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG
) |
878 A6XX_CP_REG_TEST_0_BIT(0) |
879 A6XX_CP_REG_TEST_0_WAIT_FOR_ME
);
881 OUT_PKT7(ring
, CP_COND_REG_EXEC
, 2);
882 OUT_RING(ring
, CP_COND_REG_EXEC_0_MODE(PRED_TEST
));
883 OUT_RING(ring
, CP_COND_REG_EXEC_1_DWORDS(11));
885 /* if (no overflow) */ {
886 OUT_PKT7(ring
, CP_SET_BIN_DATA5
, 7);
887 OUT_RING(ring
, CP_SET_BIN_DATA5_0_VSC_SIZE(pipe
->w
* pipe
->h
) |
888 CP_SET_BIN_DATA5_0_VSC_N(tile
->n
));
889 OUT_RELOC(ring
, fd6_ctx
->vsc_draw_strm
, /* per-pipe draw-stream address */
890 (tile
->p
* fd6_ctx
->vsc_draw_strm_pitch
), 0, 0);
891 OUT_RELOC(ring
, fd6_ctx
->vsc_draw_strm
, /* VSC_DRAW_STRM_ADDRESS + (p * 4) */
892 (tile
->p
* 4) + (32 * fd6_ctx
->vsc_draw_strm_pitch
), 0, 0);
893 OUT_RELOC(ring
, fd6_ctx
->vsc_prim_strm
,
894 (tile
->p
* fd6_ctx
->vsc_prim_strm_pitch
), 0, 0);
896 OUT_PKT7(ring
, CP_SET_VISIBILITY_OVERRIDE
, 1);
899 /* use a NOP packet to skip over the 'else' side: */
900 OUT_PKT7(ring
, CP_NOP
, 2);
902 OUT_PKT7(ring
, CP_SET_VISIBILITY_OVERRIDE
, 1);
906 set_window_offset(ring
, x1
, y1
);
908 const struct fd_gmem_stateobj
*gmem
= batch
->gmem_state
;
909 set_bin_size(ring
, gmem
->bin_w
, gmem
->bin_h
, 0x6000000);
911 OUT_PKT7(ring
, CP_SET_MODE
, 1);
914 set_window_offset(ring
, x1
, y1
);
916 OUT_PKT7(ring
, CP_SET_VISIBILITY_OVERRIDE
, 1);
919 OUT_PKT7(ring
, CP_SET_MODE
, 1);
925 set_blit_scissor(struct fd_batch
*batch
, struct fd_ringbuffer
*ring
)
927 struct pipe_scissor_state blit_scissor
= batch
->max_scissor
;
929 blit_scissor
.minx
= ROUND_DOWN_TO(blit_scissor
.minx
, 16);
930 blit_scissor
.miny
= ROUND_DOWN_TO(blit_scissor
.miny
, 4);
931 blit_scissor
.maxx
= ALIGN(blit_scissor
.maxx
, 16);
932 blit_scissor
.maxy
= ALIGN(blit_scissor
.maxy
, 4);
934 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_SCISSOR_TL
, 2);
936 A6XX_RB_BLIT_SCISSOR_TL_X(blit_scissor
.minx
) |
937 A6XX_RB_BLIT_SCISSOR_TL_Y(blit_scissor
.miny
));
939 A6XX_RB_BLIT_SCISSOR_BR_X(blit_scissor
.maxx
- 1) |
940 A6XX_RB_BLIT_SCISSOR_BR_Y(blit_scissor
.maxy
- 1));
944 emit_blit(struct fd_batch
*batch
,
945 struct fd_ringbuffer
*ring
,
947 struct pipe_surface
*psurf
,
950 struct fdl_slice
*slice
;
951 struct fd_resource
*rsc
= fd_resource(psurf
->texture
);
952 enum pipe_format pfmt
= psurf
->format
;
956 debug_assert(psurf
->u
.tex
.first_layer
== psurf
->u
.tex
.last_layer
);
958 /* separate stencil case: */
961 pfmt
= rsc
->base
.format
;
964 slice
= fd_resource_slice(rsc
, psurf
->u
.tex
.level
);
965 offset
= fd_resource_offset(rsc
, psurf
->u
.tex
.level
,
966 psurf
->u
.tex
.first_layer
);
967 ubwc_enabled
= fd_resource_ubwc_enabled(rsc
, psurf
->u
.tex
.level
);
969 debug_assert(psurf
->u
.tex
.first_layer
== psurf
->u
.tex
.last_layer
);
971 enum a6xx_format format
= fd6_pipe2color(pfmt
);
972 uint32_t stride
= slice
->pitch
;
973 uint32_t size
= slice
->size0
;
974 enum a3xx_color_swap swap
= fd6_resource_swap(rsc
, pfmt
);
975 enum a3xx_msaa_samples samples
=
976 fd_msaa_samples(rsc
->base
.nr_samples
);
977 uint32_t tile_mode
= fd_resource_tile_mode(&rsc
->base
, psurf
->u
.tex
.level
);
980 A6XX_RB_BLIT_DST_INFO(.tile_mode
= tile_mode
, .samples
= samples
,
981 .color_format
= format
, .color_swap
= swap
, .flags
= ubwc_enabled
),
982 A6XX_RB_BLIT_DST(.bo
= rsc
->bo
, .bo_offset
= offset
),
983 A6XX_RB_BLIT_DST_PITCH(.a6xx_rb_blit_dst_pitch
= stride
),
984 A6XX_RB_BLIT_DST_ARRAY_PITCH(.a6xx_rb_blit_dst_array_pitch
= size
));
986 OUT_REG(ring
, A6XX_RB_BLIT_BASE_GMEM(.dword
= base
));
989 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_FLAG_DST_LO
, 3);
990 fd6_emit_flag_reference(ring
, rsc
,
991 psurf
->u
.tex
.level
, psurf
->u
.tex
.first_layer
);
994 fd6_emit_blit(batch
, ring
);
998 emit_restore_blit(struct fd_batch
*batch
,
999 struct fd_ringbuffer
*ring
,
1001 struct pipe_surface
*psurf
,
1004 bool stencil
= (buffer
== FD_BUFFER_STENCIL
);
1006 OUT_REG(ring
, A6XX_RB_BLIT_INFO(
1007 .gmem
= true, .unk0
= true,
1008 .depth
= (buffer
== FD_BUFFER_DEPTH
),
1009 .integer
= util_format_is_pure_integer(psurf
->format
)));
1011 emit_blit(batch
, ring
, base
, psurf
, stencil
);
1015 emit_clears(struct fd_batch
*batch
, struct fd_ringbuffer
*ring
)
1017 struct pipe_framebuffer_state
*pfb
= &batch
->framebuffer
;
1018 const struct fd_gmem_stateobj
*gmem
= batch
->gmem_state
;
1019 enum a3xx_msaa_samples samples
= fd_msaa_samples(pfb
->samples
);
1021 uint32_t buffers
= batch
->fast_cleared
;
1023 if (buffers
& PIPE_CLEAR_COLOR
) {
1025 for (int i
= 0; i
< pfb
->nr_cbufs
; i
++) {
1026 union pipe_color_union
*color
= &batch
->clear_color
[i
];
1027 union util_color uc
= {0};
1032 if (!(buffers
& (PIPE_CLEAR_COLOR0
<< i
)))
1035 enum pipe_format pfmt
= pfb
->cbufs
[i
]->format
;
1037 // XXX I think RB_CLEAR_COLOR_DWn wants to take into account SWAP??
1038 union pipe_color_union swapped
;
1039 switch (fd6_pipe2swap(pfmt
)) {
1041 swapped
.ui
[0] = color
->ui
[0];
1042 swapped
.ui
[1] = color
->ui
[1];
1043 swapped
.ui
[2] = color
->ui
[2];
1044 swapped
.ui
[3] = color
->ui
[3];
1047 swapped
.ui
[2] = color
->ui
[0];
1048 swapped
.ui
[1] = color
->ui
[1];
1049 swapped
.ui
[0] = color
->ui
[2];
1050 swapped
.ui
[3] = color
->ui
[3];
1053 swapped
.ui
[3] = color
->ui
[0];
1054 swapped
.ui
[0] = color
->ui
[1];
1055 swapped
.ui
[1] = color
->ui
[2];
1056 swapped
.ui
[2] = color
->ui
[3];
1059 swapped
.ui
[3] = color
->ui
[0];
1060 swapped
.ui
[2] = color
->ui
[1];
1061 swapped
.ui
[1] = color
->ui
[2];
1062 swapped
.ui
[0] = color
->ui
[3];
1066 util_pack_color_union(pfmt
, &uc
, &swapped
);
1068 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_DST_INFO
, 1);
1069 OUT_RING(ring
, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR
) |
1070 A6XX_RB_BLIT_DST_INFO_SAMPLES(samples
) |
1071 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(fd6_pipe2color(pfmt
)));
1073 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_INFO
, 1);
1074 OUT_RING(ring
, A6XX_RB_BLIT_INFO_GMEM
|
1075 A6XX_RB_BLIT_INFO_CLEAR_MASK(0xf));
1077 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_BASE_GMEM
, 1);
1078 OUT_RING(ring
, gmem
->cbuf_base
[i
]);
1080 OUT_PKT4(ring
, REG_A6XX_RB_UNKNOWN_88D0
, 1);
1083 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0
, 4);
1084 OUT_RING(ring
, uc
.ui
[0]);
1085 OUT_RING(ring
, uc
.ui
[1]);
1086 OUT_RING(ring
, uc
.ui
[2]);
1087 OUT_RING(ring
, uc
.ui
[3]);
1089 fd6_emit_blit(batch
, ring
);
1093 const bool has_depth
= pfb
->zsbuf
;
1094 const bool has_separate_stencil
=
1095 has_depth
&& fd_resource(pfb
->zsbuf
->texture
)->stencil
;
1097 /* First clear depth or combined depth/stencil. */
1098 if ((has_depth
&& (buffers
& PIPE_CLEAR_DEPTH
)) ||
1099 (!has_separate_stencil
&& (buffers
& PIPE_CLEAR_STENCIL
))) {
1100 enum pipe_format pfmt
= pfb
->zsbuf
->format
;
1101 uint32_t clear_value
;
1104 if (has_separate_stencil
) {
1105 pfmt
= util_format_get_depth_only(pfb
->zsbuf
->format
);
1106 clear_value
= util_pack_z(pfmt
, batch
->clear_depth
);
1108 pfmt
= pfb
->zsbuf
->format
;
1109 clear_value
= util_pack_z_stencil(pfmt
, batch
->clear_depth
,
1110 batch
->clear_stencil
);
1113 if (buffers
& PIPE_CLEAR_DEPTH
)
1116 if (!has_separate_stencil
&& (buffers
& PIPE_CLEAR_STENCIL
))
1119 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_DST_INFO
, 1);
1120 OUT_RING(ring
, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR
) |
1121 A6XX_RB_BLIT_DST_INFO_SAMPLES(samples
) |
1122 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(fd6_pipe2color(pfmt
)));
1124 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_INFO
, 1);
1125 OUT_RING(ring
, A6XX_RB_BLIT_INFO_GMEM
|
1126 // XXX UNK0 for separate stencil ??
1127 A6XX_RB_BLIT_INFO_DEPTH
|
1128 A6XX_RB_BLIT_INFO_CLEAR_MASK(mask
));
1130 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_BASE_GMEM
, 1);
1131 OUT_RING(ring
, gmem
->zsbuf_base
[0]);
1133 OUT_PKT4(ring
, REG_A6XX_RB_UNKNOWN_88D0
, 1);
1136 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0
, 1);
1137 OUT_RING(ring
, clear_value
);
1139 fd6_emit_blit(batch
, ring
);
1142 /* Then clear the separate stencil buffer in case of 32 bit depth
1143 * formats with separate stencil. */
1144 if (has_separate_stencil
&& (buffers
& PIPE_CLEAR_STENCIL
)) {
1145 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_DST_INFO
, 1);
1146 OUT_RING(ring
, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR
) |
1147 A6XX_RB_BLIT_DST_INFO_SAMPLES(samples
) |
1148 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(FMT6_8_UINT
));
1150 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_INFO
, 1);
1151 OUT_RING(ring
, A6XX_RB_BLIT_INFO_GMEM
|
1152 //A6XX_RB_BLIT_INFO_UNK0 |
1153 A6XX_RB_BLIT_INFO_DEPTH
|
1154 A6XX_RB_BLIT_INFO_CLEAR_MASK(0x1));
1156 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_BASE_GMEM
, 1);
1157 OUT_RING(ring
, gmem
->zsbuf_base
[1]);
1159 OUT_PKT4(ring
, REG_A6XX_RB_UNKNOWN_88D0
, 1);
1162 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0
, 1);
1163 OUT_RING(ring
, batch
->clear_stencil
& 0xff);
1165 fd6_emit_blit(batch
, ring
);
1170 * transfer from system memory to gmem
1173 emit_restore_blits(struct fd_batch
*batch
, struct fd_ringbuffer
*ring
)
1175 const struct fd_gmem_stateobj
*gmem
= batch
->gmem_state
;
1176 struct pipe_framebuffer_state
*pfb
= &batch
->framebuffer
;
1178 if (batch
->restore
& FD_BUFFER_COLOR
) {
1180 for (i
= 0; i
< pfb
->nr_cbufs
; i
++) {
1183 if (!(batch
->restore
& (PIPE_CLEAR_COLOR0
<< i
)))
1185 emit_restore_blit(batch
, ring
, gmem
->cbuf_base
[i
], pfb
->cbufs
[i
],
1190 if (batch
->restore
& (FD_BUFFER_DEPTH
| FD_BUFFER_STENCIL
)) {
1191 struct fd_resource
*rsc
= fd_resource(pfb
->zsbuf
->texture
);
1193 if (!rsc
->stencil
|| (batch
->restore
& FD_BUFFER_DEPTH
)) {
1194 emit_restore_blit(batch
, ring
, gmem
->zsbuf_base
[0], pfb
->zsbuf
,
1197 if (rsc
->stencil
&& (batch
->restore
& FD_BUFFER_STENCIL
)) {
1198 emit_restore_blit(batch
, ring
, gmem
->zsbuf_base
[1], pfb
->zsbuf
,
1205 prepare_tile_setup_ib(struct fd_batch
*batch
)
1207 batch
->tile_setup
= fd_submit_new_ringbuffer(batch
->submit
, 0x1000,
1208 FD_RINGBUFFER_STREAMING
);
1210 set_blit_scissor(batch
, batch
->tile_setup
);
1212 emit_restore_blits(batch
, batch
->tile_setup
);
1213 emit_clears(batch
, batch
->tile_setup
);
1217 * transfer from system memory to gmem
1220 fd6_emit_tile_mem2gmem(struct fd_batch
*batch
, const struct fd_tile
*tile
)
1224 /* before IB to rendering cmds: */
1226 fd6_emit_tile_renderprep(struct fd_batch
*batch
, const struct fd_tile
*tile
)
1228 fd_log(batch
, "TILE: START CLEAR/RESTORE");
1229 if (batch
->fast_cleared
|| !use_hw_binning(batch
)) {
1230 fd6_emit_ib(batch
->gmem
, batch
->tile_setup
);
1232 emit_conditional_ib(batch
, tile
, batch
->tile_setup
);
1234 fd_log(batch
, "TILE: END CLEAR/RESTORE");
1238 emit_resolve_blit(struct fd_batch
*batch
,
1239 struct fd_ringbuffer
*ring
,
1241 struct pipe_surface
*psurf
,
1245 bool stencil
= false;
1247 if (!fd_resource(psurf
->texture
)->valid
)
1251 case FD_BUFFER_COLOR
:
1253 case FD_BUFFER_STENCIL
:
1254 info
|= A6XX_RB_BLIT_INFO_UNK0
;
1257 case FD_BUFFER_DEPTH
:
1258 info
|= A6XX_RB_BLIT_INFO_DEPTH
;
1262 if (util_format_is_pure_integer(psurf
->format
))
1263 info
|= A6XX_RB_BLIT_INFO_INTEGER
;
1265 OUT_PKT4(ring
, REG_A6XX_RB_BLIT_INFO
, 1);
1266 OUT_RING(ring
, info
);
1268 emit_blit(batch
, ring
, base
, psurf
, stencil
);
1272 * transfer from gmem to system memory (ie. normal RAM)
1276 prepare_tile_fini_ib(struct fd_batch
*batch
)
1278 const struct fd_gmem_stateobj
*gmem
= batch
->gmem_state
;
1279 struct pipe_framebuffer_state
*pfb
= &batch
->framebuffer
;
1280 struct fd_ringbuffer
*ring
;
1282 batch
->tile_fini
= fd_submit_new_ringbuffer(batch
->submit
, 0x1000,
1283 FD_RINGBUFFER_STREAMING
);
1284 ring
= batch
->tile_fini
;
1286 set_blit_scissor(batch
, ring
);
1288 if (batch
->resolve
& (FD_BUFFER_DEPTH
| FD_BUFFER_STENCIL
)) {
1289 struct fd_resource
*rsc
= fd_resource(pfb
->zsbuf
->texture
);
1291 if (!rsc
->stencil
|| (batch
->resolve
& FD_BUFFER_DEPTH
)) {
1292 emit_resolve_blit(batch
, ring
,
1293 gmem
->zsbuf_base
[0], pfb
->zsbuf
,
1296 if (rsc
->stencil
&& (batch
->resolve
& FD_BUFFER_STENCIL
)) {
1297 emit_resolve_blit(batch
, ring
,
1298 gmem
->zsbuf_base
[1], pfb
->zsbuf
,
1303 if (batch
->resolve
& FD_BUFFER_COLOR
) {
1305 for (i
= 0; i
< pfb
->nr_cbufs
; i
++) {
1308 if (!(batch
->resolve
& (PIPE_CLEAR_COLOR0
<< i
)))
1310 emit_resolve_blit(batch
, ring
, gmem
->cbuf_base
[i
], pfb
->cbufs
[i
],
1317 fd6_emit_tile(struct fd_batch
*batch
, const struct fd_tile
*tile
)
1319 if (!use_hw_binning(batch
)) {
1320 fd6_emit_ib(batch
->gmem
, batch
->draw
);
1322 emit_conditional_ib(batch
, tile
, batch
->draw
);
1327 fd6_emit_tile_gmem2mem(struct fd_batch
*batch
, const struct fd_tile
*tile
)
1329 struct fd_ringbuffer
*ring
= batch
->gmem
;
1331 if (use_hw_binning(batch
)) {
1332 /* Conditionally execute if no VSC overflow: */
1334 BEGIN_RING(ring
, 7); /* ensure if/else doesn't get split */
1336 OUT_PKT7(ring
, CP_REG_TEST
, 1);
1337 OUT_RING(ring
, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG
) |
1338 A6XX_CP_REG_TEST_0_BIT(0) |
1339 A6XX_CP_REG_TEST_0_WAIT_FOR_ME
);
1341 OUT_PKT7(ring
, CP_COND_REG_EXEC
, 2);
1342 OUT_RING(ring
, CP_COND_REG_EXEC_0_MODE(PRED_TEST
));
1343 OUT_RING(ring
, CP_COND_REG_EXEC_1_DWORDS(2));
1345 /* if (no overflow) */ {
1346 OUT_PKT7(ring
, CP_SET_MARKER
, 1);
1347 OUT_RING(ring
, A6XX_CP_SET_MARKER_0_MODE(RM6_ENDVIS
));
1351 OUT_PKT7(ring
, CP_SET_DRAW_STATE
, 3);
1352 OUT_RING(ring
, CP_SET_DRAW_STATE__0_COUNT(0) |
1353 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
1354 CP_SET_DRAW_STATE__0_GROUP_ID(0));
1355 OUT_RING(ring
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1356 OUT_RING(ring
, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1358 OUT_PKT7(ring
, CP_SKIP_IB2_ENABLE_LOCAL
, 1);
1359 OUT_RING(ring
, 0x0);
1361 emit_marker6(ring
, 7);
1362 OUT_PKT7(ring
, CP_SET_MARKER
, 1);
1363 OUT_RING(ring
, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE
));
1364 emit_marker6(ring
, 7);
1366 fd_log(batch
, "TILE: START RESOLVE");
1367 if (batch
->fast_cleared
|| !use_hw_binning(batch
)) {
1368 fd6_emit_ib(batch
->gmem
, batch
->tile_fini
);
1370 emit_conditional_ib(batch
, tile
, batch
->tile_fini
);
1372 fd_log(batch
, "TILE: END RESOLVE");
1376 fd6_emit_tile_fini(struct fd_batch
*batch
)
1378 struct fd_ringbuffer
*ring
= batch
->gmem
;
1380 if (batch
->epilogue
)
1381 fd6_emit_ib(batch
->gmem
, batch
->epilogue
);
1383 OUT_PKT4(ring
, REG_A6XX_GRAS_LRZ_CNTL
, 1);
1384 OUT_RING(ring
, A6XX_GRAS_LRZ_CNTL_ENABLE
);
1386 fd6_emit_lrz_flush(ring
);
1388 fd6_event_write(batch
, ring
, PC_CCU_RESOLVE_TS
, true);
1390 if (use_hw_binning(batch
)) {
1391 check_vsc_overflow(batch
->ctx
);
1396 emit_sysmem_clears(struct fd_batch
*batch
, struct fd_ringbuffer
*ring
)
1398 struct fd_context
*ctx
= batch
->ctx
;
1399 struct pipe_framebuffer_state
*pfb
= &batch
->framebuffer
;
1401 uint32_t buffers
= batch
->fast_cleared
;
1403 if (buffers
& PIPE_CLEAR_COLOR
) {
1404 for (int i
= 0; i
< pfb
->nr_cbufs
; i
++) {
1405 union pipe_color_union
*color
= &batch
->clear_color
[i
];
1410 if (!(buffers
& (PIPE_CLEAR_COLOR0
<< i
)))
1413 fd6_clear_surface(ctx
, ring
,
1414 pfb
->cbufs
[i
], pfb
->width
, pfb
->height
, color
);
1417 if (buffers
& (PIPE_CLEAR_DEPTH
| PIPE_CLEAR_STENCIL
)) {
1418 union pipe_color_union value
= {};
1420 const bool has_depth
= pfb
->zsbuf
;
1421 struct pipe_resource
*separate_stencil
=
1422 has_depth
&& fd_resource(pfb
->zsbuf
->texture
)->stencil
?
1423 &fd_resource(pfb
->zsbuf
->texture
)->stencil
->base
: NULL
;
1425 if ((has_depth
&& (buffers
& PIPE_CLEAR_DEPTH
)) ||
1426 (!separate_stencil
&& (buffers
& PIPE_CLEAR_STENCIL
))) {
1427 value
.f
[0] = batch
->clear_depth
;
1428 value
.ui
[1] = batch
->clear_stencil
;
1429 fd6_clear_surface(ctx
, ring
,
1430 pfb
->zsbuf
, pfb
->width
, pfb
->height
, &value
);
1433 if (separate_stencil
&& (buffers
& PIPE_CLEAR_STENCIL
)) {
1434 value
.ui
[0] = batch
->clear_stencil
;
1436 struct pipe_surface stencil_surf
= *pfb
->zsbuf
;
1437 stencil_surf
.texture
= separate_stencil
;
1439 fd6_clear_surface(ctx
, ring
,
1440 &stencil_surf
, pfb
->width
, pfb
->height
, &value
);
1444 fd6_event_write(batch
, ring
, PC_CCU_FLUSH_COLOR_TS
, true);
1448 setup_tess_buffers(struct fd_batch
*batch
, struct fd_ringbuffer
*ring
)
1450 struct fd_context
*ctx
= batch
->ctx
;
1452 batch
->tessfactor_bo
= fd_bo_new(ctx
->screen
->dev
,
1453 batch
->tessfactor_size
,
1454 DRM_FREEDRENO_GEM_TYPE_KMEM
, "tessfactor");
1456 batch
->tessparam_bo
= fd_bo_new(ctx
->screen
->dev
,
1457 batch
->tessparam_size
,
1458 DRM_FREEDRENO_GEM_TYPE_KMEM
, "tessparam");
1460 OUT_PKT4(ring
, REG_A6XX_PC_TESSFACTOR_ADDR_LO
, 2);
1461 OUT_RELOC(ring
, batch
->tessfactor_bo
, 0, 0, 0);
1463 batch
->tess_addrs_constobj
->cur
= batch
->tess_addrs_constobj
->start
;
1464 OUT_RELOC(batch
->tess_addrs_constobj
, batch
->tessparam_bo
, 0, 0, 0);
1465 OUT_RELOC(batch
->tess_addrs_constobj
, batch
->tessfactor_bo
, 0, 0, 0);
1469 fd6_emit_sysmem_prep(struct fd_batch
*batch
)
1471 struct pipe_framebuffer_state
*pfb
= &batch
->framebuffer
;
1472 struct fd_ringbuffer
*ring
= batch
->gmem
;
1474 fd6_emit_restore(batch
, ring
);
1476 if (pfb
->width
> 0 && pfb
->height
> 0)
1477 set_scissor(ring
, 0, 0, pfb
->width
- 1, pfb
->height
- 1);
1479 set_scissor(ring
, 0, 0, 0, 0);
1481 set_window_offset(ring
, 0, 0);
1483 set_bin_size(ring
, 0, 0, 0xc00000); /* 0xc00000 = BYPASS? */
1485 emit_sysmem_clears(batch
, ring
);
1487 fd6_emit_lrz_flush(ring
);
1489 if (batch
->lrz_clear
)
1490 fd6_emit_ib(ring
, batch
->lrz_clear
);
1492 emit_marker6(ring
, 7);
1493 OUT_PKT7(ring
, CP_SET_MARKER
, 1);
1494 OUT_RING(ring
, A6XX_CP_SET_MARKER_0_MODE(RM6_BYPASS
));
1495 emit_marker6(ring
, 7);
1497 if (batch
->tessellation
)
1498 setup_tess_buffers(batch
, ring
);
1500 OUT_PKT7(ring
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1501 OUT_RING(ring
, 0x0);
1503 /* blob controls "local" in IB2, but I think that is not required */
1504 OUT_PKT7(ring
, CP_SKIP_IB2_ENABLE_LOCAL
, 1);
1505 OUT_RING(ring
, 0x1);
1507 fd6_event_write(batch
, ring
, PC_CCU_INVALIDATE_COLOR
, false);
1508 fd6_cache_inv(batch
, ring
);
1510 fd_wfi(batch
, ring
);
1511 OUT_PKT4(ring
, REG_A6XX_RB_CCU_CNTL
, 1);
1512 OUT_RING(ring
, fd6_context(batch
->ctx
)->magic
.RB_CCU_CNTL_bypass
);
1514 /* enable stream-out, with sysmem there is only one pass: */
1515 OUT_PKT4(ring
, REG_A6XX_VPC_SO_OVERRIDE
, 1);
1518 OUT_PKT7(ring
, CP_SET_VISIBILITY_OVERRIDE
, 1);
1519 OUT_RING(ring
, 0x1);
1521 emit_zs(ring
, pfb
->zsbuf
, NULL
);
1522 emit_mrt(ring
, pfb
, NULL
);
1523 emit_msaa(ring
, pfb
->samples
);
1525 update_render_cntl(batch
, pfb
, false);
1529 fd6_emit_sysmem_fini(struct fd_batch
*batch
)
1531 struct fd_ringbuffer
*ring
= batch
->gmem
;
1533 if (batch
->epilogue
)
1534 fd6_emit_ib(batch
->gmem
, batch
->epilogue
);
1536 OUT_PKT7(ring
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1537 OUT_RING(ring
, 0x0);
1539 fd6_emit_lrz_flush(ring
);
1541 fd6_event_write(batch
, ring
, PC_CCU_FLUSH_COLOR_TS
, true);
1545 fd6_gmem_init(struct pipe_context
*pctx
)
1547 struct fd_context
*ctx
= fd_context(pctx
);
1549 ctx
->emit_tile_init
= fd6_emit_tile_init
;
1550 ctx
->emit_tile_prep
= fd6_emit_tile_prep
;
1551 ctx
->emit_tile_mem2gmem
= fd6_emit_tile_mem2gmem
;
1552 ctx
->emit_tile_renderprep
= fd6_emit_tile_renderprep
;
1553 ctx
->emit_tile
= fd6_emit_tile
;
1554 ctx
->emit_tile_gmem2mem
= fd6_emit_tile_gmem2mem
;
1555 ctx
->emit_tile_fini
= fd6_emit_tile_fini
;
1556 ctx
->emit_sysmem_prep
= fd6_emit_sysmem_prep
;
1557 ctx
->emit_sysmem_fini
= fd6_emit_sysmem_fini
;