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freedreno: move UBWC color offset to fd_resource_offset()
[mesa.git] / src / gallium / drivers / freedreno / a6xx / fd6_gmem.c
1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 * Authors:
25 * Rob Clark <robclark@freedesktop.org>
26 */
27
28 #include <stdio.h>
29
30 #include "pipe/p_state.h"
31 #include "util/u_string.h"
32 #include "util/u_memory.h"
33 #include "util/u_inlines.h"
34 #include "util/u_format.h"
35
36 #include "freedreno_draw.h"
37 #include "freedreno_state.h"
38 #include "freedreno_resource.h"
39
40 #include "fd6_gmem.h"
41 #include "fd6_context.h"
42 #include "fd6_draw.h"
43 #include "fd6_emit.h"
44 #include "fd6_program.h"
45 #include "fd6_format.h"
46 #include "fd6_zsa.h"
47
48 /* some bits in common w/ a4xx: */
49 #include "a4xx/fd4_draw.h"
50
51 static void
52 emit_mrt(struct fd_ringbuffer *ring, struct pipe_framebuffer_state *pfb,
53 struct fd_gmem_stateobj *gmem)
54 {
55 unsigned char mrt_comp[A6XX_MAX_RENDER_TARGETS] = {0};
56 unsigned srgb_cntl = 0;
57 unsigned i;
58
59 for (i = 0; i < pfb->nr_cbufs; i++) {
60 enum a6xx_color_fmt format = 0;
61 enum a3xx_color_swap swap = WZYX;
62 bool sint = false, uint = false;
63 struct fd_resource *rsc = NULL;
64 struct fd_resource_slice *slice = NULL;
65 uint32_t stride = 0;
66 uint32_t offset, ubwc_offset;
67 uint32_t tile_mode;
68
69 if (!pfb->cbufs[i])
70 continue;
71
72 mrt_comp[i] = 0xf;
73
74 struct pipe_surface *psurf = pfb->cbufs[i];
75 enum pipe_format pformat = psurf->format;
76 rsc = fd_resource(psurf->texture);
77 if (!rsc->bo)
78 continue;
79
80 uint32_t base = gmem ? gmem->cbuf_base[i] : 0;
81 slice = fd_resource_slice(rsc, psurf->u.tex.level);
82 format = fd6_pipe2color(pformat);
83 sint = util_format_is_pure_sint(pformat);
84 uint = util_format_is_pure_uint(pformat);
85
86 if (util_format_is_srgb(pformat))
87 srgb_cntl |= (1 << i);
88
89 offset = fd_resource_offset(rsc, psurf->u.tex.level,
90 psurf->u.tex.first_layer);
91 ubwc_offset = fd_resource_ubwc_offset(rsc, psurf->u.tex.level,
92 psurf->u.tex.first_layer);
93
94 stride = slice->pitch * rsc->cpp * pfb->samples;
95 swap = rsc->tile_mode ? WZYX : fd6_pipe2swap(pformat);
96
97 if (rsc->tile_mode &&
98 fd_resource_level_linear(psurf->texture, psurf->u.tex.level))
99 tile_mode = TILE6_LINEAR;
100 else
101 tile_mode = rsc->tile_mode;
102
103 if (rsc->tile_mode &&
104 fd_resource_level_linear(psurf->texture, psurf->u.tex.level))
105 tile_mode = TILE6_LINEAR;
106 else
107 tile_mode = rsc->tile_mode;
108
109 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
110 debug_assert((offset + slice->size0) <= fd_bo_size(rsc->bo));
111
112 OUT_PKT4(ring, REG_A6XX_RB_MRT_BUF_INFO(i), 6);
113 OUT_RING(ring, A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format) |
114 A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(tile_mode) |
115 A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(swap));
116 OUT_RING(ring, A6XX_RB_MRT_PITCH(stride));
117 OUT_RING(ring, A6XX_RB_MRT_ARRAY_PITCH(slice->size0));
118 OUT_RELOCW(ring, rsc->bo, offset, 0, 0); /* BASE_LO/HI */
119 OUT_RING(ring, base); /* RB_MRT[i].BASE_GMEM */
120 OUT_PKT4(ring, REG_A6XX_SP_FS_MRT_REG(i), 1);
121 OUT_RING(ring, A6XX_SP_FS_MRT_REG_COLOR_FORMAT(format) |
122 COND(sint, A6XX_SP_FS_MRT_REG_COLOR_SINT) |
123 COND(uint, A6XX_SP_FS_MRT_REG_COLOR_UINT));
124
125 OUT_PKT4(ring, REG_A6XX_RB_MRT_FLAG_BUFFER(i), 3);
126 if (fd6_ubwc_enabled(rsc, tile_mode)) {
127 OUT_RELOCW(ring, rsc->bo, ubwc_offset, 0, 0); /* BASE_LO/HI */
128 OUT_RING(ring, A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(rsc->ubwc_pitch) |
129 A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(rsc->ubwc_size));
130 } else {
131 OUT_RING(ring, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_LO */
132 OUT_RING(ring, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_HI */
133 OUT_RING(ring, 0x00000000);
134 }
135 }
136
137 OUT_PKT4(ring, REG_A6XX_RB_SRGB_CNTL, 1);
138 OUT_RING(ring, srgb_cntl);
139
140 OUT_PKT4(ring, REG_A6XX_SP_SRGB_CNTL, 1);
141 OUT_RING(ring, srgb_cntl);
142
143 OUT_PKT4(ring, REG_A6XX_RB_RENDER_COMPONENTS, 1);
144 OUT_RING(ring, A6XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
145 A6XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
146 A6XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
147 A6XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
148 A6XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
149 A6XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
150 A6XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
151 A6XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
152
153 OUT_PKT4(ring, REG_A6XX_SP_FS_RENDER_COMPONENTS, 1);
154 OUT_RING(ring,
155 A6XX_SP_FS_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
156 A6XX_SP_FS_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
157 A6XX_SP_FS_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
158 A6XX_SP_FS_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
159 A6XX_SP_FS_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
160 A6XX_SP_FS_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
161 A6XX_SP_FS_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
162 A6XX_SP_FS_RENDER_COMPONENTS_RT7(mrt_comp[7]));
163 }
164
165 static void
166 emit_zs(struct fd_ringbuffer *ring, struct pipe_surface *zsbuf,
167 struct fd_gmem_stateobj *gmem)
168 {
169 if (zsbuf) {
170 struct fd_resource *rsc = fd_resource(zsbuf->texture);
171 enum a6xx_depth_format fmt = fd6_pipe2depth(zsbuf->format);
172 struct fd_resource_slice *slice = fd_resource_slice(rsc, 0);
173 uint32_t stride = slice->pitch * rsc->cpp;
174 uint32_t size = slice->size0;
175 uint32_t base = gmem ? gmem->zsbuf_base[0] : 0;
176 uint32_t offset = fd_resource_offset(rsc, zsbuf->u.tex.level,
177 zsbuf->u.tex.first_layer);
178 uint32_t ubwc_offset = fd_resource_ubwc_offset(rsc, zsbuf->u.tex.level,
179 zsbuf->u.tex.first_layer);
180
181 bool ubwc_enabled =
182 !fd_resource_level_linear(zsbuf->texture, zsbuf->u.tex.level) && rsc->ubwc_size;
183
184 OUT_PKT4(ring, REG_A6XX_RB_DEPTH_BUFFER_INFO, 6);
185 OUT_RING(ring, A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(fmt));
186 OUT_RING(ring, A6XX_RB_DEPTH_BUFFER_PITCH(stride));
187 OUT_RING(ring, A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(size));
188 OUT_RELOCW(ring, rsc->bo, offset, 0, 0); /* RB_DEPTH_BUFFER_BASE_LO/HI */
189 OUT_RING(ring, base); /* RB_DEPTH_BUFFER_BASE_GMEM */
190
191 OUT_PKT4(ring, REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO, 1);
192 OUT_RING(ring, A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(fmt));
193
194 OUT_PKT4(ring, REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO, 3);
195 if (ubwc_enabled) {
196 OUT_RELOCW(ring, rsc->bo, ubwc_offset, 0, 0); /* BASE_LO/HI */
197 OUT_RING(ring, A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(rsc->ubwc_pitch) |
198 A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(rsc->ubwc_size));
199 } else {
200 OUT_RING(ring, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_LO */
201 OUT_RING(ring, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_HI */
202 OUT_RING(ring, 0x00000000);
203 }
204
205 if (rsc->lrz) {
206 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO, 5);
207 OUT_RELOCW(ring, rsc->lrz, 0, 0, 0);
208 OUT_RING(ring, A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH(rsc->lrz_pitch));
209 //OUT_RELOCW(ring, rsc->lrz, 0, 0, 0); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO/HI */
210 // XXX a6xx seems to use a different buffer here.. not sure what for..
211 OUT_RING(ring, 0x00000000);
212 OUT_RING(ring, 0x00000000);
213 } else {
214 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO, 5);
215 OUT_RING(ring, 0x00000000);
216 OUT_RING(ring, 0x00000000);
217 OUT_RING(ring, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
218 OUT_RING(ring, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO */
219 OUT_RING(ring, 0x00000000);
220 }
221
222 if (rsc->stencil) {
223 struct fd_resource_slice *slice = fd_resource_slice(rsc->stencil, 0);
224 stride = slice->pitch * rsc->stencil->cpp;
225 size = slice->size0;
226 uint32_t base = gmem ? gmem->zsbuf_base[1] : 0;
227
228 OUT_PKT4(ring, REG_A6XX_RB_STENCIL_INFO, 6);
229 OUT_RING(ring, A6XX_RB_STENCIL_INFO_SEPARATE_STENCIL);
230 OUT_RING(ring, A6XX_RB_STENCIL_BUFFER_PITCH(stride));
231 OUT_RING(ring, A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(size));
232 OUT_RELOCW(ring, rsc->stencil->bo, 0, 0, 0); /* RB_STENCIL_BASE_LO/HI */
233 OUT_RING(ring, base); /* RB_STENCIL_BASE_LO */
234 } else {
235 OUT_PKT4(ring, REG_A6XX_RB_STENCIL_INFO, 1);
236 OUT_RING(ring, 0x00000000); /* RB_STENCIL_INFO */
237 }
238 } else {
239 OUT_PKT4(ring, REG_A6XX_RB_DEPTH_BUFFER_INFO, 6);
240 OUT_RING(ring, A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH6_NONE));
241 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_PITCH */
242 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_ARRAY_PITCH */
243 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_BASE_LO */
244 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_BASE_HI */
245 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_BASE_GMEM */
246
247 OUT_PKT4(ring, REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO, 1);
248 OUT_RING(ring, A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH6_NONE));
249
250 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO, 5);
251 OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
252 OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
253 OUT_RING(ring, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
254 OUT_RING(ring, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO */
255 OUT_RING(ring, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI */
256
257 OUT_PKT4(ring, REG_A6XX_RB_STENCIL_INFO, 1);
258 OUT_RING(ring, 0x00000000); /* RB_STENCIL_INFO */
259 }
260 }
261
262 static bool
263 use_hw_binning(struct fd_batch *batch)
264 {
265 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
266
267 // TODO figure out hw limits for binning
268
269 return fd_binning_enabled && ((gmem->nbins_x * gmem->nbins_y) > 2) &&
270 (batch->num_draws > 0);
271 }
272
273 static void
274 patch_fb_read(struct fd_batch *batch)
275 {
276 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
277
278 for (unsigned i = 0; i < fd_patch_num_elements(&batch->fb_read_patches); i++) {
279 struct fd_cs_patch *patch = fd_patch_element(&batch->fb_read_patches, i);
280 *patch->cs = patch->val | A6XX_TEX_CONST_2_PITCH(gmem->bin_w * gmem->cbuf_cpp[0]);
281 }
282 util_dynarray_resize(&batch->fb_read_patches, 0);
283 }
284
285 static void
286 patch_draws(struct fd_batch *batch, enum pc_di_vis_cull_mode vismode)
287 {
288 unsigned i;
289 for (i = 0; i < fd_patch_num_elements(&batch->draw_patches); i++) {
290 struct fd_cs_patch *patch = fd_patch_element(&batch->draw_patches, i);
291 *patch->cs = patch->val | DRAW4(0, 0, 0, vismode);
292 }
293 util_dynarray_resize(&batch->draw_patches, 0);
294 }
295
296 static void
297 update_render_cntl(struct fd_batch *batch, struct pipe_framebuffer_state *pfb, bool binning)
298 {
299 struct fd_ringbuffer *ring = batch->gmem;
300 uint32_t cntl = 0;
301 bool depth_ubwc_enable = false;
302 uint32_t mrts_ubwc_enable = 0;
303 int i;
304
305 if (pfb->zsbuf) {
306 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
307 depth_ubwc_enable =
308 !fd_resource_level_linear(pfb->zsbuf->texture, pfb->zsbuf->u.tex.level) && rsc->ubwc_size;
309 }
310
311 for (i = 0; i < pfb->nr_cbufs; i++) {
312 if (!pfb->cbufs[i])
313 continue;
314
315 struct pipe_surface *psurf = pfb->cbufs[i];
316 struct fd_resource *rsc = fd_resource(psurf->texture);
317 if (!rsc->bo)
318 continue;
319
320 if (fd6_ubwc_enabled(rsc, rsc->tile_mode))
321 mrts_ubwc_enable |= 1 << i;
322 }
323
324 cntl |= A6XX_RB_RENDER_CNTL_UNK4;
325 if (binning)
326 cntl |= A6XX_RB_RENDER_CNTL_BINNING;
327
328 OUT_PKT7(ring, CP_REG_WRITE, 3);
329 OUT_RING(ring, 0x2);
330 OUT_RING(ring, REG_A6XX_RB_RENDER_CNTL);
331 OUT_RING(ring, cntl |
332 COND(depth_ubwc_enable, A6XX_RB_RENDER_CNTL_FLAG_DEPTH) |
333 A6XX_RB_RENDER_CNTL_FLAG_MRTS(mrts_ubwc_enable));
334 }
335
336 static void
337 update_vsc_pipe(struct fd_batch *batch)
338 {
339 struct fd_context *ctx = batch->ctx;
340 struct fd6_context *fd6_ctx = fd6_context(ctx);
341 struct fd_gmem_stateobj *gmem = &ctx->gmem;
342 struct fd_ringbuffer *ring = batch->gmem;
343 int i;
344
345 OUT_PKT4(ring, REG_A6XX_VSC_BIN_SIZE, 3);
346 OUT_RING(ring, A6XX_VSC_BIN_SIZE_WIDTH(gmem->bin_w) |
347 A6XX_VSC_BIN_SIZE_HEIGHT(gmem->bin_h));
348 OUT_RELOCW(ring, fd6_ctx->vsc_data,
349 32 * A6XX_VSC_DATA_PITCH, 0, 0); /* VSC_SIZE_ADDRESS_LO/HI */
350
351 OUT_PKT4(ring, REG_A6XX_VSC_BIN_COUNT, 1);
352 OUT_RING(ring, A6XX_VSC_BIN_COUNT_NX(gmem->nbins_x) |
353 A6XX_VSC_BIN_COUNT_NY(gmem->nbins_y));
354
355 OUT_PKT4(ring, REG_A6XX_VSC_PIPE_CONFIG_REG(0), 32);
356 for (i = 0; i < 32; i++) {
357 struct fd_vsc_pipe *pipe = &ctx->vsc_pipe[i];
358 OUT_RING(ring, A6XX_VSC_PIPE_CONFIG_REG_X(pipe->x) |
359 A6XX_VSC_PIPE_CONFIG_REG_Y(pipe->y) |
360 A6XX_VSC_PIPE_CONFIG_REG_W(pipe->w) |
361 A6XX_VSC_PIPE_CONFIG_REG_H(pipe->h));
362 }
363
364 OUT_PKT4(ring, REG_A6XX_VSC_PIPE_DATA2_ADDRESS_LO, 4);
365 OUT_RELOCW(ring, fd6_ctx->vsc_data2, 0, 0, 0);
366 OUT_RING(ring, A6XX_VSC_DATA2_PITCH);
367 OUT_RING(ring, fd_bo_size(fd6_ctx->vsc_data2));
368
369 OUT_PKT4(ring, REG_A6XX_VSC_PIPE_DATA_ADDRESS_LO, 4);
370 OUT_RELOCW(ring, fd6_ctx->vsc_data, 0, 0, 0);
371 OUT_RING(ring, A6XX_VSC_DATA_PITCH);
372 OUT_RING(ring, fd_bo_size(fd6_ctx->vsc_data));
373 }
374
375 static void
376 set_scissor(struct fd_ringbuffer *ring, uint32_t x1, uint32_t y1, uint32_t x2, uint32_t y2)
377 {
378 OUT_PKT4(ring, REG_A6XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
379 OUT_RING(ring, A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X(x1) |
380 A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(y1));
381 OUT_RING(ring, A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X(x2) |
382 A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(y2));
383
384 OUT_PKT4(ring, REG_A6XX_GRAS_RESOLVE_CNTL_1, 2);
385 OUT_RING(ring, A6XX_GRAS_RESOLVE_CNTL_1_X(x1) |
386 A6XX_GRAS_RESOLVE_CNTL_1_Y(y1));
387 OUT_RING(ring, A6XX_GRAS_RESOLVE_CNTL_2_X(x2) |
388 A6XX_GRAS_RESOLVE_CNTL_2_Y(y2));
389 }
390
391 static void
392 set_bin_size(struct fd_ringbuffer *ring, uint32_t w, uint32_t h, uint32_t flag)
393 {
394 OUT_PKT4(ring, REG_A6XX_GRAS_BIN_CONTROL, 1);
395 OUT_RING(ring, A6XX_GRAS_BIN_CONTROL_BINW(w) |
396 A6XX_GRAS_BIN_CONTROL_BINH(h) | flag);
397
398 OUT_PKT4(ring, REG_A6XX_RB_BIN_CONTROL, 1);
399 OUT_RING(ring, A6XX_RB_BIN_CONTROL_BINW(w) |
400 A6XX_RB_BIN_CONTROL_BINH(h) | flag);
401
402 /* no flag for RB_BIN_CONTROL2... */
403 OUT_PKT4(ring, REG_A6XX_RB_BIN_CONTROL2, 1);
404 OUT_RING(ring, A6XX_RB_BIN_CONTROL2_BINW(w) |
405 A6XX_RB_BIN_CONTROL2_BINH(h));
406 }
407
408 static void
409 emit_binning_pass(struct fd_batch *batch)
410 {
411 struct fd_context *ctx = batch->ctx;
412 struct fd_ringbuffer *ring = batch->gmem;
413 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
414
415 uint32_t x1 = gmem->minx;
416 uint32_t y1 = gmem->miny;
417 uint32_t x2 = gmem->minx + gmem->width - 1;
418 uint32_t y2 = gmem->miny + gmem->height - 1;
419
420 set_scissor(ring, x1, y1, x2, y2);
421
422 emit_marker6(ring, 7);
423 OUT_PKT7(ring, CP_SET_MARKER, 1);
424 OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(RM6_BINNING));
425 emit_marker6(ring, 7);
426
427 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
428 OUT_RING(ring, 0x1);
429
430 OUT_PKT7(ring, CP_SET_MODE, 1);
431 OUT_RING(ring, 0x1);
432
433 OUT_WFI5(ring);
434
435 OUT_PKT4(ring, REG_A6XX_VFD_MODE_CNTL, 1);
436 OUT_RING(ring, A6XX_VFD_MODE_CNTL_BINNING_PASS);
437
438 update_vsc_pipe(batch);
439
440 OUT_PKT4(ring, REG_A6XX_PC_UNKNOWN_9805, 1);
441 OUT_RING(ring, 0x1);
442
443 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A0F8, 1);
444 OUT_RING(ring, 0x1);
445
446 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
447 OUT_RING(ring, UNK_2C);
448
449 OUT_PKT4(ring, REG_A6XX_RB_WINDOW_OFFSET, 1);
450 OUT_RING(ring, A6XX_RB_WINDOW_OFFSET_X(0) |
451 A6XX_RB_WINDOW_OFFSET_Y(0));
452
453 OUT_PKT4(ring, REG_A6XX_SP_TP_WINDOW_OFFSET, 1);
454 OUT_RING(ring, A6XX_SP_TP_WINDOW_OFFSET_X(0) |
455 A6XX_SP_TP_WINDOW_OFFSET_Y(0));
456
457 /* emit IB to binning drawcmds: */
458 fd6_emit_ib(ring, batch->draw);
459
460 fd_reset_wfi(batch);
461
462 OUT_PKT7(ring, CP_SET_DRAW_STATE, 3);
463 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
464 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
465 CP_SET_DRAW_STATE__0_GROUP_ID(0));
466 OUT_RING(ring, CP_SET_DRAW_STATE__1_ADDR_LO(0));
467 OUT_RING(ring, CP_SET_DRAW_STATE__2_ADDR_HI(0));
468
469 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
470 OUT_RING(ring, UNK_2D);
471
472 OUT_PKT7(ring, CP_EVENT_WRITE, 4);
473 OUT_RING(ring, CACHE_FLUSH_TS);
474 OUT_RELOCW(ring, fd6_context(ctx)->blit_mem, 0, 0, 0); /* ADDR_LO/HI */
475 OUT_RING(ring, 0x00000000);
476
477 fd_wfi(batch, ring);
478 }
479
480 static void
481 emit_msaa(struct fd_ringbuffer *ring, unsigned nr)
482 {
483 enum a3xx_msaa_samples samples = fd_msaa_samples(nr);
484
485 OUT_PKT4(ring, REG_A6XX_SP_TP_RAS_MSAA_CNTL, 2);
486 OUT_RING(ring, A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(samples));
487 OUT_RING(ring, A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(samples) |
488 COND(samples == MSAA_ONE, A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE));
489
490 OUT_PKT4(ring, REG_A6XX_GRAS_RAS_MSAA_CNTL, 2);
491 OUT_RING(ring, A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(samples));
492 OUT_RING(ring, A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(samples) |
493 COND(samples == MSAA_ONE, A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE));
494
495 OUT_PKT4(ring, REG_A6XX_RB_RAS_MSAA_CNTL, 2);
496 OUT_RING(ring, A6XX_RB_RAS_MSAA_CNTL_SAMPLES(samples));
497 OUT_RING(ring, A6XX_RB_DEST_MSAA_CNTL_SAMPLES(samples) |
498 COND(samples == MSAA_ONE, A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE));
499
500 OUT_PKT4(ring, REG_A6XX_RB_MSAA_CNTL, 1);
501 OUT_RING(ring, A6XX_RB_MSAA_CNTL_SAMPLES(samples));
502 }
503
504 static void prepare_tile_setup_ib(struct fd_batch *batch);
505 static void prepare_tile_fini_ib(struct fd_batch *batch);
506
507 /* before first tile */
508 static void
509 fd6_emit_tile_init(struct fd_batch *batch)
510 {
511 struct fd_context *ctx = batch->ctx;
512 struct fd_ringbuffer *ring = batch->gmem;
513 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
514 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
515
516 fd6_emit_restore(batch, ring);
517
518 fd6_emit_lrz_flush(ring);
519
520 if (batch->lrz_clear)
521 fd6_emit_ib(ring, batch->lrz_clear);
522
523 fd6_cache_inv(batch, ring);
524
525 prepare_tile_setup_ib(batch);
526 prepare_tile_fini_ib(batch);
527
528 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
529 OUT_RING(ring, 0x0);
530
531 /* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */
532 fd_wfi(batch, ring);
533 OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
534 OUT_RING(ring, 0x7c400004); /* RB_CCU_CNTL */
535
536 emit_zs(ring, pfb->zsbuf, &ctx->gmem);
537 emit_mrt(ring, pfb, &ctx->gmem);
538 emit_msaa(ring, pfb->samples);
539 patch_fb_read(batch);
540
541 if (use_hw_binning(batch)) {
542 set_bin_size(ring, gmem->bin_w, gmem->bin_h,
543 A6XX_RB_BIN_CONTROL_BINNING_PASS | 0x6000000);
544 update_render_cntl(batch, pfb, true);
545 emit_binning_pass(batch);
546 patch_draws(batch, USE_VISIBILITY);
547
548 set_bin_size(ring, gmem->bin_w, gmem->bin_h,
549 A6XX_RB_BIN_CONTROL_USE_VIZ | 0x6000000);
550
551 OUT_PKT4(ring, REG_A6XX_VFD_MODE_CNTL, 1);
552 OUT_RING(ring, 0x0);
553 } else {
554 set_bin_size(ring, gmem->bin_w, gmem->bin_h, 0x6000000);
555 patch_draws(batch, IGNORE_VISIBILITY);
556 }
557
558 update_render_cntl(batch, pfb, false);
559 }
560
561 static void
562 set_window_offset(struct fd_ringbuffer *ring, uint32_t x1, uint32_t y1)
563 {
564 OUT_PKT4(ring, REG_A6XX_RB_WINDOW_OFFSET, 1);
565 OUT_RING(ring, A6XX_RB_WINDOW_OFFSET_X(x1) |
566 A6XX_RB_WINDOW_OFFSET_Y(y1));
567
568 OUT_PKT4(ring, REG_A6XX_RB_WINDOW_OFFSET2, 1);
569 OUT_RING(ring, A6XX_RB_WINDOW_OFFSET2_X(x1) |
570 A6XX_RB_WINDOW_OFFSET2_Y(y1));
571
572 OUT_PKT4(ring, REG_A6XX_SP_WINDOW_OFFSET, 1);
573 OUT_RING(ring, A6XX_SP_WINDOW_OFFSET_X(x1) |
574 A6XX_SP_WINDOW_OFFSET_Y(y1));
575
576 OUT_PKT4(ring, REG_A6XX_SP_TP_WINDOW_OFFSET, 1);
577 OUT_RING(ring, A6XX_SP_TP_WINDOW_OFFSET_X(x1) |
578 A6XX_SP_TP_WINDOW_OFFSET_Y(y1));
579 }
580
581 /* before mem2gmem */
582 static void
583 fd6_emit_tile_prep(struct fd_batch *batch, struct fd_tile *tile)
584 {
585 struct fd_context *ctx = batch->ctx;
586 struct fd6_context *fd6_ctx = fd6_context(ctx);
587 struct fd_ringbuffer *ring = batch->gmem;
588
589 OUT_PKT7(ring, CP_SET_MARKER, 1);
590 OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(0x7));
591
592 emit_marker6(ring, 7);
593 OUT_PKT7(ring, CP_SET_MARKER, 1);
594 OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(RM6_GMEM) | 0x10);
595 emit_marker6(ring, 7);
596
597 uint32_t x1 = tile->xoff;
598 uint32_t y1 = tile->yoff;
599 uint32_t x2 = tile->xoff + tile->bin_w - 1;
600 uint32_t y2 = tile->yoff + tile->bin_h - 1;
601
602 set_scissor(ring, x1, y1, x2, y2);
603
604 set_window_offset(ring, x1, y1);
605
606 OUT_PKT4(ring, REG_A6XX_VPC_SO_OVERRIDE, 1);
607 OUT_RING(ring, A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
608
609 if (use_hw_binning(batch)) {
610 struct fd_vsc_pipe *pipe = &ctx->vsc_pipe[tile->p];
611
612 OUT_PKT7(ring, CP_WAIT_FOR_ME, 0);
613
614 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
615 OUT_RING(ring, 0x0);
616
617 OUT_PKT7(ring, CP_SET_MODE, 1);
618 OUT_RING(ring, 0x0);
619
620 OUT_PKT7(ring, CP_SET_BIN_DATA5, 7);
621 OUT_RING(ring, CP_SET_BIN_DATA5_0_VSC_SIZE(pipe->w * pipe->h) |
622 CP_SET_BIN_DATA5_0_VSC_N(tile->n));
623 OUT_RELOC(ring, fd6_ctx->vsc_data, /* VSC_PIPE[p].DATA_ADDRESS */
624 (tile->p * A6XX_VSC_DATA_PITCH), 0, 0);
625 OUT_RELOC(ring, fd6_ctx->vsc_data, /* VSC_SIZE_ADDRESS + (p * 4) */
626 (tile->p * 4) + (32 * A6XX_VSC_DATA_PITCH), 0, 0);
627 OUT_RELOC(ring, fd6_ctx->vsc_data2,
628 (tile->p * A6XX_VSC_DATA2_PITCH), 0, 0);
629 } else {
630 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
631 OUT_RING(ring, 0x1);
632
633 OUT_PKT7(ring, CP_SET_MODE, 1);
634 OUT_RING(ring, 0x0);
635 }
636 }
637
638 static void
639 set_blit_scissor(struct fd_batch *batch, struct fd_ringbuffer *ring)
640 {
641 struct pipe_scissor_state blit_scissor;
642 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
643
644 blit_scissor.minx = batch->max_scissor.minx;
645 blit_scissor.miny = batch->max_scissor.miny;
646 blit_scissor.maxx = MIN2(pfb->width, batch->max_scissor.maxx);
647 blit_scissor.maxy = MIN2(pfb->height, batch->max_scissor.maxy);
648
649 OUT_PKT4(ring, REG_A6XX_RB_BLIT_SCISSOR_TL, 2);
650 OUT_RING(ring,
651 A6XX_RB_BLIT_SCISSOR_TL_X(blit_scissor.minx) |
652 A6XX_RB_BLIT_SCISSOR_TL_Y(blit_scissor.miny));
653 OUT_RING(ring,
654 A6XX_RB_BLIT_SCISSOR_BR_X(blit_scissor.maxx - 1) |
655 A6XX_RB_BLIT_SCISSOR_BR_Y(blit_scissor.maxy - 1));
656 }
657
658 static void
659 emit_blit(struct fd_batch *batch,
660 struct fd_ringbuffer *ring,
661 uint32_t base,
662 struct pipe_surface *psurf,
663 bool stencil)
664 {
665 struct fd_resource_slice *slice;
666 struct fd_resource *rsc = fd_resource(psurf->texture);
667 enum pipe_format pfmt = psurf->format;
668 uint32_t offset, ubwc_offset;
669
670 /* separate stencil case: */
671 if (stencil) {
672 rsc = rsc->stencil;
673 pfmt = rsc->base.format;
674 }
675
676 slice = fd_resource_slice(rsc, psurf->u.tex.level);
677 offset = fd_resource_offset(rsc, psurf->u.tex.level,
678 psurf->u.tex.first_layer);
679 ubwc_offset = fd_resource_ubwc_offset(rsc, psurf->u.tex.level,
680 psurf->u.tex.first_layer);
681
682 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
683
684 enum a6xx_color_fmt format = fd6_pipe2color(pfmt);
685 uint32_t stride = slice->pitch * rsc->cpp;
686 uint32_t size = slice->size0;
687 enum a3xx_color_swap swap = rsc->tile_mode ? WZYX : fd6_pipe2swap(pfmt);
688 enum a3xx_msaa_samples samples =
689 fd_msaa_samples(rsc->base.nr_samples);
690 uint32_t tile_mode;
691
692 if (rsc->tile_mode &&
693 fd_resource_level_linear(&rsc->base, psurf->u.tex.level))
694 tile_mode = TILE6_LINEAR;
695 else
696 tile_mode = rsc->tile_mode;
697
698 OUT_PKT4(ring, REG_A6XX_RB_BLIT_DST_INFO, 5);
699 OUT_RING(ring,
700 A6XX_RB_BLIT_DST_INFO_TILE_MODE(tile_mode) |
701 A6XX_RB_BLIT_DST_INFO_SAMPLES(samples) |
702 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(format) |
703 A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(swap) |
704 COND(fd6_ubwc_enabled(rsc, tile_mode), A6XX_RB_BLIT_DST_INFO_FLAGS));
705 OUT_RELOCW(ring, rsc->bo, offset, 0, 0); /* RB_BLIT_DST_LO/HI */
706 OUT_RING(ring, A6XX_RB_BLIT_DST_PITCH(stride));
707 OUT_RING(ring, A6XX_RB_BLIT_DST_ARRAY_PITCH(size));
708
709 OUT_PKT4(ring, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
710 OUT_RING(ring, base);
711
712 if (fd6_ubwc_enabled(rsc, tile_mode)) {
713 OUT_PKT4(ring, REG_A6XX_RB_BLIT_FLAG_DST_LO, 3);
714 OUT_RELOCW(ring, rsc->bo, ubwc_offset, 0, 0);
715 OUT_RING(ring, A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(rsc->ubwc_pitch) |
716 A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(rsc->ubwc_size));
717 }
718
719 fd6_emit_blit(batch, ring);
720 }
721
722 static void
723 emit_restore_blit(struct fd_batch *batch,
724 struct fd_ringbuffer *ring,
725 uint32_t base,
726 struct pipe_surface *psurf,
727 unsigned buffer)
728 {
729 uint32_t info = 0;
730 bool stencil = false;
731
732 switch (buffer) {
733 case FD_BUFFER_COLOR:
734 info |= A6XX_RB_BLIT_INFO_UNK0;
735 break;
736 case FD_BUFFER_STENCIL:
737 info |= A6XX_RB_BLIT_INFO_UNK0;
738 stencil = true;
739 break;
740 case FD_BUFFER_DEPTH:
741 info |= A6XX_RB_BLIT_INFO_DEPTH | A6XX_RB_BLIT_INFO_UNK0;
742 break;
743 }
744
745 if (util_format_is_pure_integer(psurf->format))
746 info |= A6XX_RB_BLIT_INFO_INTEGER;
747
748 OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
749 OUT_RING(ring, info | A6XX_RB_BLIT_INFO_GMEM);
750
751 emit_blit(batch, ring, base, psurf, stencil);
752 }
753
754 static void
755 emit_clears(struct fd_batch *batch, struct fd_ringbuffer *ring)
756 {
757 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
758 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
759 enum a3xx_msaa_samples samples = fd_msaa_samples(pfb->samples);
760
761 uint32_t buffers = batch->fast_cleared;
762
763 if (buffers & PIPE_CLEAR_COLOR) {
764
765 for (int i = 0; i < pfb->nr_cbufs; i++) {
766 union pipe_color_union *color = &batch->clear_color[i];
767 union util_color uc = {0};
768
769 if (!pfb->cbufs[i])
770 continue;
771
772 if (!(buffers & (PIPE_CLEAR_COLOR0 << i)))
773 continue;
774
775 enum pipe_format pfmt = pfb->cbufs[i]->format;
776
777 // XXX I think RB_CLEAR_COLOR_DWn wants to take into account SWAP??
778 union pipe_color_union swapped;
779 switch (fd6_pipe2swap(pfmt)) {
780 case WZYX:
781 swapped.ui[0] = color->ui[0];
782 swapped.ui[1] = color->ui[1];
783 swapped.ui[2] = color->ui[2];
784 swapped.ui[3] = color->ui[3];
785 break;
786 case WXYZ:
787 swapped.ui[2] = color->ui[0];
788 swapped.ui[1] = color->ui[1];
789 swapped.ui[0] = color->ui[2];
790 swapped.ui[3] = color->ui[3];
791 break;
792 case ZYXW:
793 swapped.ui[3] = color->ui[0];
794 swapped.ui[0] = color->ui[1];
795 swapped.ui[1] = color->ui[2];
796 swapped.ui[2] = color->ui[3];
797 break;
798 case XYZW:
799 swapped.ui[3] = color->ui[0];
800 swapped.ui[2] = color->ui[1];
801 swapped.ui[1] = color->ui[2];
802 swapped.ui[0] = color->ui[3];
803 break;
804 }
805
806 if (util_format_is_pure_uint(pfmt)) {
807 util_format_write_4ui(pfmt, swapped.ui, 0, &uc, 0, 0, 0, 1, 1);
808 } else if (util_format_is_pure_sint(pfmt)) {
809 util_format_write_4i(pfmt, swapped.i, 0, &uc, 0, 0, 0, 1, 1);
810 } else {
811 util_pack_color(swapped.f, pfmt, &uc);
812 }
813
814 OUT_PKT4(ring, REG_A6XX_RB_BLIT_DST_INFO, 1);
815 OUT_RING(ring, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR) |
816 A6XX_RB_BLIT_DST_INFO_SAMPLES(samples) |
817 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(fd6_pipe2color(pfmt)));
818
819 OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
820 OUT_RING(ring, A6XX_RB_BLIT_INFO_GMEM |
821 A6XX_RB_BLIT_INFO_CLEAR_MASK(0xf));
822
823 OUT_PKT4(ring, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
824 OUT_RING(ring, gmem->cbuf_base[i]);
825
826 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_88D0, 1);
827 OUT_RING(ring, 0);
828
829 OUT_PKT4(ring, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 4);
830 OUT_RING(ring, uc.ui[0]);
831 OUT_RING(ring, uc.ui[1]);
832 OUT_RING(ring, uc.ui[2]);
833 OUT_RING(ring, uc.ui[3]);
834
835 fd6_emit_blit(batch, ring);
836 }
837 }
838
839 const bool has_depth = pfb->zsbuf;
840 const bool has_separate_stencil =
841 has_depth && fd_resource(pfb->zsbuf->texture)->stencil;
842
843 /* First clear depth or combined depth/stencil. */
844 if ((has_depth && (buffers & PIPE_CLEAR_DEPTH)) ||
845 (!has_separate_stencil && (buffers & PIPE_CLEAR_STENCIL))) {
846 enum pipe_format pfmt = pfb->zsbuf->format;
847 uint32_t clear_value;
848 uint32_t mask = 0;
849
850 if (has_separate_stencil) {
851 pfmt = util_format_get_depth_only(pfb->zsbuf->format);
852 clear_value = util_pack_z(pfmt, batch->clear_depth);
853 } else {
854 pfmt = pfb->zsbuf->format;
855 clear_value = util_pack_z_stencil(pfmt, batch->clear_depth,
856 batch->clear_stencil);
857 }
858
859 if (buffers & PIPE_CLEAR_DEPTH)
860 mask |= 0x1;
861
862 if (!has_separate_stencil && (buffers & PIPE_CLEAR_STENCIL))
863 mask |= 0x2;
864
865 OUT_PKT4(ring, REG_A6XX_RB_BLIT_DST_INFO, 1);
866 OUT_RING(ring, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR) |
867 A6XX_RB_BLIT_DST_INFO_SAMPLES(samples) |
868 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(fd6_pipe2color(pfmt)));
869
870 OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
871 OUT_RING(ring, A6XX_RB_BLIT_INFO_GMEM |
872 // XXX UNK0 for separate stencil ??
873 A6XX_RB_BLIT_INFO_DEPTH |
874 A6XX_RB_BLIT_INFO_CLEAR_MASK(mask));
875
876 OUT_PKT4(ring, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
877 OUT_RING(ring, gmem->zsbuf_base[0]);
878
879 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_88D0, 1);
880 OUT_RING(ring, 0);
881
882 OUT_PKT4(ring, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 1);
883 OUT_RING(ring, clear_value);
884
885 fd6_emit_blit(batch, ring);
886 }
887
888 /* Then clear the separate stencil buffer in case of 32 bit depth
889 * formats with separate stencil. */
890 if (has_separate_stencil && (buffers & PIPE_CLEAR_STENCIL)) {
891 OUT_PKT4(ring, REG_A6XX_RB_BLIT_DST_INFO, 1);
892 OUT_RING(ring, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR) |
893 A6XX_RB_BLIT_DST_INFO_SAMPLES(samples) |
894 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(RB6_R8_UINT));
895
896 OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
897 OUT_RING(ring, A6XX_RB_BLIT_INFO_GMEM |
898 //A6XX_RB_BLIT_INFO_UNK0 |
899 A6XX_RB_BLIT_INFO_DEPTH |
900 A6XX_RB_BLIT_INFO_CLEAR_MASK(0x1));
901
902 OUT_PKT4(ring, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
903 OUT_RING(ring, gmem->zsbuf_base[1]);
904
905 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_88D0, 1);
906 OUT_RING(ring, 0);
907
908 OUT_PKT4(ring, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 1);
909 OUT_RING(ring, batch->clear_stencil & 0xff);
910
911 fd6_emit_blit(batch, ring);
912 }
913 }
914
915 /*
916 * transfer from system memory to gmem
917 */
918 static void
919 emit_restore_blits(struct fd_batch *batch, struct fd_ringbuffer *ring)
920 {
921 struct fd_context *ctx = batch->ctx;
922 struct fd_gmem_stateobj *gmem = &ctx->gmem;
923 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
924
925 if (batch->restore & FD_BUFFER_COLOR) {
926 unsigned i;
927 for (i = 0; i < pfb->nr_cbufs; i++) {
928 if (!pfb->cbufs[i])
929 continue;
930 if (!(batch->restore & (PIPE_CLEAR_COLOR0 << i)))
931 continue;
932 emit_restore_blit(batch, ring, gmem->cbuf_base[i], pfb->cbufs[i],
933 FD_BUFFER_COLOR);
934 }
935 }
936
937 if (batch->restore & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
938 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
939
940 if (!rsc->stencil || (batch->restore & FD_BUFFER_DEPTH)) {
941 emit_restore_blit(batch, ring, gmem->zsbuf_base[0], pfb->zsbuf,
942 FD_BUFFER_DEPTH);
943 }
944 if (rsc->stencil && (batch->restore & FD_BUFFER_STENCIL)) {
945 emit_restore_blit(batch, ring, gmem->zsbuf_base[1], pfb->zsbuf,
946 FD_BUFFER_STENCIL);
947 }
948 }
949 }
950
951 static void
952 prepare_tile_setup_ib(struct fd_batch *batch)
953 {
954 batch->tile_setup = fd_submit_new_ringbuffer(batch->submit, 0x1000,
955 FD_RINGBUFFER_STREAMING);
956
957 set_blit_scissor(batch, batch->tile_setup);
958
959 emit_restore_blits(batch, batch->tile_setup);
960 emit_clears(batch, batch->tile_setup);
961 }
962
963 /*
964 * transfer from system memory to gmem
965 */
966 static void
967 fd6_emit_tile_mem2gmem(struct fd_batch *batch, struct fd_tile *tile)
968 {
969 }
970
971 /* before IB to rendering cmds: */
972 static void
973 fd6_emit_tile_renderprep(struct fd_batch *batch, struct fd_tile *tile)
974 {
975 fd6_emit_ib(batch->gmem, batch->tile_setup);
976 }
977
978 static void
979 emit_resolve_blit(struct fd_batch *batch,
980 struct fd_ringbuffer *ring,
981 uint32_t base,
982 struct pipe_surface *psurf,
983 unsigned buffer)
984 {
985 uint32_t info = 0;
986 bool stencil = false;
987
988 if (!fd_resource(psurf->texture)->valid)
989 return;
990
991 switch (buffer) {
992 case FD_BUFFER_COLOR:
993 break;
994 case FD_BUFFER_STENCIL:
995 info |= A6XX_RB_BLIT_INFO_UNK0;
996 stencil = true;
997 break;
998 case FD_BUFFER_DEPTH:
999 info |= A6XX_RB_BLIT_INFO_DEPTH;
1000 break;
1001 }
1002
1003 if (util_format_is_pure_integer(psurf->format))
1004 info |= A6XX_RB_BLIT_INFO_INTEGER;
1005
1006 OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
1007 OUT_RING(ring, info);
1008
1009 emit_blit(batch, ring, base, psurf, stencil);
1010 }
1011
1012 /*
1013 * transfer from gmem to system memory (ie. normal RAM)
1014 */
1015
1016 static void
1017 prepare_tile_fini_ib(struct fd_batch *batch)
1018 {
1019 struct fd_context *ctx = batch->ctx;
1020 struct fd_gmem_stateobj *gmem = &ctx->gmem;
1021 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
1022 struct fd_ringbuffer *ring;
1023
1024 batch->tile_fini = fd_submit_new_ringbuffer(batch->submit, 0x1000,
1025 FD_RINGBUFFER_STREAMING);
1026 ring = batch->tile_fini;
1027
1028 if (use_hw_binning(batch)) {
1029 OUT_PKT7(ring, CP_SET_MARKER, 1);
1030 OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(0x5) | 0x10);
1031 }
1032
1033 OUT_PKT7(ring, CP_SET_DRAW_STATE, 3);
1034 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
1035 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
1036 CP_SET_DRAW_STATE__0_GROUP_ID(0));
1037 OUT_RING(ring, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1038 OUT_RING(ring, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1039
1040 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1041 OUT_RING(ring, 0x0);
1042
1043 emit_marker6(ring, 7);
1044 OUT_PKT7(ring, CP_SET_MARKER, 1);
1045 OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE) | 0x10);
1046 emit_marker6(ring, 7);
1047
1048 set_blit_scissor(batch, ring);
1049
1050 if (batch->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
1051 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
1052
1053 if (!rsc->stencil || (batch->resolve & FD_BUFFER_DEPTH)) {
1054 emit_resolve_blit(batch, ring,
1055 gmem->zsbuf_base[0], pfb->zsbuf,
1056 FD_BUFFER_DEPTH);
1057 }
1058 if (rsc->stencil && (batch->resolve & FD_BUFFER_STENCIL)) {
1059 emit_resolve_blit(batch, ring,
1060 gmem->zsbuf_base[1], pfb->zsbuf,
1061 FD_BUFFER_STENCIL);
1062 }
1063 }
1064
1065 if (batch->resolve & FD_BUFFER_COLOR) {
1066 unsigned i;
1067 for (i = 0; i < pfb->nr_cbufs; i++) {
1068 if (!pfb->cbufs[i])
1069 continue;
1070 if (!(batch->resolve & (PIPE_CLEAR_COLOR0 << i)))
1071 continue;
1072 emit_resolve_blit(batch, ring, gmem->cbuf_base[i], pfb->cbufs[i],
1073 FD_BUFFER_COLOR);
1074 }
1075 }
1076 }
1077
1078 static void
1079 fd6_emit_tile_gmem2mem(struct fd_batch *batch, struct fd_tile *tile)
1080 {
1081 fd6_emit_ib(batch->gmem, batch->tile_fini);
1082 }
1083
1084 static void
1085 fd6_emit_tile_fini(struct fd_batch *batch)
1086 {
1087 struct fd_ringbuffer *ring = batch->gmem;
1088
1089 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_CNTL, 1);
1090 OUT_RING(ring, A6XX_GRAS_LRZ_CNTL_ENABLE | A6XX_GRAS_LRZ_CNTL_UNK3);
1091
1092 fd6_emit_lrz_flush(ring);
1093
1094 fd6_event_write(batch, ring, CACHE_FLUSH_TS, true);
1095 }
1096
1097 static void
1098 fd6_emit_sysmem_prep(struct fd_batch *batch)
1099 {
1100 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
1101 struct fd_ringbuffer *ring = batch->gmem;
1102
1103 fd6_emit_restore(batch, ring);
1104
1105 fd6_emit_lrz_flush(ring);
1106
1107 emit_marker6(ring, 7);
1108 OUT_PKT7(ring, CP_SET_MARKER, 1);
1109 OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(RM6_BYPASS) | 0x10); /* | 0x10 ? */
1110 emit_marker6(ring, 7);
1111
1112 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1113 OUT_RING(ring, 0x0);
1114
1115 fd6_event_write(batch, ring, PC_CCU_INVALIDATE_COLOR, false);
1116 fd6_cache_inv(batch, ring);
1117
1118 #if 0
1119 OUT_PKT4(ring, REG_A6XX_PC_POWER_CNTL, 1);
1120 OUT_RING(ring, 0x00000003); /* PC_POWER_CNTL */
1121 #endif
1122
1123 #if 0
1124 OUT_PKT4(ring, REG_A6XX_VFD_POWER_CNTL, 1);
1125 OUT_RING(ring, 0x00000003); /* VFD_POWER_CNTL */
1126 #endif
1127
1128 /* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */
1129 fd_wfi(batch, ring);
1130 OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
1131 OUT_RING(ring, 0x10000000); /* RB_CCU_CNTL */
1132
1133 set_scissor(ring, 0, 0, pfb->width - 1, pfb->height - 1);
1134
1135 set_window_offset(ring, 0, 0);
1136
1137 set_bin_size(ring, 0, 0, 0xc00000); /* 0xc00000 = BYPASS? */
1138
1139 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
1140 OUT_RING(ring, 0x1);
1141
1142 patch_draws(batch, IGNORE_VISIBILITY);
1143
1144 emit_zs(ring, pfb->zsbuf, NULL);
1145 emit_mrt(ring, pfb, NULL);
1146 emit_msaa(ring, pfb->samples);
1147
1148 update_render_cntl(batch, pfb, false);
1149 }
1150
1151 static void
1152 fd6_emit_sysmem_fini(struct fd_batch *batch)
1153 {
1154 struct fd_ringbuffer *ring = batch->gmem;
1155
1156 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1157 OUT_RING(ring, 0x0);
1158
1159 fd6_emit_lrz_flush(ring);
1160
1161 fd6_event_write(batch, ring, UNK_1D, true);
1162 }
1163
1164 void
1165 fd6_gmem_init(struct pipe_context *pctx)
1166 {
1167 struct fd_context *ctx = fd_context(pctx);
1168
1169 ctx->emit_tile_init = fd6_emit_tile_init;
1170 ctx->emit_tile_prep = fd6_emit_tile_prep;
1171 ctx->emit_tile_mem2gmem = fd6_emit_tile_mem2gmem;
1172 ctx->emit_tile_renderprep = fd6_emit_tile_renderprep;
1173 ctx->emit_tile_gmem2mem = fd6_emit_tile_gmem2mem;
1174 ctx->emit_tile_fini = fd6_emit_tile_fini;
1175 ctx->emit_sysmem_prep = fd6_emit_sysmem_prep;
1176 ctx->emit_sysmem_fini = fd6_emit_sysmem_fini;
1177 }