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freedreno/a6xx: KHR_blend_equation_advanced support
[mesa.git] / src / gallium / drivers / freedreno / a6xx / fd6_gmem.c
1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 * Authors:
25 * Rob Clark <robclark@freedesktop.org>
26 */
27
28 #include <stdio.h>
29
30 #include "pipe/p_state.h"
31 #include "util/u_string.h"
32 #include "util/u_memory.h"
33 #include "util/u_inlines.h"
34 #include "util/u_format.h"
35
36 #include "freedreno_draw.h"
37 #include "freedreno_state.h"
38 #include "freedreno_resource.h"
39
40 #include "fd6_gmem.h"
41 #include "fd6_context.h"
42 #include "fd6_draw.h"
43 #include "fd6_emit.h"
44 #include "fd6_program.h"
45 #include "fd6_format.h"
46 #include "fd6_zsa.h"
47
48 /* some bits in common w/ a4xx: */
49 #include "a4xx/fd4_draw.h"
50
51 static void
52 emit_mrt(struct fd_ringbuffer *ring, struct pipe_framebuffer_state *pfb,
53 struct fd_gmem_stateobj *gmem)
54 {
55 unsigned char mrt_comp[A6XX_MAX_RENDER_TARGETS] = {0};
56 unsigned srgb_cntl = 0;
57 unsigned i;
58
59 for (i = 0; i < pfb->nr_cbufs; i++) {
60 enum a6xx_color_fmt format = 0;
61 enum a3xx_color_swap swap = WZYX;
62 bool sint = false, uint = false;
63 struct fd_resource *rsc = NULL;
64 struct fd_resource_slice *slice = NULL;
65 uint32_t stride = 0;
66 uint32_t offset = 0;
67 uint32_t tile_mode;
68
69 if (!pfb->cbufs[i])
70 continue;
71
72 mrt_comp[i] = 0xf;
73
74 struct pipe_surface *psurf = pfb->cbufs[i];
75 enum pipe_format pformat = psurf->format;
76 rsc = fd_resource(psurf->texture);
77 if (!rsc->bo)
78 continue;
79
80 uint32_t base = gmem ? gmem->cbuf_base[i] : 0;
81 slice = fd_resource_slice(rsc, psurf->u.tex.level);
82 format = fd6_pipe2color(pformat);
83 sint = util_format_is_pure_sint(pformat);
84 uint = util_format_is_pure_uint(pformat);
85
86 if (util_format_is_srgb(pformat))
87 srgb_cntl |= (1 << i);
88
89 offset = fd_resource_offset(rsc, psurf->u.tex.level,
90 psurf->u.tex.first_layer);
91
92 stride = slice->pitch * rsc->cpp * pfb->samples;
93 swap = rsc->tile_mode ? WZYX : fd6_pipe2swap(pformat);
94
95 if (rsc->tile_mode &&
96 fd_resource_level_linear(psurf->texture, psurf->u.tex.level))
97 tile_mode = TILE6_LINEAR;
98 else
99 tile_mode = rsc->tile_mode;
100
101 if (rsc->tile_mode &&
102 fd_resource_level_linear(psurf->texture, psurf->u.tex.level))
103 tile_mode = TILE6_LINEAR;
104 else
105 tile_mode = rsc->tile_mode;
106
107 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
108 debug_assert((offset + slice->size0) <= fd_bo_size(rsc->bo));
109
110 OUT_PKT4(ring, REG_A6XX_RB_MRT_BUF_INFO(i), 6);
111 OUT_RING(ring, A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format) |
112 A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(tile_mode) |
113 A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(swap));
114 OUT_RING(ring, A6XX_RB_MRT_PITCH(stride));
115 OUT_RING(ring, A6XX_RB_MRT_ARRAY_PITCH(slice->size0));
116 OUT_RELOCW(ring, rsc->bo, offset + rsc->offset, 0, 0); /* BASE_LO/HI */
117 OUT_RING(ring, base); /* RB_MRT[i].BASE_GMEM */
118 OUT_PKT4(ring, REG_A6XX_SP_FS_MRT_REG(i), 1);
119 OUT_RING(ring, A6XX_SP_FS_MRT_REG_COLOR_FORMAT(format) |
120 COND(sint, A6XX_SP_FS_MRT_REG_COLOR_SINT) |
121 COND(uint, A6XX_SP_FS_MRT_REG_COLOR_UINT));
122
123 OUT_PKT4(ring, REG_A6XX_RB_MRT_FLAG_BUFFER(i), 3);
124 if (fd6_ubwc_enabled(rsc, tile_mode)) {
125 OUT_RELOCW(ring, rsc->bo, offset + rsc->ubwc_offset, 0, 0); /* BASE_LO/HI */
126 OUT_RING(ring, A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(rsc->ubwc_pitch) |
127 A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(rsc->ubwc_size));
128 } else {
129 OUT_RING(ring, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_LO */
130 OUT_RING(ring, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_HI */
131 OUT_RING(ring, 0x00000000);
132 }
133 }
134
135 OUT_PKT4(ring, REG_A6XX_RB_SRGB_CNTL, 1);
136 OUT_RING(ring, srgb_cntl);
137
138 OUT_PKT4(ring, REG_A6XX_SP_SRGB_CNTL, 1);
139 OUT_RING(ring, srgb_cntl);
140
141 OUT_PKT4(ring, REG_A6XX_RB_RENDER_COMPONENTS, 1);
142 OUT_RING(ring, A6XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
143 A6XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
144 A6XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
145 A6XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
146 A6XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
147 A6XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
148 A6XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
149 A6XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
150
151 OUT_PKT4(ring, REG_A6XX_SP_FS_RENDER_COMPONENTS, 1);
152 OUT_RING(ring,
153 A6XX_SP_FS_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
154 A6XX_SP_FS_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
155 A6XX_SP_FS_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
156 A6XX_SP_FS_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
157 A6XX_SP_FS_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
158 A6XX_SP_FS_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
159 A6XX_SP_FS_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
160 A6XX_SP_FS_RENDER_COMPONENTS_RT7(mrt_comp[7]));
161 }
162
163 static void
164 emit_zs(struct fd_ringbuffer *ring, struct pipe_surface *zsbuf,
165 struct fd_gmem_stateobj *gmem)
166 {
167 if (zsbuf) {
168 struct fd_resource *rsc = fd_resource(zsbuf->texture);
169 enum a6xx_depth_format fmt = fd6_pipe2depth(zsbuf->format);
170 struct fd_resource_slice *slice = fd_resource_slice(rsc, 0);
171 uint32_t stride = slice->pitch * rsc->cpp;
172 uint32_t size = slice->size0;
173 uint32_t base = gmem ? gmem->zsbuf_base[0] : 0;
174
175 bool ubwc_enabled =
176 !fd_resource_level_linear(zsbuf->texture, zsbuf->u.tex.level) && rsc->ubwc_size;
177
178 OUT_PKT4(ring, REG_A6XX_RB_DEPTH_BUFFER_INFO, 6);
179 OUT_RING(ring, A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(fmt));
180 OUT_RING(ring, A6XX_RB_DEPTH_BUFFER_PITCH(stride));
181 OUT_RING(ring, A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(size));
182 OUT_RELOCW(ring, rsc->bo, rsc->offset, 0, 0); /* RB_DEPTH_BUFFER_BASE_LO/HI */
183 OUT_RING(ring, base); /* RB_DEPTH_BUFFER_BASE_GMEM */
184
185 OUT_PKT4(ring, REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO, 1);
186 OUT_RING(ring, A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(fmt));
187
188 OUT_PKT4(ring, REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO, 3);
189 if (ubwc_enabled) {
190 OUT_RELOCW(ring, rsc->bo, rsc->ubwc_offset, 0, 0); /* BASE_LO/HI */
191 OUT_RING(ring, A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(rsc->ubwc_pitch) |
192 A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(rsc->ubwc_size));
193 } else {
194 OUT_RING(ring, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_LO */
195 OUT_RING(ring, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_HI */
196 OUT_RING(ring, 0x00000000);
197 }
198
199 if (rsc->lrz) {
200 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO, 5);
201 OUT_RELOCW(ring, rsc->lrz, 0, 0, 0);
202 OUT_RING(ring, A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH(rsc->lrz_pitch));
203 //OUT_RELOCW(ring, rsc->lrz, 0, 0, 0); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO/HI */
204 // XXX a6xx seems to use a different buffer here.. not sure what for..
205 OUT_RING(ring, 0x00000000);
206 OUT_RING(ring, 0x00000000);
207 } else {
208 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO, 5);
209 OUT_RING(ring, 0x00000000);
210 OUT_RING(ring, 0x00000000);
211 OUT_RING(ring, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
212 OUT_RING(ring, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO */
213 OUT_RING(ring, 0x00000000);
214 }
215
216 if (rsc->stencil) {
217 struct fd_resource_slice *slice = fd_resource_slice(rsc->stencil, 0);
218 stride = slice->pitch * rsc->stencil->cpp;
219 size = slice->size0;
220 uint32_t base = gmem ? gmem->zsbuf_base[1] : 0;
221
222 OUT_PKT4(ring, REG_A6XX_RB_STENCIL_INFO, 6);
223 OUT_RING(ring, A6XX_RB_STENCIL_INFO_SEPARATE_STENCIL);
224 OUT_RING(ring, A6XX_RB_STENCIL_BUFFER_PITCH(stride));
225 OUT_RING(ring, A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(size));
226 OUT_RELOCW(ring, rsc->stencil->bo, 0, 0, 0); /* RB_STENCIL_BASE_LO/HI */
227 OUT_RING(ring, base); /* RB_STENCIL_BASE_LO */
228 } else {
229 OUT_PKT4(ring, REG_A6XX_RB_STENCIL_INFO, 1);
230 OUT_RING(ring, 0x00000000); /* RB_STENCIL_INFO */
231 }
232 } else {
233 OUT_PKT4(ring, REG_A6XX_RB_DEPTH_BUFFER_INFO, 6);
234 OUT_RING(ring, A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH6_NONE));
235 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_PITCH */
236 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_ARRAY_PITCH */
237 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_BASE_LO */
238 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_BASE_HI */
239 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_BASE_GMEM */
240
241 OUT_PKT4(ring, REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO, 1);
242 OUT_RING(ring, A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH6_NONE));
243
244 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO, 5);
245 OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
246 OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
247 OUT_RING(ring, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
248 OUT_RING(ring, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO */
249 OUT_RING(ring, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI */
250
251 OUT_PKT4(ring, REG_A6XX_RB_STENCIL_INFO, 1);
252 OUT_RING(ring, 0x00000000); /* RB_STENCIL_INFO */
253 }
254 }
255
256 static bool
257 use_hw_binning(struct fd_batch *batch)
258 {
259 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
260
261 // TODO figure out hw limits for binning
262
263 return fd_binning_enabled && ((gmem->nbins_x * gmem->nbins_y) > 2) &&
264 (batch->num_draws > 0);
265 }
266
267 static void
268 patch_fb_read(struct fd_batch *batch)
269 {
270 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
271
272 for (unsigned i = 0; i < fd_patch_num_elements(&batch->fb_read_patches); i++) {
273 struct fd_cs_patch *patch = fd_patch_element(&batch->fb_read_patches, i);
274 *patch->cs = patch->val | A6XX_TEX_CONST_2_PITCH(gmem->bin_w * gmem->cbuf_cpp[0]);
275 }
276 util_dynarray_resize(&batch->fb_read_patches, 0);
277 }
278
279 static void
280 patch_draws(struct fd_batch *batch, enum pc_di_vis_cull_mode vismode)
281 {
282 unsigned i;
283 for (i = 0; i < fd_patch_num_elements(&batch->draw_patches); i++) {
284 struct fd_cs_patch *patch = fd_patch_element(&batch->draw_patches, i);
285 *patch->cs = patch->val | DRAW4(0, 0, 0, vismode);
286 }
287 util_dynarray_resize(&batch->draw_patches, 0);
288 }
289
290 static void
291 update_render_cntl(struct fd_batch *batch, struct pipe_framebuffer_state *pfb, bool binning)
292 {
293 struct fd_ringbuffer *ring = batch->gmem;
294 uint32_t cntl = 0;
295 bool depth_ubwc_enable = false;
296 uint32_t mrts_ubwc_enable = 0;
297 int i;
298
299 if (pfb->zsbuf) {
300 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
301 depth_ubwc_enable =
302 !fd_resource_level_linear(pfb->zsbuf->texture, pfb->zsbuf->u.tex.level) && rsc->ubwc_size;
303 }
304
305 for (i = 0; i < pfb->nr_cbufs; i++) {
306 if (!pfb->cbufs[i])
307 continue;
308
309 struct pipe_surface *psurf = pfb->cbufs[i];
310 struct fd_resource *rsc = fd_resource(psurf->texture);
311 if (!rsc->bo)
312 continue;
313
314 if (fd6_ubwc_enabled(rsc, rsc->tile_mode))
315 mrts_ubwc_enable |= 1 << i;
316 }
317
318 cntl |= A6XX_RB_RENDER_CNTL_UNK4;
319 if (binning)
320 cntl |= A6XX_RB_RENDER_CNTL_BINNING;
321
322 OUT_PKT7(ring, CP_REG_WRITE, 3);
323 OUT_RING(ring, 0x2);
324 OUT_RING(ring, REG_A6XX_RB_RENDER_CNTL);
325 OUT_RING(ring, cntl |
326 COND(depth_ubwc_enable, A6XX_RB_RENDER_CNTL_FLAG_DEPTH) |
327 A6XX_RB_RENDER_CNTL_FLAG_MRTS(mrts_ubwc_enable));
328 }
329
330 static void
331 update_vsc_pipe(struct fd_batch *batch)
332 {
333 struct fd_context *ctx = batch->ctx;
334 struct fd6_context *fd6_ctx = fd6_context(ctx);
335 struct fd_gmem_stateobj *gmem = &ctx->gmem;
336 struct fd_ringbuffer *ring = batch->gmem;
337 int i;
338
339 OUT_PKT4(ring, REG_A6XX_VSC_BIN_SIZE, 3);
340 OUT_RING(ring, A6XX_VSC_BIN_SIZE_WIDTH(gmem->bin_w) |
341 A6XX_VSC_BIN_SIZE_HEIGHT(gmem->bin_h));
342 OUT_RELOCW(ring, fd6_ctx->vsc_data,
343 32 * A6XX_VSC_DATA_PITCH, 0, 0); /* VSC_SIZE_ADDRESS_LO/HI */
344
345 OUT_PKT4(ring, REG_A6XX_VSC_BIN_COUNT, 1);
346 OUT_RING(ring, A6XX_VSC_BIN_COUNT_NX(gmem->nbins_x) |
347 A6XX_VSC_BIN_COUNT_NY(gmem->nbins_y));
348
349 OUT_PKT4(ring, REG_A6XX_VSC_PIPE_CONFIG_REG(0), 32);
350 for (i = 0; i < 32; i++) {
351 struct fd_vsc_pipe *pipe = &ctx->vsc_pipe[i];
352 OUT_RING(ring, A6XX_VSC_PIPE_CONFIG_REG_X(pipe->x) |
353 A6XX_VSC_PIPE_CONFIG_REG_Y(pipe->y) |
354 A6XX_VSC_PIPE_CONFIG_REG_W(pipe->w) |
355 A6XX_VSC_PIPE_CONFIG_REG_H(pipe->h));
356 }
357
358 OUT_PKT4(ring, REG_A6XX_VSC_PIPE_DATA2_ADDRESS_LO, 4);
359 OUT_RELOCW(ring, fd6_ctx->vsc_data2, 0, 0, 0);
360 OUT_RING(ring, A6XX_VSC_DATA2_PITCH);
361 OUT_RING(ring, fd_bo_size(fd6_ctx->vsc_data2));
362
363 OUT_PKT4(ring, REG_A6XX_VSC_PIPE_DATA_ADDRESS_LO, 4);
364 OUT_RELOCW(ring, fd6_ctx->vsc_data, 0, 0, 0);
365 OUT_RING(ring, A6XX_VSC_DATA_PITCH);
366 OUT_RING(ring, fd_bo_size(fd6_ctx->vsc_data));
367 }
368
369 static void
370 set_scissor(struct fd_ringbuffer *ring, uint32_t x1, uint32_t y1, uint32_t x2, uint32_t y2)
371 {
372 OUT_PKT4(ring, REG_A6XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
373 OUT_RING(ring, A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X(x1) |
374 A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(y1));
375 OUT_RING(ring, A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X(x2) |
376 A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(y2));
377
378 OUT_PKT4(ring, REG_A6XX_GRAS_RESOLVE_CNTL_1, 2);
379 OUT_RING(ring, A6XX_GRAS_RESOLVE_CNTL_1_X(x1) |
380 A6XX_GRAS_RESOLVE_CNTL_1_Y(y1));
381 OUT_RING(ring, A6XX_GRAS_RESOLVE_CNTL_2_X(x2) |
382 A6XX_GRAS_RESOLVE_CNTL_2_Y(y2));
383 }
384
385 static void
386 set_bin_size(struct fd_ringbuffer *ring, uint32_t w, uint32_t h, uint32_t flag)
387 {
388 OUT_PKT4(ring, REG_A6XX_GRAS_BIN_CONTROL, 1);
389 OUT_RING(ring, A6XX_GRAS_BIN_CONTROL_BINW(w) |
390 A6XX_GRAS_BIN_CONTROL_BINH(h) | flag);
391
392 OUT_PKT4(ring, REG_A6XX_RB_BIN_CONTROL, 1);
393 OUT_RING(ring, A6XX_RB_BIN_CONTROL_BINW(w) |
394 A6XX_RB_BIN_CONTROL_BINH(h) | flag);
395
396 /* no flag for RB_BIN_CONTROL2... */
397 OUT_PKT4(ring, REG_A6XX_RB_BIN_CONTROL2, 1);
398 OUT_RING(ring, A6XX_RB_BIN_CONTROL2_BINW(w) |
399 A6XX_RB_BIN_CONTROL2_BINH(h));
400 }
401
402 static void
403 emit_binning_pass(struct fd_batch *batch)
404 {
405 struct fd_context *ctx = batch->ctx;
406 struct fd_ringbuffer *ring = batch->gmem;
407 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
408
409 uint32_t x1 = gmem->minx;
410 uint32_t y1 = gmem->miny;
411 uint32_t x2 = gmem->minx + gmem->width - 1;
412 uint32_t y2 = gmem->miny + gmem->height - 1;
413
414 set_scissor(ring, x1, y1, x2, y2);
415
416 emit_marker6(ring, 7);
417 OUT_PKT7(ring, CP_SET_MARKER, 1);
418 OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(RM6_BINNING));
419 emit_marker6(ring, 7);
420
421 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
422 OUT_RING(ring, 0x1);
423
424 OUT_PKT7(ring, CP_SET_MODE, 1);
425 OUT_RING(ring, 0x1);
426
427 OUT_WFI5(ring);
428
429 OUT_PKT4(ring, REG_A6XX_VFD_MODE_CNTL, 1);
430 OUT_RING(ring, A6XX_VFD_MODE_CNTL_BINNING_PASS);
431
432 update_vsc_pipe(batch);
433
434 OUT_PKT4(ring, REG_A6XX_PC_UNKNOWN_9805, 1);
435 OUT_RING(ring, 0x1);
436
437 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A0F8, 1);
438 OUT_RING(ring, 0x1);
439
440 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
441 OUT_RING(ring, UNK_2C);
442
443 OUT_PKT4(ring, REG_A6XX_RB_WINDOW_OFFSET, 1);
444 OUT_RING(ring, A6XX_RB_WINDOW_OFFSET_X(0) |
445 A6XX_RB_WINDOW_OFFSET_Y(0));
446
447 OUT_PKT4(ring, REG_A6XX_SP_TP_WINDOW_OFFSET, 1);
448 OUT_RING(ring, A6XX_SP_TP_WINDOW_OFFSET_X(0) |
449 A6XX_SP_TP_WINDOW_OFFSET_Y(0));
450
451 /* emit IB to binning drawcmds: */
452 fd6_emit_ib(ring, batch->draw);
453
454 fd_reset_wfi(batch);
455
456 OUT_PKT7(ring, CP_SET_DRAW_STATE, 3);
457 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
458 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
459 CP_SET_DRAW_STATE__0_GROUP_ID(0));
460 OUT_RING(ring, CP_SET_DRAW_STATE__1_ADDR_LO(0));
461 OUT_RING(ring, CP_SET_DRAW_STATE__2_ADDR_HI(0));
462
463 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
464 OUT_RING(ring, UNK_2D);
465
466 OUT_PKT7(ring, CP_EVENT_WRITE, 4);
467 OUT_RING(ring, CACHE_FLUSH_TS);
468 OUT_RELOCW(ring, fd6_context(ctx)->blit_mem, 0, 0, 0); /* ADDR_LO/HI */
469 OUT_RING(ring, 0x00000000);
470
471 fd_wfi(batch, ring);
472 }
473
474 static void
475 emit_msaa(struct fd_ringbuffer *ring, unsigned nr)
476 {
477 enum a3xx_msaa_samples samples = fd_msaa_samples(nr);
478
479 OUT_PKT4(ring, REG_A6XX_SP_TP_RAS_MSAA_CNTL, 2);
480 OUT_RING(ring, A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(samples));
481 OUT_RING(ring, A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(samples) |
482 COND(samples == MSAA_ONE, A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE));
483
484 OUT_PKT4(ring, REG_A6XX_GRAS_RAS_MSAA_CNTL, 2);
485 OUT_RING(ring, A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(samples));
486 OUT_RING(ring, A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(samples) |
487 COND(samples == MSAA_ONE, A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE));
488
489 OUT_PKT4(ring, REG_A6XX_RB_RAS_MSAA_CNTL, 2);
490 OUT_RING(ring, A6XX_RB_RAS_MSAA_CNTL_SAMPLES(samples));
491 OUT_RING(ring, A6XX_RB_DEST_MSAA_CNTL_SAMPLES(samples) |
492 COND(samples == MSAA_ONE, A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE));
493
494 OUT_PKT4(ring, REG_A6XX_RB_MSAA_CNTL, 1);
495 OUT_RING(ring, A6XX_RB_MSAA_CNTL_SAMPLES(samples));
496 }
497
498 static void prepare_tile_setup_ib(struct fd_batch *batch);
499 static void prepare_tile_fini_ib(struct fd_batch *batch);
500
501 /* before first tile */
502 static void
503 fd6_emit_tile_init(struct fd_batch *batch)
504 {
505 struct fd_context *ctx = batch->ctx;
506 struct fd_ringbuffer *ring = batch->gmem;
507 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
508 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
509
510 fd6_emit_restore(batch, ring);
511
512 fd6_emit_lrz_flush(ring);
513
514 if (batch->lrz_clear)
515 fd6_emit_ib(ring, batch->lrz_clear);
516
517 fd6_cache_inv(batch, ring);
518
519 prepare_tile_setup_ib(batch);
520 prepare_tile_fini_ib(batch);
521
522 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
523 OUT_RING(ring, 0x0);
524
525 /* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */
526 fd_wfi(batch, ring);
527 OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
528 OUT_RING(ring, 0x7c400004); /* RB_CCU_CNTL */
529
530 emit_zs(ring, pfb->zsbuf, &ctx->gmem);
531 emit_mrt(ring, pfb, &ctx->gmem);
532 emit_msaa(ring, pfb->samples);
533 patch_fb_read(batch);
534
535 if (use_hw_binning(batch)) {
536 set_bin_size(ring, gmem->bin_w, gmem->bin_h,
537 A6XX_RB_BIN_CONTROL_BINNING_PASS | 0x6000000);
538 update_render_cntl(batch, pfb, true);
539 emit_binning_pass(batch);
540 patch_draws(batch, USE_VISIBILITY);
541
542 set_bin_size(ring, gmem->bin_w, gmem->bin_h,
543 A6XX_RB_BIN_CONTROL_USE_VIZ | 0x6000000);
544
545 OUT_PKT4(ring, REG_A6XX_VFD_MODE_CNTL, 1);
546 OUT_RING(ring, 0x0);
547 } else {
548 set_bin_size(ring, gmem->bin_w, gmem->bin_h, 0x6000000);
549 patch_draws(batch, IGNORE_VISIBILITY);
550 }
551
552 update_render_cntl(batch, pfb, false);
553 }
554
555 static void
556 set_window_offset(struct fd_ringbuffer *ring, uint32_t x1, uint32_t y1)
557 {
558 OUT_PKT4(ring, REG_A6XX_RB_WINDOW_OFFSET, 1);
559 OUT_RING(ring, A6XX_RB_WINDOW_OFFSET_X(x1) |
560 A6XX_RB_WINDOW_OFFSET_Y(y1));
561
562 OUT_PKT4(ring, REG_A6XX_RB_WINDOW_OFFSET2, 1);
563 OUT_RING(ring, A6XX_RB_WINDOW_OFFSET2_X(x1) |
564 A6XX_RB_WINDOW_OFFSET2_Y(y1));
565
566 OUT_PKT4(ring, REG_A6XX_SP_WINDOW_OFFSET, 1);
567 OUT_RING(ring, A6XX_SP_WINDOW_OFFSET_X(x1) |
568 A6XX_SP_WINDOW_OFFSET_Y(y1));
569
570 OUT_PKT4(ring, REG_A6XX_SP_TP_WINDOW_OFFSET, 1);
571 OUT_RING(ring, A6XX_SP_TP_WINDOW_OFFSET_X(x1) |
572 A6XX_SP_TP_WINDOW_OFFSET_Y(y1));
573 }
574
575 /* before mem2gmem */
576 static void
577 fd6_emit_tile_prep(struct fd_batch *batch, struct fd_tile *tile)
578 {
579 struct fd_context *ctx = batch->ctx;
580 struct fd6_context *fd6_ctx = fd6_context(ctx);
581 struct fd_ringbuffer *ring = batch->gmem;
582
583 OUT_PKT7(ring, CP_SET_MARKER, 1);
584 OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(0x7));
585
586 emit_marker6(ring, 7);
587 OUT_PKT7(ring, CP_SET_MARKER, 1);
588 OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(RM6_GMEM) | 0x10);
589 emit_marker6(ring, 7);
590
591 uint32_t x1 = tile->xoff;
592 uint32_t y1 = tile->yoff;
593 uint32_t x2 = tile->xoff + tile->bin_w - 1;
594 uint32_t y2 = tile->yoff + tile->bin_h - 1;
595
596 set_scissor(ring, x1, y1, x2, y2);
597
598 set_window_offset(ring, x1, y1);
599
600 OUT_PKT4(ring, REG_A6XX_VPC_SO_OVERRIDE, 1);
601 OUT_RING(ring, A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
602
603 if (use_hw_binning(batch)) {
604 struct fd_vsc_pipe *pipe = &ctx->vsc_pipe[tile->p];
605
606 OUT_PKT7(ring, CP_WAIT_FOR_ME, 0);
607
608 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
609 OUT_RING(ring, 0x0);
610
611 OUT_PKT7(ring, CP_SET_MODE, 1);
612 OUT_RING(ring, 0x0);
613
614 OUT_PKT7(ring, CP_SET_BIN_DATA5, 7);
615 OUT_RING(ring, CP_SET_BIN_DATA5_0_VSC_SIZE(pipe->w * pipe->h) |
616 CP_SET_BIN_DATA5_0_VSC_N(tile->n));
617 OUT_RELOC(ring, fd6_ctx->vsc_data, /* VSC_PIPE[p].DATA_ADDRESS */
618 (tile->p * A6XX_VSC_DATA_PITCH), 0, 0);
619 OUT_RELOC(ring, fd6_ctx->vsc_data, /* VSC_SIZE_ADDRESS + (p * 4) */
620 (tile->p * 4) + (32 * A6XX_VSC_DATA_PITCH), 0, 0);
621 OUT_RELOC(ring, fd6_ctx->vsc_data2,
622 (tile->p * A6XX_VSC_DATA2_PITCH), 0, 0);
623 } else {
624 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
625 OUT_RING(ring, 0x1);
626
627 OUT_PKT7(ring, CP_SET_MODE, 1);
628 OUT_RING(ring, 0x0);
629 }
630 }
631
632 static void
633 set_blit_scissor(struct fd_batch *batch, struct fd_ringbuffer *ring)
634 {
635 struct pipe_scissor_state blit_scissor;
636 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
637
638 blit_scissor.minx = batch->max_scissor.minx;
639 blit_scissor.miny = batch->max_scissor.miny;
640 blit_scissor.maxx = MIN2(pfb->width, batch->max_scissor.maxx);
641 blit_scissor.maxy = MIN2(pfb->height, batch->max_scissor.maxy);
642
643 OUT_PKT4(ring, REG_A6XX_RB_BLIT_SCISSOR_TL, 2);
644 OUT_RING(ring,
645 A6XX_RB_BLIT_SCISSOR_TL_X(blit_scissor.minx) |
646 A6XX_RB_BLIT_SCISSOR_TL_Y(blit_scissor.miny));
647 OUT_RING(ring,
648 A6XX_RB_BLIT_SCISSOR_BR_X(blit_scissor.maxx - 1) |
649 A6XX_RB_BLIT_SCISSOR_BR_Y(blit_scissor.maxy - 1));
650 }
651
652 static void
653 emit_blit(struct fd_batch *batch,
654 struct fd_ringbuffer *ring,
655 uint32_t base,
656 struct pipe_surface *psurf,
657 bool stencil)
658 {
659 struct fd_resource_slice *slice;
660 struct fd_resource *rsc = fd_resource(psurf->texture);
661 enum pipe_format pfmt = psurf->format;
662 uint32_t offset;
663
664 /* separate stencil case: */
665 if (stencil) {
666 rsc = rsc->stencil;
667 pfmt = rsc->base.format;
668 }
669
670 slice = fd_resource_slice(rsc, psurf->u.tex.level);
671 offset = fd_resource_offset(rsc, psurf->u.tex.level,
672 psurf->u.tex.first_layer);
673
674 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
675
676 enum a6xx_color_fmt format = fd6_pipe2color(pfmt);
677 uint32_t stride = slice->pitch * rsc->cpp;
678 uint32_t size = slice->size0;
679 enum a3xx_color_swap swap = rsc->tile_mode ? WZYX : fd6_pipe2swap(pfmt);
680 enum a3xx_msaa_samples samples =
681 fd_msaa_samples(rsc->base.nr_samples);
682 uint32_t tile_mode;
683
684 if (rsc->tile_mode &&
685 fd_resource_level_linear(&rsc->base, psurf->u.tex.level))
686 tile_mode = TILE6_LINEAR;
687 else
688 tile_mode = rsc->tile_mode;
689
690 OUT_PKT4(ring, REG_A6XX_RB_BLIT_DST_INFO, 5);
691 OUT_RING(ring,
692 A6XX_RB_BLIT_DST_INFO_TILE_MODE(tile_mode) |
693 A6XX_RB_BLIT_DST_INFO_SAMPLES(samples) |
694 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(format) |
695 A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(swap) |
696 COND(fd6_ubwc_enabled(rsc, tile_mode), A6XX_RB_BLIT_DST_INFO_FLAGS));
697 OUT_RELOCW(ring, rsc->bo, offset + rsc->offset, 0, 0); /* RB_BLIT_DST_LO/HI */
698 OUT_RING(ring, A6XX_RB_BLIT_DST_PITCH(stride));
699 OUT_RING(ring, A6XX_RB_BLIT_DST_ARRAY_PITCH(size));
700
701 OUT_PKT4(ring, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
702 OUT_RING(ring, base);
703
704 if (fd6_ubwc_enabled(rsc, tile_mode)) {
705 OUT_PKT4(ring, REG_A6XX_RB_BLIT_FLAG_DST_LO, 3);
706 OUT_RELOCW(ring, rsc->bo, offset + rsc->ubwc_offset, 0, 0);
707 OUT_RING(ring, A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(rsc->ubwc_pitch) |
708 A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(rsc->ubwc_size));
709 }
710
711 fd6_emit_blit(batch, ring);
712 }
713
714 static void
715 emit_restore_blit(struct fd_batch *batch,
716 struct fd_ringbuffer *ring,
717 uint32_t base,
718 struct pipe_surface *psurf,
719 unsigned buffer)
720 {
721 uint32_t info = 0;
722 bool stencil = false;
723
724 switch (buffer) {
725 case FD_BUFFER_COLOR:
726 info |= A6XX_RB_BLIT_INFO_UNK0;
727 break;
728 case FD_BUFFER_STENCIL:
729 info |= A6XX_RB_BLIT_INFO_UNK0;
730 stencil = true;
731 break;
732 case FD_BUFFER_DEPTH:
733 info |= A6XX_RB_BLIT_INFO_DEPTH | A6XX_RB_BLIT_INFO_UNK0;
734 break;
735 }
736
737 if (util_format_is_pure_integer(psurf->format))
738 info |= A6XX_RB_BLIT_INFO_INTEGER;
739
740 OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
741 OUT_RING(ring, info | A6XX_RB_BLIT_INFO_GMEM);
742
743 emit_blit(batch, ring, base, psurf, stencil);
744 }
745
746 static void
747 emit_clears(struct fd_batch *batch, struct fd_ringbuffer *ring)
748 {
749 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
750 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
751 enum a3xx_msaa_samples samples = fd_msaa_samples(pfb->samples);
752
753 uint32_t buffers = batch->fast_cleared;
754
755 if (buffers & PIPE_CLEAR_COLOR) {
756
757 for (int i = 0; i < pfb->nr_cbufs; i++) {
758 union pipe_color_union *color = &batch->clear_color[i];
759 union util_color uc = {0};
760
761 if (!pfb->cbufs[i])
762 continue;
763
764 if (!(buffers & (PIPE_CLEAR_COLOR0 << i)))
765 continue;
766
767 enum pipe_format pfmt = pfb->cbufs[i]->format;
768
769 // XXX I think RB_CLEAR_COLOR_DWn wants to take into account SWAP??
770 union pipe_color_union swapped;
771 switch (fd6_pipe2swap(pfmt)) {
772 case WZYX:
773 swapped.ui[0] = color->ui[0];
774 swapped.ui[1] = color->ui[1];
775 swapped.ui[2] = color->ui[2];
776 swapped.ui[3] = color->ui[3];
777 break;
778 case WXYZ:
779 swapped.ui[2] = color->ui[0];
780 swapped.ui[1] = color->ui[1];
781 swapped.ui[0] = color->ui[2];
782 swapped.ui[3] = color->ui[3];
783 break;
784 case ZYXW:
785 swapped.ui[3] = color->ui[0];
786 swapped.ui[0] = color->ui[1];
787 swapped.ui[1] = color->ui[2];
788 swapped.ui[2] = color->ui[3];
789 break;
790 case XYZW:
791 swapped.ui[3] = color->ui[0];
792 swapped.ui[2] = color->ui[1];
793 swapped.ui[1] = color->ui[2];
794 swapped.ui[0] = color->ui[3];
795 break;
796 }
797
798 if (util_format_is_pure_uint(pfmt)) {
799 util_format_write_4ui(pfmt, swapped.ui, 0, &uc, 0, 0, 0, 1, 1);
800 } else if (util_format_is_pure_sint(pfmt)) {
801 util_format_write_4i(pfmt, swapped.i, 0, &uc, 0, 0, 0, 1, 1);
802 } else {
803 util_pack_color(swapped.f, pfmt, &uc);
804 }
805
806 OUT_PKT4(ring, REG_A6XX_RB_BLIT_DST_INFO, 1);
807 OUT_RING(ring, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR) |
808 A6XX_RB_BLIT_DST_INFO_SAMPLES(samples) |
809 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(fd6_pipe2color(pfmt)));
810
811 OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
812 OUT_RING(ring, A6XX_RB_BLIT_INFO_GMEM |
813 A6XX_RB_BLIT_INFO_CLEAR_MASK(0xf));
814
815 OUT_PKT4(ring, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
816 OUT_RING(ring, gmem->cbuf_base[i]);
817
818 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_88D0, 1);
819 OUT_RING(ring, 0);
820
821 OUT_PKT4(ring, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 4);
822 OUT_RING(ring, uc.ui[0]);
823 OUT_RING(ring, uc.ui[1]);
824 OUT_RING(ring, uc.ui[2]);
825 OUT_RING(ring, uc.ui[3]);
826
827 fd6_emit_blit(batch, ring);
828 }
829 }
830
831 const bool has_depth = pfb->zsbuf;
832 const bool has_separate_stencil =
833 has_depth && fd_resource(pfb->zsbuf->texture)->stencil;
834
835 /* First clear depth or combined depth/stencil. */
836 if ((has_depth && (buffers & PIPE_CLEAR_DEPTH)) ||
837 (!has_separate_stencil && (buffers & PIPE_CLEAR_STENCIL))) {
838 enum pipe_format pfmt = pfb->zsbuf->format;
839 uint32_t clear_value;
840 uint32_t mask = 0;
841
842 if (has_separate_stencil) {
843 pfmt = util_format_get_depth_only(pfb->zsbuf->format);
844 clear_value = util_pack_z(pfmt, batch->clear_depth);
845 } else {
846 pfmt = pfb->zsbuf->format;
847 clear_value = util_pack_z_stencil(pfmt, batch->clear_depth,
848 batch->clear_stencil);
849 }
850
851 if (buffers & PIPE_CLEAR_DEPTH)
852 mask |= 0x1;
853
854 if (!has_separate_stencil && (buffers & PIPE_CLEAR_STENCIL))
855 mask |= 0x2;
856
857 OUT_PKT4(ring, REG_A6XX_RB_BLIT_DST_INFO, 1);
858 OUT_RING(ring, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR) |
859 A6XX_RB_BLIT_DST_INFO_SAMPLES(samples) |
860 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(fd6_pipe2color(pfmt)));
861
862 OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
863 OUT_RING(ring, A6XX_RB_BLIT_INFO_GMEM |
864 // XXX UNK0 for separate stencil ??
865 A6XX_RB_BLIT_INFO_DEPTH |
866 A6XX_RB_BLIT_INFO_CLEAR_MASK(mask));
867
868 OUT_PKT4(ring, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
869 OUT_RING(ring, gmem->zsbuf_base[0]);
870
871 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_88D0, 1);
872 OUT_RING(ring, 0);
873
874 OUT_PKT4(ring, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 1);
875 OUT_RING(ring, clear_value);
876
877 fd6_emit_blit(batch, ring);
878 }
879
880 /* Then clear the separate stencil buffer in case of 32 bit depth
881 * formats with separate stencil. */
882 if (has_separate_stencil && (buffers & PIPE_CLEAR_STENCIL)) {
883 OUT_PKT4(ring, REG_A6XX_RB_BLIT_DST_INFO, 1);
884 OUT_RING(ring, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR) |
885 A6XX_RB_BLIT_DST_INFO_SAMPLES(samples) |
886 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(RB6_R8_UINT));
887
888 OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
889 OUT_RING(ring, A6XX_RB_BLIT_INFO_GMEM |
890 //A6XX_RB_BLIT_INFO_UNK0 |
891 A6XX_RB_BLIT_INFO_DEPTH |
892 A6XX_RB_BLIT_INFO_CLEAR_MASK(0x1));
893
894 OUT_PKT4(ring, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
895 OUT_RING(ring, gmem->zsbuf_base[1]);
896
897 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_88D0, 1);
898 OUT_RING(ring, 0);
899
900 OUT_PKT4(ring, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 1);
901 OUT_RING(ring, batch->clear_stencil & 0xff);
902
903 fd6_emit_blit(batch, ring);
904 }
905 }
906
907 /*
908 * transfer from system memory to gmem
909 */
910 static void
911 emit_restore_blits(struct fd_batch *batch, struct fd_ringbuffer *ring)
912 {
913 struct fd_context *ctx = batch->ctx;
914 struct fd_gmem_stateobj *gmem = &ctx->gmem;
915 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
916
917 if (batch->restore & FD_BUFFER_COLOR) {
918 unsigned i;
919 for (i = 0; i < pfb->nr_cbufs; i++) {
920 if (!pfb->cbufs[i])
921 continue;
922 if (!(batch->restore & (PIPE_CLEAR_COLOR0 << i)))
923 continue;
924 emit_restore_blit(batch, ring, gmem->cbuf_base[i], pfb->cbufs[i],
925 FD_BUFFER_COLOR);
926 }
927 }
928
929 if (batch->restore & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
930 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
931
932 if (!rsc->stencil || (batch->restore & FD_BUFFER_DEPTH)) {
933 emit_restore_blit(batch, ring, gmem->zsbuf_base[0], pfb->zsbuf,
934 FD_BUFFER_DEPTH);
935 }
936 if (rsc->stencil && (batch->restore & FD_BUFFER_STENCIL)) {
937 emit_restore_blit(batch, ring, gmem->zsbuf_base[1], pfb->zsbuf,
938 FD_BUFFER_STENCIL);
939 }
940 }
941 }
942
943 static void
944 prepare_tile_setup_ib(struct fd_batch *batch)
945 {
946 batch->tile_setup = fd_submit_new_ringbuffer(batch->submit, 0x1000,
947 FD_RINGBUFFER_STREAMING);
948
949 set_blit_scissor(batch, batch->tile_setup);
950
951 emit_restore_blits(batch, batch->tile_setup);
952 emit_clears(batch, batch->tile_setup);
953 }
954
955 /*
956 * transfer from system memory to gmem
957 */
958 static void
959 fd6_emit_tile_mem2gmem(struct fd_batch *batch, struct fd_tile *tile)
960 {
961 }
962
963 /* before IB to rendering cmds: */
964 static void
965 fd6_emit_tile_renderprep(struct fd_batch *batch, struct fd_tile *tile)
966 {
967 fd6_emit_ib(batch->gmem, batch->tile_setup);
968 }
969
970 static void
971 emit_resolve_blit(struct fd_batch *batch,
972 struct fd_ringbuffer *ring,
973 uint32_t base,
974 struct pipe_surface *psurf,
975 unsigned buffer)
976 {
977 uint32_t info = 0;
978 bool stencil = false;
979
980 if (!fd_resource(psurf->texture)->valid)
981 return;
982
983 switch (buffer) {
984 case FD_BUFFER_COLOR:
985 break;
986 case FD_BUFFER_STENCIL:
987 info |= A6XX_RB_BLIT_INFO_UNK0;
988 stencil = true;
989 break;
990 case FD_BUFFER_DEPTH:
991 info |= A6XX_RB_BLIT_INFO_DEPTH;
992 break;
993 }
994
995 if (util_format_is_pure_integer(psurf->format))
996 info |= A6XX_RB_BLIT_INFO_INTEGER;
997
998 OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
999 OUT_RING(ring, info);
1000
1001 emit_blit(batch, ring, base, psurf, stencil);
1002 }
1003
1004 /*
1005 * transfer from gmem to system memory (ie. normal RAM)
1006 */
1007
1008 static void
1009 prepare_tile_fini_ib(struct fd_batch *batch)
1010 {
1011 struct fd_context *ctx = batch->ctx;
1012 struct fd_gmem_stateobj *gmem = &ctx->gmem;
1013 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
1014 struct fd_ringbuffer *ring;
1015
1016 batch->tile_fini = fd_submit_new_ringbuffer(batch->submit, 0x1000,
1017 FD_RINGBUFFER_STREAMING);
1018 ring = batch->tile_fini;
1019
1020 if (use_hw_binning(batch)) {
1021 OUT_PKT7(ring, CP_SET_MARKER, 1);
1022 OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(0x5) | 0x10);
1023 }
1024
1025 OUT_PKT7(ring, CP_SET_DRAW_STATE, 3);
1026 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
1027 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
1028 CP_SET_DRAW_STATE__0_GROUP_ID(0));
1029 OUT_RING(ring, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1030 OUT_RING(ring, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1031
1032 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1033 OUT_RING(ring, 0x0);
1034
1035 emit_marker6(ring, 7);
1036 OUT_PKT7(ring, CP_SET_MARKER, 1);
1037 OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE) | 0x10);
1038 emit_marker6(ring, 7);
1039
1040 set_blit_scissor(batch, ring);
1041
1042 if (batch->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
1043 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
1044
1045 if (!rsc->stencil || (batch->resolve & FD_BUFFER_DEPTH)) {
1046 emit_resolve_blit(batch, ring,
1047 gmem->zsbuf_base[0], pfb->zsbuf,
1048 FD_BUFFER_DEPTH);
1049 }
1050 if (rsc->stencil && (batch->resolve & FD_BUFFER_STENCIL)) {
1051 emit_resolve_blit(batch, ring,
1052 gmem->zsbuf_base[1], pfb->zsbuf,
1053 FD_BUFFER_STENCIL);
1054 }
1055 }
1056
1057 if (batch->resolve & FD_BUFFER_COLOR) {
1058 unsigned i;
1059 for (i = 0; i < pfb->nr_cbufs; i++) {
1060 if (!pfb->cbufs[i])
1061 continue;
1062 if (!(batch->resolve & (PIPE_CLEAR_COLOR0 << i)))
1063 continue;
1064 emit_resolve_blit(batch, ring, gmem->cbuf_base[i], pfb->cbufs[i],
1065 FD_BUFFER_COLOR);
1066 }
1067 }
1068 }
1069
1070 static void
1071 fd6_emit_tile_gmem2mem(struct fd_batch *batch, struct fd_tile *tile)
1072 {
1073 fd6_emit_ib(batch->gmem, batch->tile_fini);
1074 }
1075
1076 static void
1077 fd6_emit_tile_fini(struct fd_batch *batch)
1078 {
1079 struct fd_ringbuffer *ring = batch->gmem;
1080
1081 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_CNTL, 1);
1082 OUT_RING(ring, A6XX_GRAS_LRZ_CNTL_ENABLE | A6XX_GRAS_LRZ_CNTL_UNK3);
1083
1084 fd6_emit_lrz_flush(ring);
1085
1086 fd6_event_write(batch, ring, CACHE_FLUSH_TS, true);
1087 }
1088
1089 static void
1090 fd6_emit_sysmem_prep(struct fd_batch *batch)
1091 {
1092 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
1093 struct fd_ringbuffer *ring = batch->gmem;
1094
1095 fd6_emit_restore(batch, ring);
1096
1097 fd6_emit_lrz_flush(ring);
1098
1099 emit_marker6(ring, 7);
1100 OUT_PKT7(ring, CP_SET_MARKER, 1);
1101 OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(RM6_BYPASS) | 0x10); /* | 0x10 ? */
1102 emit_marker6(ring, 7);
1103
1104 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1105 OUT_RING(ring, 0x0);
1106
1107 fd6_event_write(batch, ring, PC_CCU_INVALIDATE_COLOR, false);
1108 fd6_cache_inv(batch, ring);
1109
1110 #if 0
1111 OUT_PKT4(ring, REG_A6XX_PC_POWER_CNTL, 1);
1112 OUT_RING(ring, 0x00000003); /* PC_POWER_CNTL */
1113 #endif
1114
1115 #if 0
1116 OUT_PKT4(ring, REG_A6XX_VFD_POWER_CNTL, 1);
1117 OUT_RING(ring, 0x00000003); /* VFD_POWER_CNTL */
1118 #endif
1119
1120 /* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */
1121 fd_wfi(batch, ring);
1122 OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
1123 OUT_RING(ring, 0x10000000); /* RB_CCU_CNTL */
1124
1125 set_scissor(ring, 0, 0, pfb->width - 1, pfb->height - 1);
1126
1127 set_window_offset(ring, 0, 0);
1128
1129 set_bin_size(ring, 0, 0, 0xc00000); /* 0xc00000 = BYPASS? */
1130
1131 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
1132 OUT_RING(ring, 0x1);
1133
1134 patch_draws(batch, IGNORE_VISIBILITY);
1135
1136 emit_zs(ring, pfb->zsbuf, NULL);
1137 emit_mrt(ring, pfb, NULL);
1138 emit_msaa(ring, pfb->samples);
1139
1140 update_render_cntl(batch, pfb, false);
1141 }
1142
1143 static void
1144 fd6_emit_sysmem_fini(struct fd_batch *batch)
1145 {
1146 struct fd_ringbuffer *ring = batch->gmem;
1147
1148 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1149 OUT_RING(ring, 0x0);
1150
1151 fd6_emit_lrz_flush(ring);
1152
1153 fd6_event_write(batch, ring, UNK_1D, true);
1154 }
1155
1156 void
1157 fd6_gmem_init(struct pipe_context *pctx)
1158 {
1159 struct fd_context *ctx = fd_context(pctx);
1160
1161 ctx->emit_tile_init = fd6_emit_tile_init;
1162 ctx->emit_tile_prep = fd6_emit_tile_prep;
1163 ctx->emit_tile_mem2gmem = fd6_emit_tile_mem2gmem;
1164 ctx->emit_tile_renderprep = fd6_emit_tile_renderprep;
1165 ctx->emit_tile_gmem2mem = fd6_emit_tile_gmem2mem;
1166 ctx->emit_tile_fini = fd6_emit_tile_fini;
1167 ctx->emit_sysmem_prep = fd6_emit_sysmem_prep;
1168 ctx->emit_sysmem_fini = fd6_emit_sysmem_fini;
1169 }