src/gallium/drivers/freedreno/a6xx/fd6_gmem.c

   1 /*
   2  * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
   3  * Copyright © 2018 Google, Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  22  * SOFTWARE.
  23  *
  24  * Authors:
  25  *    Rob Clark <robclark@freedesktop.org>
  26  */
  27
  28 #include <stdio.h>
  29
  30 #include "pipe/p_state.h"
  31 #include "util/u_string.h"
  32 #include "util/u_memory.h"
  33 #include "util/u_inlines.h"
  34 #include "util/u_format.h"
  35
  36 #include "freedreno_draw.h"
  37 #include "freedreno_state.h"
  38 #include "freedreno_resource.h"
  39
  40 #include "fd6_gmem.h"
  41 #include "fd6_context.h"
  42 #include "fd6_draw.h"
  43 #include "fd6_emit.h"
  44 #include "fd6_program.h"
  45 #include "fd6_format.h"
  46 #include "fd6_zsa.h"
  47
  48 static void
  49 emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
  50                 struct pipe_surface **bufs, struct fd_gmem_stateobj *gmem)
  51 {
  52         enum a6xx_tile_mode tile_mode;
  53         unsigned srgb_cntl = 0;
  54         unsigned i;
  55
  56         for (i = 0; i < nr_bufs; i++) {
  57                 enum a6xx_color_fmt format = 0;
  58                 enum a3xx_color_swap swap = WZYX;
  59                 bool sint = false, uint = false;
  60                 struct fd_resource *rsc = NULL;
  61                 struct fd_resource_slice *slice = NULL;
  62                 uint32_t stride = 0;
  63                 uint32_t offset = 0;
  64
  65                 if (gmem) {
  66                         tile_mode = TILE6_2;
  67                 } else {
  68                         tile_mode = TILE6_LINEAR;
  69                 }
  70
  71                 if (!bufs[i])
  72                         continue;
  73
  74                 struct pipe_surface *psurf = bufs[i];
  75                 enum pipe_format pformat = psurf->format;
  76                 rsc = fd_resource(psurf->texture);
  77                 if (!rsc->bo)
  78                         continue;
  79
  80                 uint32_t base = gmem ? gmem->cbuf_base[i] : 0;
  81                 slice = fd_resource_slice(rsc, psurf->u.tex.level);
  82                 format = fd6_pipe2color(pformat);
  83                 swap = fd6_pipe2swap(pformat);
  84                 sint = util_format_is_pure_sint(pformat);
  85                 uint = util_format_is_pure_uint(pformat);
  86
  87                 if (util_format_is_srgb(pformat))
  88                         srgb_cntl |= (1 << i);
  89
  90                 offset = fd_resource_offset(rsc, psurf->u.tex.level,
  91                                                                         psurf->u.tex.first_layer);
  92
  93                 stride = slice->pitch * rsc->cpp;
  94
  95                 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
  96                 debug_assert((offset + slice->size0) <= fd_bo_size(rsc->bo));
  97
  98                 OUT_PKT4(ring, REG_A6XX_RB_MRT_BUF_INFO(i), 6);
  99                 OUT_RING(ring, A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format) |
 100                                 A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(rsc->tile_mode) |
 101                                 A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(swap));
 102                 OUT_RING(ring, A6XX_RB_MRT_PITCH(stride));
 103                 OUT_RING(ring, A6XX_RB_MRT_ARRAY_PITCH(slice->size0));
 104                 OUT_RELOCW(ring, rsc->bo, offset, 0, 0);        /* BASE_LO/HI */
 105                 OUT_RING(ring, base);                   /* RB_MRT[i].BASE_GMEM */
 106                 OUT_PKT4(ring, REG_A6XX_SP_FS_MRT_REG(i), 1);
 107                 OUT_RING(ring, A6XX_SP_FS_MRT_REG_COLOR_FORMAT(format) |
 108                                 COND(sint, A6XX_SP_FS_MRT_REG_COLOR_SINT) |
 109                                 COND(uint, A6XX_SP_FS_MRT_REG_COLOR_UINT));
 110
 111 #if 0
 112                 /* when we support UBWC, these would be the system memory
 113                  * addr/pitch/etc:
 114                  */
 115                 OUT_PKT4(ring, REG_A6XX_RB_MRT_FLAG_BUFFER(i), 4);
 116                 OUT_RING(ring, 0x00000000);    /* RB_MRT_FLAG_BUFFER[i].ADDR_LO */
 117                 OUT_RING(ring, 0x00000000);    /* RB_MRT_FLAG_BUFFER[i].ADDR_HI */
 118                 OUT_RING(ring, A6XX_RB_MRT_FLAG_BUFFER_PITCH(0));
 119                 OUT_RING(ring, A6XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(0));
 120 #endif
 121         }
 122
 123         OUT_PKT4(ring, REG_A6XX_RB_SRGB_CNTL, 1);
 124         OUT_RING(ring, srgb_cntl);
 125
 126         OUT_PKT4(ring, REG_A6XX_SP_SRGB_CNTL, 1);
 127         OUT_RING(ring, srgb_cntl);
 128 }
 129
 130 static void
 131 emit_zs(struct fd_ringbuffer *ring, struct pipe_surface *zsbuf,
 132                 struct fd_gmem_stateobj *gmem)
 133 {
 134         if (zsbuf) {
 135                 struct fd_resource *rsc = fd_resource(zsbuf->texture);
 136                 enum a6xx_depth_format fmt = fd6_pipe2depth(zsbuf->format);
 137                 struct fd_resource_slice *slice = fd_resource_slice(rsc, 0);
 138                 uint32_t stride = slice->pitch * rsc->cpp;
 139                 uint32_t size = slice->size0;
 140                 uint32_t base = gmem ? gmem->zsbuf_base[0] : 0;
 141
 142                 OUT_PKT4(ring, REG_A6XX_RB_DEPTH_BUFFER_INFO, 6);
 143                 OUT_RING(ring, A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(fmt));
 144                 OUT_RING(ring, A6XX_RB_DEPTH_BUFFER_PITCH(stride));
 145                 OUT_RING(ring, A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(size));
 146                 OUT_RELOCW(ring, rsc->bo, 0, 0, 0);  /* RB_DEPTH_BUFFER_BASE_LO/HI */
 147                 OUT_RING(ring, base); /* RB_DEPTH_BUFFER_BASE_GMEM */
 148
 149                 OUT_PKT4(ring, REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO, 1);
 150                 OUT_RING(ring, A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(fmt));
 151
 152                 OUT_PKT4(ring, REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO, 3);
 153                 OUT_RING(ring, 0x00000000);    /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
 154                 OUT_RING(ring, 0x00000000);    /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
 155                 OUT_RING(ring, 0x00000000);    /* RB_DEPTH_FLAG_BUFFER_PITCH */
 156
 157                 if (rsc->lrz) {
 158                         OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO, 5);
 159                         OUT_RELOCW(ring, rsc->lrz, 0x1000, 0, 0);
 160                         OUT_RING(ring, A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH(rsc->lrz_pitch));
 161                         OUT_RELOCW(ring, rsc->lrz, 0, 0, 0); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO/HI */
 162                 } else {
 163                         OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO, 5);
 164                         OUT_RING(ring, 0x00000000);
 165                         OUT_RING(ring, 0x00000000);
 166                         OUT_RING(ring, 0x00000000);     /* GRAS_LRZ_BUFFER_PITCH */
 167                         OUT_RING(ring, 0x00000000);     /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO */
 168                         OUT_RING(ring, 0x00000000);
 169                 }
 170
 171                 if (rsc->stencil) {
 172                         struct fd_resource_slice *slice = fd_resource_slice(rsc->stencil, 0);
 173                         stride = slice->pitch * rsc->cpp;
 174                         size = slice->size0;
 175                         uint32_t base = gmem ? gmem->zsbuf_base[1] : 0;
 176
 177                         OUT_PKT4(ring, REG_A6XX_RB_STENCIL_INFO, 6);
 178                         OUT_RING(ring, A6XX_RB_STENCIL_INFO_SEPARATE_STENCIL);
 179                         OUT_RING(ring, A6XX_RB_STENCIL_BUFFER_PITCH(stride));
 180                         OUT_RING(ring, A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(size));
 181                         OUT_RELOCW(ring, rsc->stencil->bo, 0, 0, 0);  /* RB_STENCIL_BASE_LO/HI */
 182                         OUT_RING(ring, base);  /* RB_STENCIL_BASE_LO */
 183                 } else {
 184                         OUT_PKT4(ring, REG_A6XX_RB_STENCIL_INFO, 1);
 185                         OUT_RING(ring, 0x00000000);     /* RB_STENCIL_INFO */
 186                 }
 187         } else {
 188                 OUT_PKT4(ring, REG_A6XX_RB_DEPTH_BUFFER_INFO, 6);
 189                 OUT_RING(ring, A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH6_NONE));
 190                 OUT_RING(ring, 0x00000000);    /* RB_DEPTH_BUFFER_PITCH */
 191                 OUT_RING(ring, 0x00000000);    /* RB_DEPTH_BUFFER_ARRAY_PITCH */
 192                 OUT_RING(ring, 0x00000000);    /* RB_DEPTH_BUFFER_BASE_LO */
 193                 OUT_RING(ring, 0x00000000);    /* RB_DEPTH_BUFFER_BASE_HI */
 194                 OUT_RING(ring, 0x00000000);    /* RB_DEPTH_BUFFER_BASE_GMEM */
 195
 196                 OUT_PKT4(ring, REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO, 1);
 197                 OUT_RING(ring, A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH6_NONE));
 198
 199                 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO, 5);
 200                 OUT_RING(ring, 0x00000000);    /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
 201                 OUT_RING(ring, 0x00000000);    /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
 202                 OUT_RING(ring, 0x00000000);    /* GRAS_LRZ_BUFFER_PITCH */
 203                 OUT_RING(ring, 0x00000000);    /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO */
 204                 OUT_RING(ring, 0x00000000);    /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI */
 205
 206                 OUT_PKT4(ring, REG_A6XX_RB_STENCIL_INFO, 1);
 207                 OUT_RING(ring, 0x00000000);     /* RB_STENCIL_INFO */
 208         }
 209 }
 210
 211 static bool
 212 use_hw_binning(struct fd_batch *batch)
 213 {
 214         return false;
 215 }
 216
 217 static void
 218 patch_draws(struct fd_batch *batch, enum pc_di_vis_cull_mode vismode)
 219 {
 220         unsigned i;
 221         for (i = 0; i < fd_patch_num_elements(&batch->draw_patches); i++) {
 222                 struct fd_cs_patch *patch = fd_patch_element(&batch->draw_patches, i);
 223                 *patch->cs = patch->val | DRAW4(0, 0, 0, vismode);
 224         }
 225         util_dynarray_resize(&batch->draw_patches, 0);
 226 }
 227
 228 static void
 229 patch_gmem_bases(struct fd_batch *batch)
 230 {
 231         struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
 232         unsigned i;
 233
 234         for (i = 0; i < fd_patch_num_elements(&batch->gmem_patches); i++) {
 235                 struct fd_cs_patch *patch = fd_patch_element(&batch->gmem_patches, i);
 236                 if (patch->val < MAX_RENDER_TARGETS)
 237                         *patch->cs = gmem->cbuf_base[patch->val];
 238                 else
 239                         *patch->cs = gmem->zsbuf_base[0];
 240         }
 241         util_dynarray_resize(&batch->gmem_patches, 0);
 242 }
 243
 244 static void
 245 update_vsc_pipe(struct fd_batch *batch)
 246 {
 247         struct fd_context *ctx = batch->ctx;
 248         struct fd6_context *fd6_ctx = fd6_context(ctx);
 249         struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
 250         struct fd_ringbuffer *ring = batch->gmem;
 251         int i;
 252
 253         OUT_PKT4(ring, REG_A6XX_VSC_BIN_SIZE, 3);
 254         OUT_RING(ring, A6XX_VSC_BIN_SIZE_WIDTH(gmem->bin_w) |
 255                         A6XX_VSC_BIN_SIZE_HEIGHT(gmem->bin_h));
 256         OUT_RELOCW(ring, fd6_ctx->vsc_size_mem, 0, 0, 0); /* VSC_SIZE_ADDRESS_LO/HI */
 257
 258 #if 0
 259         OUT_PKT4(ring, REG_A6XX_UNKNOWN_0BC5, 2);
 260         OUT_RING(ring, 0x00000000);   /* UNKNOWN_0BC5 */
 261         OUT_RING(ring, 0x00000000);   /* UNKNOWN_0BC6 */
 262 #endif
 263
 264         OUT_PKT4(ring, REG_A6XX_VSC_PIPE_CONFIG_REG(0), 16);
 265         for (i = 0; i < 16; i++) {
 266                 struct fd_vsc_pipe *pipe = &ctx->vsc_pipe[i];
 267                 OUT_RING(ring, A6XX_VSC_PIPE_CONFIG_REG_X(pipe->x) |
 268                                 A6XX_VSC_PIPE_CONFIG_REG_Y(pipe->y) |
 269                                 A6XX_VSC_PIPE_CONFIG_REG_W(pipe->w) |
 270                                 A6XX_VSC_PIPE_CONFIG_REG_H(pipe->h));
 271         }
 272
 273 #if 0
 274         OUT_PKT4(ring, REG_A6XX_VSC_PIPE_DATA_ADDRESS_LO(0), 32);
 275         for (i = 0; i < 16; i++) {
 276                 struct fd_vsc_pipe *pipe = &ctx->vsc_pipe[i];
 277                 if (!pipe->bo) {
 278                         pipe->bo = fd_bo_new(ctx->dev, 0x20000,
 279                                         DRM_FREEDRENO_GEM_TYPE_KMEM);
 280                 }
 281                 OUT_RELOCW(ring, pipe->bo, 0, 0, 0);     /* VSC_PIPE_DATA_ADDRESS[i].LO/HI */
 282         }
 283 #endif
 284
 285 #if 0
 286         OUT_PKT4(ring, REG_A6XX_VSC_PIPE_DATA_LENGTH_REG(0), 16);
 287         for (i = 0; i < 16; i++) {
 288                 struct fd_vsc_pipe *pipe = &ctx->vsc_pipe[i];
 289                 OUT_RING(ring, fd_bo_size(pipe->bo) - 32); /* VSC_PIPE_DATA_LENGTH[i] */
 290         }
 291 #endif
 292 }
 293
 294 static void
 295 set_scissor(struct fd_ringbuffer *ring, uint32_t x1, uint32_t y1, uint32_t x2, uint32_t y2)
 296 {
 297         OUT_PKT4(ring, REG_A6XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
 298         OUT_RING(ring, A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X(x1) |
 299                          A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(y1));
 300         OUT_RING(ring, A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X(x2) |
 301                          A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(y2));
 302
 303         OUT_PKT4(ring, REG_A6XX_GRAS_RESOLVE_CNTL_1, 2);
 304         OUT_RING(ring, A6XX_GRAS_RESOLVE_CNTL_1_X(x1) |
 305                          A6XX_GRAS_RESOLVE_CNTL_1_Y(y1));
 306         OUT_RING(ring, A6XX_GRAS_RESOLVE_CNTL_2_X(x2) |
 307                          A6XX_GRAS_RESOLVE_CNTL_2_Y(y2));
 308 }
 309
 310 static void
 311 emit_binning_pass(struct fd_batch *batch)
 312 {
 313         struct fd_context *ctx = batch->ctx;
 314         struct fd_ringbuffer *ring = batch->gmem;
 315         struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
 316
 317         uint32_t x1 = gmem->minx;
 318         uint32_t y1 = gmem->miny;
 319         uint32_t x2 = gmem->minx + gmem->width - 1;
 320         uint32_t y2 = gmem->miny + gmem->height - 1;
 321
 322         emit_marker6(ring, 7);
 323         OUT_PKT7(ring, CP_SET_MARKER, 1);
 324         OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(RM6_BINNING) | 0x10); /* | 0x10 ? */
 325         emit_marker6(ring, 7);
 326
 327 #if 0
 328         OUT_PKT4(ring, REG_A6XX_RB_CNTL, 1);
 329         OUT_RING(ring, A6XX_RB_CNTL_WIDTH(gmem->bin_w) |
 330                         A6XX_RB_CNTL_HEIGHT(gmem->bin_h));
 331 #endif
 332
 333         set_scissor(ring, x1, y1, x2, y2);
 334
 335         update_vsc_pipe(batch);
 336
 337 #if 0
 338         OUT_PKT4(ring, REG_A6XX_VPC_MODE_CNTL, 1);
 339         OUT_RING(ring, A6XX_VPC_MODE_CNTL_BINNING_PASS);
 340 #endif
 341
 342         OUT_PKT7(ring, CP_EVENT_WRITE, 1);
 343         OUT_RING(ring, UNK_2C);
 344
 345         OUT_PKT4(ring, REG_A6XX_RB_WINDOW_OFFSET, 1);
 346         OUT_RING(ring, A6XX_RB_WINDOW_OFFSET_X(0) |
 347                         A6XX_RB_WINDOW_OFFSET_Y(0));
 348
 349         /* emit IB to binning drawcmds: */
 350         ctx->emit_ib(ring, batch->binning);
 351
 352         fd_reset_wfi(batch);
 353
 354         OUT_PKT7(ring, CP_EVENT_WRITE, 1);
 355         OUT_RING(ring, UNK_2D);
 356
 357         OUT_PKT7(ring, CP_EVENT_WRITE, 4);
 358         OUT_RING(ring, CACHE_FLUSH_TS);
 359         OUT_RELOCW(ring, fd6_context(ctx)->blit_mem, 0, 0, 0);  /* ADDR_LO/HI */
 360         OUT_RING(ring, 0x00000000);
 361
 362         // TODO CP_COND_WRITE's for all the vsc buffers (check for overflow??)
 363
 364         fd_wfi(batch, ring);
 365
 366 #if 0
 367         OUT_PKT4(ring, REG_A6XX_VPC_MODE_CNTL, 1);
 368         OUT_RING(ring, 0x0);
 369 #endif
 370 }
 371
 372 static void
 373 disable_msaa(struct fd_ringbuffer *ring)
 374 {
 375         // TODO MSAA
 376         OUT_PKT4(ring, REG_A6XX_SP_TP_RAS_MSAA_CNTL, 2);
 377         OUT_RING(ring, A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(MSAA_ONE));
 378         OUT_RING(ring, A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(MSAA_ONE) |
 379                          A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE);
 380
 381         OUT_PKT4(ring, REG_A6XX_GRAS_RAS_MSAA_CNTL, 2);
 382         OUT_RING(ring, A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(MSAA_ONE));
 383         OUT_RING(ring, A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(MSAA_ONE) |
 384                          A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE);
 385
 386         OUT_PKT4(ring, REG_A6XX_RB_RAS_MSAA_CNTL, 2);
 387         OUT_RING(ring, A6XX_RB_RAS_MSAA_CNTL_SAMPLES(MSAA_ONE));
 388         OUT_RING(ring, A6XX_RB_DEST_MSAA_CNTL_SAMPLES(MSAA_ONE) |
 389                          A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE);
 390 }
 391
 392 static void
 393 set_bin_size(struct fd_ringbuffer *ring, uint32_t w, uint32_t h, uint32_t flag)
 394 {
 395         OUT_PKT4(ring, REG_A6XX_GRAS_BIN_CONTROL, 1);
 396         OUT_RING(ring, A6XX_GRAS_BIN_CONTROL_BINW(w) |
 397                          A6XX_GRAS_BIN_CONTROL_BINH(h) | flag);
 398
 399         OUT_PKT4(ring, REG_A6XX_RB_BIN_CONTROL, 1);
 400         OUT_RING(ring, A6XX_RB_BIN_CONTROL_BINW(w) |
 401                          A6XX_RB_BIN_CONTROL_BINH(h) | flag);
 402
 403         /* no flag for X3_BIN_SIZE... */
 404         OUT_PKT4(ring, REG_A6XX_RB_BIN_CONTROL2, 1);
 405         OUT_RING(ring, A6XX_RB_BIN_CONTROL2_BINW(w) |
 406                          A6XX_RB_BIN_CONTROL2_BINH(h));
 407 }
 408
 409 /* before first tile */
 410 static void
 411 fd6_emit_tile_init(struct fd_batch *batch)
 412 {
 413         struct fd_context *ctx = batch->ctx;
 414         struct fd_ringbuffer *ring = batch->gmem;
 415         struct pipe_framebuffer_state *pfb = &batch->framebuffer;
 416         struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
 417
 418         fd6_emit_restore(batch, ring);
 419
 420         if (batch->lrz_clear)
 421                 ctx->emit_ib(ring, batch->lrz_clear);
 422
 423         fd6_emit_lrz_flush(ring);
 424
 425         OUT_PKT7(ring, CP_EVENT_WRITE, 1);
 426         OUT_RING(ring, 0x31); /* vertex cache invalidate? */
 427
 428 #if 0
 429         OUT_PKT4(ring, REG_A6XX_GRAS_CL_CNTL, 1);
 430         OUT_RING(ring, 0x00000080);   /* GRAS_CL_CNTL */
 431 #endif
 432
 433         OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
 434         OUT_RING(ring, 0x0);
 435
 436 #if 0
 437         OUT_PKT4(ring, REG_A6XX_PC_POWER_CNTL, 1);
 438         OUT_RING(ring, 0x00000003);   /* PC_POWER_CNTL */
 439 #endif
 440
 441 #if 0
 442         OUT_PKT4(ring, REG_A6XX_VFD_POWER_CNTL, 1);
 443         OUT_RING(ring, 0x00000003);   /* VFD_POWER_CNTL */
 444 #endif
 445
 446         /* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */
 447         fd_wfi(batch, ring);
 448         OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
 449         OUT_RING(ring, 0x7c400004);   /* RB_CCU_CNTL */
 450
 451         DBG("emit_mrt");
 452         emit_zs(ring, pfb->zsbuf, &ctx->gmem);
 453         emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, &ctx->gmem);
 454
 455         patch_gmem_bases(batch);
 456
 457         set_bin_size(ring, gmem->bin_w, gmem->bin_h, 0x6000000);
 458
 459         disable_msaa(ring);
 460
 461         if (use_hw_binning(batch)) {
 462                 emit_binning_pass(batch);
 463                 fd6_emit_lrz_flush(ring);
 464                 patch_draws(batch, USE_VISIBILITY);
 465         } else {
 466                 patch_draws(batch, IGNORE_VISIBILITY);
 467         }
 468 }
 469
 470 static void
 471 set_window_offset(struct fd_ringbuffer *ring, uint32_t x1, uint32_t y1)
 472 {
 473         OUT_PKT4(ring, REG_A6XX_RB_WINDOW_OFFSET, 1);
 474         OUT_RING(ring, A6XX_RB_WINDOW_OFFSET_X(x1) |
 475                         A6XX_RB_WINDOW_OFFSET_Y(y1));
 476
 477         OUT_PKT4(ring, REG_A6XX_RB_WINDOW_OFFSET2, 1);
 478         OUT_RING(ring, A6XX_RB_WINDOW_OFFSET2_X(x1) |
 479                         A6XX_RB_WINDOW_OFFSET2_Y(y1));
 480
 481         OUT_PKT4(ring, REG_A6XX_SP_WINDOW_OFFSET, 1);
 482         OUT_RING(ring, A6XX_SP_WINDOW_OFFSET_X(x1) |
 483                         A6XX_SP_WINDOW_OFFSET_Y(y1));
 484
 485         OUT_PKT4(ring, REG_A6XX_SP_TP_WINDOW_OFFSET, 1);
 486         OUT_RING(ring, A6XX_SP_TP_WINDOW_OFFSET_X(x1) |
 487                         A6XX_SP_TP_WINDOW_OFFSET_Y(y1));
 488 }
 489
 490 /* before mem2gmem */
 491 static void
 492 fd6_emit_tile_prep(struct fd_batch *batch, struct fd_tile *tile)
 493 {
 494         struct fd_context *ctx = batch->ctx;
 495         struct fd6_context *fd6_ctx = fd6_context(ctx);
 496         struct fd_ringbuffer *ring = batch->gmem;
 497
 498         emit_marker6(ring, 7);
 499         OUT_PKT7(ring, CP_SET_MARKER, 1);
 500         OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(RM6_GMEM) | 0x10); /* | 0x10 ? */
 501         emit_marker6(ring, 7);
 502
 503         uint32_t x1 = tile->xoff;
 504         uint32_t y1 = tile->yoff;
 505         uint32_t x2 = tile->xoff + tile->bin_w - 1;
 506         uint32_t y2 = tile->yoff + tile->bin_h - 1;
 507
 508         set_scissor(ring, x1, y1, x2, y2);
 509
 510         set_window_offset(ring, x1, y1);
 511
 512         OUT_PKT4(ring, REG_A6XX_VPC_SO_OVERRIDE, 1);
 513         OUT_RING(ring, A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
 514
 515         if (use_hw_binning(batch)) {
 516                 struct fd_vsc_pipe *pipe = &ctx->vsc_pipe[tile->p];
 517
 518                 OUT_PKT7(ring, CP_WAIT_FOR_ME, 0);
 519
 520                 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
 521                 OUT_RING(ring, 0x0);
 522
 523                 OUT_PKT7(ring, CP_SET_BIN_DATA5, 5);
 524                 OUT_RING(ring, CP_SET_BIN_DATA5_0_VSC_SIZE(pipe->w * pipe->h) |
 525                                 CP_SET_BIN_DATA5_0_VSC_N(tile->n));
 526                 OUT_RELOC(ring, pipe->bo, 0, 0, 0);      /* VSC_PIPE[p].DATA_ADDRESS */
 527                 OUT_RELOC(ring, fd6_ctx->vsc_size_mem,   /* VSC_SIZE_ADDRESS + (p * 4) */
 528                                 (tile->p * 4), 0, 0);
 529         } else {
 530                 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
 531                 OUT_RING(ring, 0x1);
 532         }
 533
 534         OUT_PKT7(ring, CP_SET_MODE, 1);
 535         OUT_RING(ring, 0x0);
 536 }
 537
 538 static void
 539 set_blit_scissor(struct fd_batch *batch)
 540 {
 541         struct fd_ringbuffer *ring = batch->gmem;
 542         struct pipe_scissor_state blit_scissor;
 543         struct pipe_framebuffer_state *pfb = &batch->framebuffer;
 544
 545         blit_scissor.minx = batch->max_scissor.minx;
 546         blit_scissor.miny = batch->max_scissor.miny;
 547         blit_scissor.maxx = MIN2(pfb->width - 1, batch->max_scissor.maxx);
 548         blit_scissor.maxy = MIN2(pfb->height - 1, batch->max_scissor.maxy);
 549
 550         OUT_PKT4(ring, REG_A6XX_RB_BLIT_SCISSOR_TL, 2);
 551         OUT_RING(ring,
 552                          A6XX_RB_BLIT_SCISSOR_TL_X(blit_scissor.minx) |
 553                          A6XX_RB_BLIT_SCISSOR_TL_Y(blit_scissor.miny));
 554         OUT_RING(ring,
 555                          A6XX_RB_BLIT_SCISSOR_BR_X(blit_scissor.maxx - 1) |
 556                          A6XX_RB_BLIT_SCISSOR_BR_Y(blit_scissor.maxy - 1));
 557 }
 558
 559 static void
 560 emit_blit(struct fd_batch *batch, uint32_t base,
 561                   struct pipe_surface *psurf,
 562                   struct fd_resource *rsc)
 563 {
 564         struct fd_ringbuffer *ring = batch->gmem;
 565         struct fd_resource_slice *slice;
 566         uint32_t offset;
 567
 568         slice = fd_resource_slice(rsc, psurf->u.tex.level);
 569         offset = fd_resource_offset(rsc, psurf->u.tex.level,
 570                         psurf->u.tex.first_layer);
 571
 572         debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
 573
 574         enum pipe_format pfmt = psurf->format;
 575         enum a6xx_color_fmt format = fd6_pipe2color(pfmt);
 576         uint32_t stride = slice->pitch * rsc->cpp;
 577         uint32_t size = slice->size0;
 578         enum a3xx_color_swap swap = fd6_pipe2swap(pfmt);
 579
 580         // TODO: tile mode
 581         // bool tiled;
 582         // tiled = rsc->tile_mode &&
 583         //   !fd_resource_level_linear(psurf->texture, psurf->u.tex.level);
 584
 585         OUT_PKT4(ring, REG_A6XX_RB_BLIT_DST_INFO, 5);
 586         OUT_RING(ring,
 587                          A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR) |
 588                          A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(format) |
 589                          A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(swap));
 590         OUT_RELOCW(ring, rsc->bo, offset, 0, 0);  /* RB_BLIT_DST_LO/HI */
 591         OUT_RING(ring, A6XX_RB_BLIT_DST_PITCH(stride));
 592         OUT_RING(ring, A6XX_RB_BLIT_DST_ARRAY_PITCH(size));
 593
 594         OUT_PKT4(ring, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
 595         OUT_RING(ring, base);
 596
 597         fd6_emit_blit(batch->ctx, ring);
 598 }
 599
 600 static void
 601 emit_restore_blit(struct fd_batch *batch, uint32_t base,
 602                                   struct pipe_surface *psurf,
 603                                   struct fd_resource *rsc,
 604                                   unsigned buffer)
 605 {
 606         struct fd_ringbuffer *ring = batch->gmem;
 607         uint32_t info = 0;
 608
 609         switch (buffer) {
 610         case FD_BUFFER_COLOR:
 611                 info |= A6XX_RB_BLIT_INFO_UNK0;
 612                 break;
 613         case FD_BUFFER_STENCIL:
 614                 info |= A6XX_RB_BLIT_INFO_UNK0;
 615                 break;
 616         case FD_BUFFER_DEPTH:
 617                 info |= A6XX_RB_BLIT_INFO_DEPTH | A6XX_RB_BLIT_INFO_UNK0;
 618                 break;
 619         }
 620
 621         if (util_format_is_pure_integer(psurf->format))
 622                 info |= A6XX_RB_BLIT_INFO_INTEGER;
 623
 624         OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
 625         OUT_RING(ring, info | A6XX_RB_BLIT_INFO_GMEM);
 626
 627         emit_blit(batch, base, psurf, rsc);
 628 }
 629
 630 /*
 631  * transfer from system memory to gmem
 632  */
 633 static void
 634 fd6_emit_tile_mem2gmem(struct fd_batch *batch, struct fd_tile *tile)
 635 {
 636         struct fd_context *ctx = batch->ctx;
 637         struct fd_gmem_stateobj *gmem = &ctx->gmem;
 638         struct pipe_framebuffer_state *pfb = &batch->framebuffer;
 639
 640         set_blit_scissor(batch);
 641
 642         if (fd_gmem_needs_restore(batch, tile, FD_BUFFER_COLOR)) {
 643                 unsigned i;
 644                 for (i = 0; i < pfb->nr_cbufs; i++) {
 645                         if (!pfb->cbufs[i])
 646                                 continue;
 647                         if (!(batch->restore & (PIPE_CLEAR_COLOR0 << i)))
 648                                 continue;
 649                         emit_restore_blit(batch, gmem->cbuf_base[i], pfb->cbufs[i],
 650                                                           fd_resource(pfb->cbufs[i]->texture),
 651                                                           FD_BUFFER_COLOR);
 652                 }
 653         }
 654
 655         if (fd_gmem_needs_restore(batch, tile, FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
 656                 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
 657
 658                 if (!rsc->stencil || fd_gmem_needs_restore(batch, tile, FD_BUFFER_DEPTH)) {
 659                         emit_restore_blit(batch, gmem->zsbuf_base[0], pfb->zsbuf, rsc,
 660                                                           FD_BUFFER_DEPTH);
 661                 }
 662                 if (rsc->stencil && fd_gmem_needs_restore(batch, tile, FD_BUFFER_STENCIL)) {
 663                         emit_restore_blit(batch, gmem->zsbuf_base[1], pfb->zsbuf, rsc->stencil,
 664                                                           FD_BUFFER_STENCIL);
 665                 }
 666         }
 667 }
 668
 669 /* before IB to rendering cmds: */
 670 static void
 671 fd6_emit_tile_renderprep(struct fd_batch *batch, struct fd_tile *tile)
 672 {
 673 }
 674
 675 static void
 676 emit_resolve_blit(struct fd_batch *batch, uint32_t base,
 677                                   struct pipe_surface *psurf,
 678                                   struct fd_resource *rsc,
 679                                   unsigned buffer)
 680 {
 681         struct fd_ringbuffer *ring = batch->gmem;
 682         uint32_t info = 0;
 683
 684         if (!rsc->valid)
 685                 return;
 686
 687         switch (buffer) {
 688         case FD_BUFFER_COLOR:
 689                 break;
 690         case FD_BUFFER_STENCIL:
 691                 info |= A6XX_RB_BLIT_INFO_UNK0;
 692                 break;
 693         case FD_BUFFER_DEPTH:
 694                 info |= A6XX_RB_BLIT_INFO_DEPTH;
 695                 break;
 696         }
 697
 698         if (util_format_is_pure_integer(psurf->format))
 699                 info |= A6XX_RB_BLIT_INFO_INTEGER;
 700
 701         OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
 702         OUT_RING(ring, info);
 703
 704         emit_blit(batch, base, psurf, rsc);
 705 }
 706
 707 /*
 708  * transfer from gmem to system memory (ie. normal RAM)
 709  */
 710
 711 static void
 712 fd6_emit_tile_gmem2mem(struct fd_batch *batch, struct fd_tile *tile)
 713 {
 714         struct fd_context *ctx = batch->ctx;
 715         struct fd_gmem_stateobj *gmem = &ctx->gmem;
 716         struct pipe_framebuffer_state *pfb = &batch->framebuffer;
 717         struct fd_ringbuffer *ring = batch->gmem;
 718
 719         OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
 720         OUT_RING(ring, 0x0);
 721
 722         emit_marker6(ring, 7);
 723         OUT_PKT7(ring, CP_SET_MARKER, 1);
 724         OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE)); /*  | 0x10 ? */
 725         emit_marker6(ring, 7);
 726
 727         set_blit_scissor(batch);
 728
 729         if (batch->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
 730                 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
 731
 732                 if (!rsc->stencil || (batch->resolve & FD_BUFFER_DEPTH)) {
 733                         emit_resolve_blit(batch, gmem->zsbuf_base[0], pfb->zsbuf, rsc,
 734                                                           FD_BUFFER_DEPTH);
 735                 }
 736                 if (rsc->stencil && (batch->resolve & FD_BUFFER_STENCIL)) {
 737                         emit_resolve_blit(batch, gmem->zsbuf_base[1], pfb->zsbuf, rsc->stencil,
 738                                                           FD_BUFFER_STENCIL);
 739                 }
 740         }
 741
 742         if (batch->resolve & FD_BUFFER_COLOR) {
 743                 unsigned i;
 744                 for (i = 0; i < pfb->nr_cbufs; i++) {
 745                         if (!pfb->cbufs[i])
 746                                 continue;
 747                         if (!(batch->resolve & (PIPE_CLEAR_COLOR0 << i)))
 748                                 continue;
 749                         emit_resolve_blit(batch, gmem->cbuf_base[i], pfb->cbufs[i],
 750                                                           fd_resource(pfb->cbufs[i]->texture),
 751                                                           FD_BUFFER_COLOR);
 752                 }
 753         }
 754 }
 755
 756 static void
 757 fd6_emit_tile_fini(struct fd_batch *batch)
 758 {
 759         struct fd_ringbuffer *ring = batch->gmem;
 760
 761         fd6_emit_lrz_flush(ring);
 762
 763         fd6_cache_flush(batch, ring);
 764 }
 765
 766 static void
 767 fd6_emit_sysmem_prep(struct fd_batch *batch)
 768 {
 769         struct pipe_framebuffer_state *pfb = &batch->framebuffer;
 770         struct fd_ringbuffer *ring = batch->gmem;
 771
 772         fd6_emit_restore(batch, ring);
 773
 774         fd6_emit_lrz_flush(ring);
 775
 776         emit_marker6(ring, 7);
 777         OUT_PKT7(ring, CP_SET_MARKER, 1);
 778         OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(RM6_BYPASS) | 0x10); /* | 0x10 ? */
 779         emit_marker6(ring, 7);
 780
 781         OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
 782         OUT_RING(ring, 0x0);
 783
 784         OUT_PKT7(ring, CP_EVENT_WRITE, 1);
 785         OUT_RING(ring, PC_CCU_INVALIDATE_COLOR);
 786
 787         OUT_PKT7(ring, CP_EVENT_WRITE, 1);
 788         OUT_RING(ring, 0x31); /* vertex cache invalidate? */
 789
 790 #if 0
 791         OUT_PKT4(ring, REG_A6XX_PC_POWER_CNTL, 1);
 792         OUT_RING(ring, 0x00000003);   /* PC_POWER_CNTL */
 793 #endif
 794
 795 #if 0
 796         OUT_PKT4(ring, REG_A6XX_VFD_POWER_CNTL, 1);
 797         OUT_RING(ring, 0x00000003);   /* VFD_POWER_CNTL */
 798 #endif
 799
 800         /* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */
 801         fd_wfi(batch, ring);
 802         OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
 803         OUT_RING(ring, 0x10000000);   /* RB_CCU_CNTL */
 804
 805         set_scissor(ring, 0, 0, pfb->width - 1, pfb->height - 1);
 806
 807         set_window_offset(ring, 0, 0);
 808
 809         set_bin_size(ring, 0, 0, 0xc00000); /* 0xc00000 = BYPASS? */
 810
 811         OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
 812         OUT_RING(ring, 0x1);
 813
 814         patch_draws(batch, IGNORE_VISIBILITY);
 815
 816         emit_zs(ring, pfb->zsbuf, NULL);
 817         emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, NULL);
 818
 819         disable_msaa(ring);
 820 }
 821
 822 static void
 823 fd6_emit_sysmem_fini(struct fd_batch *batch)
 824 {
 825         struct fd6_context *fd6_ctx = fd6_context(batch->ctx);
 826         struct fd_ringbuffer *ring = batch->gmem;
 827
 828         OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
 829         OUT_RING(ring, 0x0);
 830
 831         fd6_emit_lrz_flush(ring);
 832
 833         OUT_PKT7(ring, CP_EVENT_WRITE, 4);
 834         OUT_RING(ring, UNK_1D);
 835         OUT_RELOCW(ring, fd6_ctx->blit_mem, 0, 0, 0);  /* ADDR_LO/HI */
 836         OUT_RING(ring, 0x00000000);
 837 }
 838
 839 void
 840 fd6_gmem_init(struct pipe_context *pctx)
 841 {
 842         struct fd_context *ctx = fd_context(pctx);
 843
 844         ctx->emit_tile_init = fd6_emit_tile_init;
 845         ctx->emit_tile_prep = fd6_emit_tile_prep;
 846         ctx->emit_tile_mem2gmem = fd6_emit_tile_mem2gmem;
 847         ctx->emit_tile_renderprep = fd6_emit_tile_renderprep;
 848         ctx->emit_tile_gmem2mem = fd6_emit_tile_gmem2mem;
 849         ctx->emit_tile_fini = fd6_emit_tile_fini;
 850         ctx->emit_sysmem_prep = fd6_emit_sysmem_prep;
 851         ctx->emit_sysmem_fini = fd6_emit_sysmem_fini;
 852 }