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freedreno/a6xx: Clear gmem buffers at flush time
[mesa.git] / src / gallium / drivers / freedreno / a6xx / fd6_gmem.c
1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 * Authors:
25 * Rob Clark <robclark@freedesktop.org>
26 */
27
28 #include <stdio.h>
29
30 #include "pipe/p_state.h"
31 #include "util/u_string.h"
32 #include "util/u_memory.h"
33 #include "util/u_inlines.h"
34 #include "util/u_format.h"
35
36 #include "freedreno_draw.h"
37 #include "freedreno_state.h"
38 #include "freedreno_resource.h"
39
40 #include "fd6_gmem.h"
41 #include "fd6_context.h"
42 #include "fd6_draw.h"
43 #include "fd6_emit.h"
44 #include "fd6_program.h"
45 #include "fd6_format.h"
46 #include "fd6_zsa.h"
47
48 /* some bits in common w/ a4xx: */
49 #include "a4xx/fd4_draw.h"
50
51 static void
52 emit_mrt(struct fd_ringbuffer *ring, struct pipe_framebuffer_state *pfb,
53 struct fd_gmem_stateobj *gmem)
54 {
55 unsigned char mrt_comp[A6XX_MAX_RENDER_TARGETS] = {0};
56 unsigned srgb_cntl = 0;
57 unsigned i;
58
59 for (i = 0; i < pfb->nr_cbufs; i++) {
60 enum a6xx_color_fmt format = 0;
61 enum a3xx_color_swap swap = WZYX;
62 bool sint = false, uint = false;
63 struct fd_resource *rsc = NULL;
64 struct fd_resource_slice *slice = NULL;
65 uint32_t stride = 0;
66 uint32_t offset = 0;
67
68 if (!pfb->cbufs[i])
69 continue;
70
71 mrt_comp[i] = 0xf;
72
73 struct pipe_surface *psurf = pfb->cbufs[i];
74 enum pipe_format pformat = psurf->format;
75 rsc = fd_resource(psurf->texture);
76 if (!rsc->bo)
77 continue;
78
79 uint32_t base = gmem ? gmem->cbuf_base[i] : 0;
80 slice = fd_resource_slice(rsc, psurf->u.tex.level);
81 format = fd6_pipe2color(pformat);
82 swap = fd6_pipe2swap(pformat);
83 sint = util_format_is_pure_sint(pformat);
84 uint = util_format_is_pure_uint(pformat);
85
86 if (util_format_is_srgb(pformat))
87 srgb_cntl |= (1 << i);
88
89 offset = fd_resource_offset(rsc, psurf->u.tex.level,
90 psurf->u.tex.first_layer);
91
92 stride = slice->pitch * rsc->cpp;
93
94 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
95 debug_assert((offset + slice->size0) <= fd_bo_size(rsc->bo));
96
97 OUT_PKT4(ring, REG_A6XX_RB_MRT_BUF_INFO(i), 6);
98 OUT_RING(ring, A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format) |
99 A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(rsc->tile_mode) |
100 A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(swap));
101 OUT_RING(ring, A6XX_RB_MRT_PITCH(stride));
102 OUT_RING(ring, A6XX_RB_MRT_ARRAY_PITCH(slice->size0));
103 OUT_RELOCW(ring, rsc->bo, offset, 0, 0); /* BASE_LO/HI */
104 OUT_RING(ring, base); /* RB_MRT[i].BASE_GMEM */
105 OUT_PKT4(ring, REG_A6XX_SP_FS_MRT_REG(i), 1);
106 OUT_RING(ring, A6XX_SP_FS_MRT_REG_COLOR_FORMAT(format) |
107 COND(sint, A6XX_SP_FS_MRT_REG_COLOR_SINT) |
108 COND(uint, A6XX_SP_FS_MRT_REG_COLOR_UINT));
109
110 #if 0
111 /* when we support UBWC, these would be the system memory
112 * addr/pitch/etc:
113 */
114 OUT_PKT4(ring, REG_A6XX_RB_MRT_FLAG_BUFFER(i), 4);
115 OUT_RING(ring, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_LO */
116 OUT_RING(ring, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_HI */
117 OUT_RING(ring, A6XX_RB_MRT_FLAG_BUFFER_PITCH(0));
118 OUT_RING(ring, A6XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(0));
119 #endif
120 }
121
122 OUT_PKT4(ring, REG_A6XX_RB_SRGB_CNTL, 1);
123 OUT_RING(ring, srgb_cntl);
124
125 OUT_PKT4(ring, REG_A6XX_SP_SRGB_CNTL, 1);
126 OUT_RING(ring, srgb_cntl);
127
128 OUT_PKT4(ring, REG_A6XX_RB_RENDER_COMPONENTS, 1);
129 OUT_RING(ring, A6XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
130 A6XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
131 A6XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
132 A6XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
133 A6XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
134 A6XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
135 A6XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
136 A6XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
137
138 OUT_PKT4(ring, REG_A6XX_SP_FS_RENDER_COMPONENTS, 1);
139 OUT_RING(ring,
140 A6XX_SP_FS_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
141 A6XX_SP_FS_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
142 A6XX_SP_FS_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
143 A6XX_SP_FS_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
144 A6XX_SP_FS_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
145 A6XX_SP_FS_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
146 A6XX_SP_FS_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
147 A6XX_SP_FS_RENDER_COMPONENTS_RT7(mrt_comp[7]));
148 }
149
150 static void
151 emit_zs(struct fd_ringbuffer *ring, struct pipe_surface *zsbuf,
152 struct fd_gmem_stateobj *gmem)
153 {
154 if (zsbuf) {
155 struct fd_resource *rsc = fd_resource(zsbuf->texture);
156 enum a6xx_depth_format fmt = fd6_pipe2depth(zsbuf->format);
157 struct fd_resource_slice *slice = fd_resource_slice(rsc, 0);
158 uint32_t stride = slice->pitch * rsc->cpp;
159 uint32_t size = slice->size0;
160 uint32_t base = gmem ? gmem->zsbuf_base[0] : 0;
161
162 OUT_PKT4(ring, REG_A6XX_RB_DEPTH_BUFFER_INFO, 6);
163 OUT_RING(ring, A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(fmt));
164 OUT_RING(ring, A6XX_RB_DEPTH_BUFFER_PITCH(stride));
165 OUT_RING(ring, A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(size));
166 OUT_RELOCW(ring, rsc->bo, 0, 0, 0); /* RB_DEPTH_BUFFER_BASE_LO/HI */
167 OUT_RING(ring, base); /* RB_DEPTH_BUFFER_BASE_GMEM */
168
169 OUT_PKT4(ring, REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO, 1);
170 OUT_RING(ring, A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(fmt));
171
172 OUT_PKT4(ring, REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO, 3);
173 OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
174 OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
175 OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_PITCH */
176
177 if (rsc->lrz) {
178 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO, 5);
179 OUT_RELOCW(ring, rsc->lrz, 0, 0, 0);
180 OUT_RING(ring, A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH(rsc->lrz_pitch));
181 //OUT_RELOCW(ring, rsc->lrz, 0, 0, 0); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO/HI */
182 // XXX a6xx seems to use a different buffer here.. not sure what for..
183 OUT_RING(ring, 0x00000000);
184 OUT_RING(ring, 0x00000000);
185 } else {
186 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO, 5);
187 OUT_RING(ring, 0x00000000);
188 OUT_RING(ring, 0x00000000);
189 OUT_RING(ring, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
190 OUT_RING(ring, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO */
191 OUT_RING(ring, 0x00000000);
192 }
193
194 if (rsc->stencil) {
195 struct fd_resource_slice *slice = fd_resource_slice(rsc->stencil, 0);
196 stride = slice->pitch * rsc->cpp;
197 size = slice->size0;
198 uint32_t base = gmem ? gmem->zsbuf_base[1] : 0;
199
200 OUT_PKT4(ring, REG_A6XX_RB_STENCIL_INFO, 6);
201 OUT_RING(ring, A6XX_RB_STENCIL_INFO_SEPARATE_STENCIL);
202 OUT_RING(ring, A6XX_RB_STENCIL_BUFFER_PITCH(stride));
203 OUT_RING(ring, A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(size));
204 OUT_RELOCW(ring, rsc->stencil->bo, 0, 0, 0); /* RB_STENCIL_BASE_LO/HI */
205 OUT_RING(ring, base); /* RB_STENCIL_BASE_LO */
206 } else {
207 OUT_PKT4(ring, REG_A6XX_RB_STENCIL_INFO, 1);
208 OUT_RING(ring, 0x00000000); /* RB_STENCIL_INFO */
209 }
210 } else {
211 OUT_PKT4(ring, REG_A6XX_RB_DEPTH_BUFFER_INFO, 6);
212 OUT_RING(ring, A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH6_NONE));
213 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_PITCH */
214 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_ARRAY_PITCH */
215 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_BASE_LO */
216 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_BASE_HI */
217 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_BASE_GMEM */
218
219 OUT_PKT4(ring, REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO, 1);
220 OUT_RING(ring, A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH6_NONE));
221
222 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO, 5);
223 OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
224 OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
225 OUT_RING(ring, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
226 OUT_RING(ring, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO */
227 OUT_RING(ring, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI */
228
229 OUT_PKT4(ring, REG_A6XX_RB_STENCIL_INFO, 1);
230 OUT_RING(ring, 0x00000000); /* RB_STENCIL_INFO */
231 }
232 }
233
234 static bool
235 use_hw_binning(struct fd_batch *batch)
236 {
237 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
238
239 // TODO figure out hw limits for binning
240
241 return fd_binning_enabled && ((gmem->nbins_x * gmem->nbins_y) > 2) &&
242 (batch->num_draws > 0);
243 }
244
245 static void
246 patch_draws(struct fd_batch *batch, enum pc_di_vis_cull_mode vismode)
247 {
248 unsigned i;
249 for (i = 0; i < fd_patch_num_elements(&batch->draw_patches); i++) {
250 struct fd_cs_patch *patch = fd_patch_element(&batch->draw_patches, i);
251 *patch->cs = patch->val | DRAW4(0, 0, 0, vismode);
252 }
253 util_dynarray_resize(&batch->draw_patches, 0);
254 }
255
256 static void
257 update_render_cntl(struct fd_batch *batch, bool binning)
258 {
259 struct fd_ringbuffer *ring = batch->gmem;
260 uint32_t cntl = 0;
261
262 cntl |= A6XX_RB_RENDER_CNTL_UNK4;
263 if (binning)
264 cntl |= A6XX_RB_RENDER_CNTL_BINNING;
265
266 OUT_PKT7(ring, CP_REG_WRITE, 3);
267 OUT_RING(ring, 0x2);
268 OUT_RING(ring, REG_A6XX_RB_RENDER_CNTL);
269 OUT_RING(ring, cntl);
270 }
271
272 static void
273 update_vsc_pipe(struct fd_batch *batch)
274 {
275 struct fd_context *ctx = batch->ctx;
276 struct fd6_context *fd6_ctx = fd6_context(ctx);
277 struct fd_gmem_stateobj *gmem = &ctx->gmem;
278 struct fd_ringbuffer *ring = batch->gmem;
279 int i;
280
281 OUT_PKT4(ring, REG_A6XX_VSC_BIN_SIZE, 3);
282 OUT_RING(ring, A6XX_VSC_BIN_SIZE_WIDTH(gmem->bin_w) |
283 A6XX_VSC_BIN_SIZE_HEIGHT(gmem->bin_h));
284 OUT_RELOCW(ring, fd6_ctx->vsc_data,
285 32 * A6XX_VSC_DATA_PITCH, 0, 0); /* VSC_SIZE_ADDRESS_LO/HI */
286
287 OUT_PKT4(ring, REG_A6XX_VSC_BIN_COUNT, 1);
288 OUT_RING(ring, A6XX_VSC_BIN_COUNT_NX(gmem->nbins_x) |
289 A6XX_VSC_BIN_COUNT_NY(gmem->nbins_y));
290
291 OUT_PKT4(ring, REG_A6XX_VSC_PIPE_CONFIG_REG(0), 32);
292 for (i = 0; i < 32; i++) {
293 struct fd_vsc_pipe *pipe = &ctx->vsc_pipe[i];
294 OUT_RING(ring, A6XX_VSC_PIPE_CONFIG_REG_X(pipe->x) |
295 A6XX_VSC_PIPE_CONFIG_REG_Y(pipe->y) |
296 A6XX_VSC_PIPE_CONFIG_REG_W(pipe->w) |
297 A6XX_VSC_PIPE_CONFIG_REG_H(pipe->h));
298 }
299
300 OUT_PKT4(ring, REG_A6XX_VSC_PIPE_DATA2_ADDRESS_LO, 4);
301 OUT_RELOCW(ring, fd6_ctx->vsc_data2, 0, 0, 0);
302 OUT_RING(ring, A6XX_VSC_DATA2_PITCH);
303 OUT_RING(ring, fd_bo_size(fd6_ctx->vsc_data2));
304
305 OUT_PKT4(ring, REG_A6XX_VSC_PIPE_DATA_ADDRESS_LO, 4);
306 OUT_RELOCW(ring, fd6_ctx->vsc_data, 0, 0, 0);
307 OUT_RING(ring, A6XX_VSC_DATA_PITCH);
308 OUT_RING(ring, fd_bo_size(fd6_ctx->vsc_data));
309 }
310
311 static void
312 set_scissor(struct fd_ringbuffer *ring, uint32_t x1, uint32_t y1, uint32_t x2, uint32_t y2)
313 {
314 OUT_PKT4(ring, REG_A6XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
315 OUT_RING(ring, A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X(x1) |
316 A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(y1));
317 OUT_RING(ring, A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X(x2) |
318 A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(y2));
319
320 OUT_PKT4(ring, REG_A6XX_GRAS_RESOLVE_CNTL_1, 2);
321 OUT_RING(ring, A6XX_GRAS_RESOLVE_CNTL_1_X(x1) |
322 A6XX_GRAS_RESOLVE_CNTL_1_Y(y1));
323 OUT_RING(ring, A6XX_GRAS_RESOLVE_CNTL_2_X(x2) |
324 A6XX_GRAS_RESOLVE_CNTL_2_Y(y2));
325 }
326
327 static void
328 set_bin_size(struct fd_ringbuffer *ring, uint32_t w, uint32_t h, uint32_t flag)
329 {
330 OUT_PKT4(ring, REG_A6XX_GRAS_BIN_CONTROL, 1);
331 OUT_RING(ring, A6XX_GRAS_BIN_CONTROL_BINW(w) |
332 A6XX_GRAS_BIN_CONTROL_BINH(h) | flag);
333
334 OUT_PKT4(ring, REG_A6XX_RB_BIN_CONTROL, 1);
335 OUT_RING(ring, A6XX_RB_BIN_CONTROL_BINW(w) |
336 A6XX_RB_BIN_CONTROL_BINH(h) | flag);
337
338 /* no flag for RB_BIN_CONTROL2... */
339 OUT_PKT4(ring, REG_A6XX_RB_BIN_CONTROL2, 1);
340 OUT_RING(ring, A6XX_RB_BIN_CONTROL2_BINW(w) |
341 A6XX_RB_BIN_CONTROL2_BINH(h));
342 }
343
344 static void
345 emit_binning_pass(struct fd_batch *batch)
346 {
347 struct fd_context *ctx = batch->ctx;
348 struct fd_ringbuffer *ring = batch->gmem;
349 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
350
351 uint32_t x1 = gmem->minx;
352 uint32_t y1 = gmem->miny;
353 uint32_t x2 = gmem->minx + gmem->width - 1;
354 uint32_t y2 = gmem->miny + gmem->height - 1;
355
356 set_scissor(ring, x1, y1, x2, y2);
357
358 emit_marker6(ring, 7);
359 OUT_PKT7(ring, CP_SET_MARKER, 1);
360 OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(RM6_BINNING));
361 emit_marker6(ring, 7);
362
363 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
364 OUT_RING(ring, 0x1);
365
366 OUT_PKT7(ring, CP_SET_MODE, 1);
367 OUT_RING(ring, 0x1);
368
369 OUT_WFI5(ring);
370
371 OUT_PKT4(ring, REG_A6XX_VFD_MODE_CNTL, 1);
372 OUT_RING(ring, A6XX_VFD_MODE_CNTL_BINNING_PASS);
373
374 update_vsc_pipe(batch);
375
376 OUT_PKT4(ring, REG_A6XX_PC_UNKNOWN_9805, 1);
377 OUT_RING(ring, 0x1);
378
379 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A0F8, 1);
380 OUT_RING(ring, 0x1);
381
382 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
383 OUT_RING(ring, UNK_2C);
384
385 OUT_PKT4(ring, REG_A6XX_RB_WINDOW_OFFSET, 1);
386 OUT_RING(ring, A6XX_RB_WINDOW_OFFSET_X(0) |
387 A6XX_RB_WINDOW_OFFSET_Y(0));
388
389 OUT_PKT4(ring, REG_A6XX_SP_TP_WINDOW_OFFSET, 1);
390 OUT_RING(ring, A6XX_SP_TP_WINDOW_OFFSET_X(0) |
391 A6XX_SP_TP_WINDOW_OFFSET_Y(0));
392
393 /* emit IB to binning drawcmds: */
394 fd6_emit_ib(ring, batch->draw);
395
396 fd_reset_wfi(batch);
397
398 OUT_PKT7(ring, CP_SET_DRAW_STATE, 3);
399 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
400 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
401 CP_SET_DRAW_STATE__0_GROUP_ID(0));
402 OUT_RING(ring, CP_SET_DRAW_STATE__1_ADDR_LO(0));
403 OUT_RING(ring, CP_SET_DRAW_STATE__2_ADDR_HI(0));
404
405 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
406 OUT_RING(ring, UNK_2D);
407
408 OUT_PKT7(ring, CP_EVENT_WRITE, 4);
409 OUT_RING(ring, CACHE_FLUSH_TS);
410 OUT_RELOCW(ring, fd6_context(ctx)->blit_mem, 0, 0, 0); /* ADDR_LO/HI */
411 OUT_RING(ring, 0x00000000);
412
413 fd_wfi(batch, ring);
414 }
415
416 static void
417 disable_msaa(struct fd_ringbuffer *ring)
418 {
419 // TODO MSAA
420 OUT_PKT4(ring, REG_A6XX_SP_TP_RAS_MSAA_CNTL, 2);
421 OUT_RING(ring, A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(MSAA_ONE));
422 OUT_RING(ring, A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(MSAA_ONE) |
423 A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE);
424
425 OUT_PKT4(ring, REG_A6XX_GRAS_RAS_MSAA_CNTL, 2);
426 OUT_RING(ring, A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(MSAA_ONE));
427 OUT_RING(ring, A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(MSAA_ONE) |
428 A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE);
429
430 OUT_PKT4(ring, REG_A6XX_RB_RAS_MSAA_CNTL, 2);
431 OUT_RING(ring, A6XX_RB_RAS_MSAA_CNTL_SAMPLES(MSAA_ONE));
432 OUT_RING(ring, A6XX_RB_DEST_MSAA_CNTL_SAMPLES(MSAA_ONE) |
433 A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE);
434 }
435
436 static void prepare_tile_setup_ib(struct fd_batch *batch);
437 static void prepare_tile_fini_ib(struct fd_batch *batch);
438
439 /* before first tile */
440 static void
441 fd6_emit_tile_init(struct fd_batch *batch)
442 {
443 struct fd_context *ctx = batch->ctx;
444 struct fd_ringbuffer *ring = batch->gmem;
445 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
446 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
447
448 fd6_emit_restore(batch, ring);
449
450 fd6_emit_lrz_flush(ring);
451
452 if (batch->lrz_clear)
453 fd6_emit_ib(ring, batch->lrz_clear);
454
455 fd6_cache_flush(batch, ring);
456
457 prepare_tile_setup_ib(batch);
458 prepare_tile_fini_ib(batch);
459
460 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
461 OUT_RING(ring, 0x0);
462
463 /* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */
464 fd_wfi(batch, ring);
465 OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
466 OUT_RING(ring, 0x7c400004); /* RB_CCU_CNTL */
467
468 emit_zs(ring, pfb->zsbuf, &ctx->gmem);
469 emit_mrt(ring, pfb, &ctx->gmem);
470
471 disable_msaa(ring);
472
473 if (use_hw_binning(batch)) {
474 set_bin_size(ring, gmem->bin_w, gmem->bin_h,
475 A6XX_RB_BIN_CONTROL_BINNING_PASS | 0x6000000);
476 update_render_cntl(batch, true);
477 emit_binning_pass(batch);
478 patch_draws(batch, USE_VISIBILITY);
479
480 set_bin_size(ring, gmem->bin_w, gmem->bin_h,
481 A6XX_RB_BIN_CONTROL_USE_VIZ | 0x6000000);
482
483 OUT_PKT4(ring, REG_A6XX_VFD_MODE_CNTL, 1);
484 OUT_RING(ring, 0x0);
485 } else {
486 set_bin_size(ring, gmem->bin_w, gmem->bin_h, 0x6000000);
487 patch_draws(batch, IGNORE_VISIBILITY);
488 }
489
490 update_render_cntl(batch, false);
491 }
492
493 static void
494 set_window_offset(struct fd_ringbuffer *ring, uint32_t x1, uint32_t y1)
495 {
496 OUT_PKT4(ring, REG_A6XX_RB_WINDOW_OFFSET, 1);
497 OUT_RING(ring, A6XX_RB_WINDOW_OFFSET_X(x1) |
498 A6XX_RB_WINDOW_OFFSET_Y(y1));
499
500 OUT_PKT4(ring, REG_A6XX_RB_WINDOW_OFFSET2, 1);
501 OUT_RING(ring, A6XX_RB_WINDOW_OFFSET2_X(x1) |
502 A6XX_RB_WINDOW_OFFSET2_Y(y1));
503
504 OUT_PKT4(ring, REG_A6XX_SP_WINDOW_OFFSET, 1);
505 OUT_RING(ring, A6XX_SP_WINDOW_OFFSET_X(x1) |
506 A6XX_SP_WINDOW_OFFSET_Y(y1));
507
508 OUT_PKT4(ring, REG_A6XX_SP_TP_WINDOW_OFFSET, 1);
509 OUT_RING(ring, A6XX_SP_TP_WINDOW_OFFSET_X(x1) |
510 A6XX_SP_TP_WINDOW_OFFSET_Y(y1));
511 }
512
513 /* before mem2gmem */
514 static void
515 fd6_emit_tile_prep(struct fd_batch *batch, struct fd_tile *tile)
516 {
517 struct fd_context *ctx = batch->ctx;
518 struct fd6_context *fd6_ctx = fd6_context(ctx);
519 struct fd_ringbuffer *ring = batch->gmem;
520
521 OUT_PKT7(ring, CP_SET_MARKER, 1);
522 OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(0x7));
523
524 emit_marker6(ring, 7);
525 OUT_PKT7(ring, CP_SET_MARKER, 1);
526 OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(RM6_GMEM) | 0x10);
527 emit_marker6(ring, 7);
528
529 uint32_t x1 = tile->xoff;
530 uint32_t y1 = tile->yoff;
531 uint32_t x2 = tile->xoff + tile->bin_w - 1;
532 uint32_t y2 = tile->yoff + tile->bin_h - 1;
533
534 set_scissor(ring, x1, y1, x2, y2);
535
536 set_window_offset(ring, x1, y1);
537
538 OUT_PKT4(ring, REG_A6XX_VPC_SO_OVERRIDE, 1);
539 OUT_RING(ring, A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
540
541 if (use_hw_binning(batch)) {
542 struct fd_vsc_pipe *pipe = &ctx->vsc_pipe[tile->p];
543
544 OUT_PKT7(ring, CP_WAIT_FOR_ME, 0);
545
546 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
547 OUT_RING(ring, 0x0);
548
549 OUT_PKT7(ring, CP_SET_MODE, 1);
550 OUT_RING(ring, 0x0);
551
552 OUT_PKT7(ring, CP_SET_BIN_DATA5, 7);
553 OUT_RING(ring, CP_SET_BIN_DATA5_0_VSC_SIZE(pipe->w * pipe->h) |
554 CP_SET_BIN_DATA5_0_VSC_N(tile->n));
555 OUT_RELOC(ring, fd6_ctx->vsc_data, /* VSC_PIPE[p].DATA_ADDRESS */
556 (tile->p * A6XX_VSC_DATA_PITCH), 0, 0);
557 OUT_RELOC(ring, fd6_ctx->vsc_data, /* VSC_SIZE_ADDRESS + (p * 4) */
558 (tile->p * 4) + (32 * A6XX_VSC_DATA_PITCH), 0, 0);
559 OUT_RELOC(ring, fd6_ctx->vsc_data2,
560 (tile->p * A6XX_VSC_DATA2_PITCH), 0, 0);
561 } else {
562 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
563 OUT_RING(ring, 0x1);
564
565 OUT_PKT7(ring, CP_SET_MODE, 1);
566 OUT_RING(ring, 0x0);
567 }
568 }
569
570 static void
571 set_blit_scissor(struct fd_batch *batch, struct fd_ringbuffer *ring)
572 {
573 struct pipe_scissor_state blit_scissor;
574 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
575
576 blit_scissor.minx = batch->max_scissor.minx;
577 blit_scissor.miny = batch->max_scissor.miny;
578 blit_scissor.maxx = MIN2(pfb->width, batch->max_scissor.maxx);
579 blit_scissor.maxy = MIN2(pfb->height, batch->max_scissor.maxy);
580
581 OUT_PKT4(ring, REG_A6XX_RB_BLIT_SCISSOR_TL, 2);
582 OUT_RING(ring,
583 A6XX_RB_BLIT_SCISSOR_TL_X(blit_scissor.minx) |
584 A6XX_RB_BLIT_SCISSOR_TL_Y(blit_scissor.miny));
585 OUT_RING(ring,
586 A6XX_RB_BLIT_SCISSOR_BR_X(blit_scissor.maxx - 1) |
587 A6XX_RB_BLIT_SCISSOR_BR_Y(blit_scissor.maxy - 1));
588 }
589
590 static void
591 emit_blit(struct fd_batch *batch,
592 struct fd_ringbuffer *ring,
593 uint32_t base,
594 struct pipe_surface *psurf,
595 struct fd_resource *rsc)
596 {
597 struct fd_resource_slice *slice;
598 uint32_t offset;
599
600 slice = fd_resource_slice(rsc, psurf->u.tex.level);
601 offset = fd_resource_offset(rsc, psurf->u.tex.level,
602 psurf->u.tex.first_layer);
603
604 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
605
606 enum pipe_format pfmt = psurf->format;
607 enum a6xx_color_fmt format = fd6_pipe2color(pfmt);
608 uint32_t stride = slice->pitch * rsc->cpp;
609 uint32_t size = slice->size0;
610 enum a3xx_color_swap swap = fd6_pipe2swap(pfmt);
611
612 // TODO: tile mode
613 // bool tiled;
614 // tiled = rsc->tile_mode &&
615 // !fd_resource_level_linear(psurf->texture, psurf->u.tex.level);
616
617 OUT_PKT4(ring, REG_A6XX_RB_BLIT_DST_INFO, 5);
618 OUT_RING(ring,
619 A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR) |
620 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(format) |
621 A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(swap));
622 OUT_RELOCW(ring, rsc->bo, offset, 0, 0); /* RB_BLIT_DST_LO/HI */
623 OUT_RING(ring, A6XX_RB_BLIT_DST_PITCH(stride));
624 OUT_RING(ring, A6XX_RB_BLIT_DST_ARRAY_PITCH(size));
625
626 OUT_PKT4(ring, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
627 OUT_RING(ring, base);
628
629 fd6_emit_blit(batch, ring);
630 }
631
632 static void
633 emit_restore_blit(struct fd_batch *batch,
634 struct fd_ringbuffer *ring,
635 uint32_t base,
636 struct pipe_surface *psurf,
637 struct fd_resource *rsc,
638 unsigned buffer)
639 {
640 uint32_t info = 0;
641
642 switch (buffer) {
643 case FD_BUFFER_COLOR:
644 info |= A6XX_RB_BLIT_INFO_UNK0;
645 break;
646 case FD_BUFFER_STENCIL:
647 info |= A6XX_RB_BLIT_INFO_UNK0;
648 break;
649 case FD_BUFFER_DEPTH:
650 info |= A6XX_RB_BLIT_INFO_DEPTH | A6XX_RB_BLIT_INFO_UNK0;
651 break;
652 }
653
654 if (util_format_is_pure_integer(psurf->format))
655 info |= A6XX_RB_BLIT_INFO_INTEGER;
656
657 OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
658 OUT_RING(ring, info | A6XX_RB_BLIT_INFO_GMEM);
659
660 emit_blit(batch, ring, base, psurf, rsc);
661 }
662
663 static void
664 emit_clears(struct fd_batch *batch, struct fd_ringbuffer *ring)
665 {
666 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
667 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
668
669 uint32_t buffers = batch->fast_cleared;
670
671 if (buffers & PIPE_CLEAR_COLOR) {
672
673 for (int i = 0; i < pfb->nr_cbufs; i++) {
674 union pipe_color_union *color = &batch->clear_color[i];
675 union util_color uc = {0};
676
677 if (!pfb->cbufs[i])
678 continue;
679
680 if (!(buffers & (PIPE_CLEAR_COLOR0 << i)))
681 continue;
682
683 enum pipe_format pfmt = pfb->cbufs[i]->format;
684
685 // XXX I think RB_CLEAR_COLOR_DWn wants to take into account SWAP??
686 union pipe_color_union swapped;
687 switch (fd6_pipe2swap(pfmt)) {
688 case WZYX:
689 swapped.ui[0] = color->ui[0];
690 swapped.ui[1] = color->ui[1];
691 swapped.ui[2] = color->ui[2];
692 swapped.ui[3] = color->ui[3];
693 break;
694 case WXYZ:
695 swapped.ui[2] = color->ui[0];
696 swapped.ui[1] = color->ui[1];
697 swapped.ui[0] = color->ui[2];
698 swapped.ui[3] = color->ui[3];
699 break;
700 case ZYXW:
701 swapped.ui[3] = color->ui[0];
702 swapped.ui[0] = color->ui[1];
703 swapped.ui[1] = color->ui[2];
704 swapped.ui[2] = color->ui[3];
705 break;
706 case XYZW:
707 swapped.ui[3] = color->ui[0];
708 swapped.ui[2] = color->ui[1];
709 swapped.ui[1] = color->ui[2];
710 swapped.ui[0] = color->ui[3];
711 break;
712 }
713
714 if (util_format_is_pure_uint(pfmt)) {
715 util_format_write_4ui(pfmt, swapped.ui, 0, &uc, 0, 0, 0, 1, 1);
716 } else if (util_format_is_pure_sint(pfmt)) {
717 util_format_write_4i(pfmt, swapped.i, 0, &uc, 0, 0, 0, 1, 1);
718 } else {
719 util_pack_color(swapped.f, pfmt, &uc);
720 }
721
722 OUT_PKT4(ring, REG_A6XX_RB_BLIT_DST_INFO, 1);
723 OUT_RING(ring, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR) |
724 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(fd6_pipe2color(pfmt)));
725
726 OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
727 OUT_RING(ring, A6XX_RB_BLIT_INFO_GMEM |
728 A6XX_RB_BLIT_INFO_CLEAR_MASK(0xf));
729
730 OUT_PKT4(ring, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
731 OUT_RING(ring, gmem->cbuf_base[i]);
732
733 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_88D0, 1);
734 OUT_RING(ring, 0);
735
736 OUT_PKT4(ring, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 4);
737 OUT_RING(ring, uc.ui[0]);
738 OUT_RING(ring, uc.ui[1]);
739 OUT_RING(ring, uc.ui[2]);
740 OUT_RING(ring, uc.ui[3]);
741
742 fd6_emit_blit(batch, ring);
743 }
744 }
745
746 const bool has_depth = pfb->zsbuf;
747 const bool has_separate_stencil =
748 has_depth && fd_resource(pfb->zsbuf->texture)->stencil;
749
750 /* First clear depth or combined depth/stencil. */
751 if ((has_depth && (buffers & PIPE_CLEAR_DEPTH)) ||
752 (!has_separate_stencil && (buffers & PIPE_CLEAR_STENCIL))) {
753 enum pipe_format pfmt = pfb->zsbuf->format;
754 uint32_t clear_value;
755 uint32_t mask = 0;
756
757 if (has_separate_stencil) {
758 pfmt = util_format_get_depth_only(pfb->zsbuf->format);
759 clear_value = util_pack_z(pfmt, batch->clear_depth);
760 } else {
761 pfmt = pfb->zsbuf->format;
762 clear_value = util_pack_z_stencil(pfmt, batch->clear_depth,
763 batch->clear_stencil);
764 }
765
766 if (buffers & PIPE_CLEAR_DEPTH)
767 mask |= 0x1;
768
769 if (!has_separate_stencil && (buffers & PIPE_CLEAR_STENCIL))
770 mask |= 0x2;
771
772 OUT_PKT4(ring, REG_A6XX_RB_BLIT_DST_INFO, 1);
773 OUT_RING(ring, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR) |
774 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(fd6_pipe2color(pfmt)));
775
776 OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
777 OUT_RING(ring, A6XX_RB_BLIT_INFO_GMEM |
778 // XXX UNK0 for separate stencil ??
779 A6XX_RB_BLIT_INFO_DEPTH |
780 A6XX_RB_BLIT_INFO_CLEAR_MASK(mask));
781
782 OUT_PKT4(ring, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
783 OUT_RING(ring, gmem->zsbuf_base[0]);
784
785 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_88D0, 1);
786 OUT_RING(ring, 0);
787
788 OUT_PKT4(ring, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 1);
789 OUT_RING(ring, clear_value);
790
791 fd6_emit_blit(batch, ring);
792 }
793
794 /* Then clear the separate stencil buffer in case of 32 bit depth
795 * formats with separate stencil. */
796 if (has_separate_stencil && (buffers & PIPE_CLEAR_STENCIL)) {
797 OUT_PKT4(ring, REG_A6XX_RB_BLIT_DST_INFO, 1);
798 OUT_RING(ring, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR) |
799 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(RB6_R8_UINT));
800
801 OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
802 OUT_RING(ring, A6XX_RB_BLIT_INFO_GMEM |
803 //A6XX_RB_BLIT_INFO_UNK0 |
804 A6XX_RB_BLIT_INFO_DEPTH |
805 A6XX_RB_BLIT_INFO_CLEAR_MASK(0x1));
806
807 OUT_PKT4(ring, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
808 OUT_RING(ring, gmem->zsbuf_base[1]);
809
810 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_88D0, 1);
811 OUT_RING(ring, 0);
812
813 OUT_PKT4(ring, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 1);
814 OUT_RING(ring, batch->clear_stencil & 0xff);
815
816 fd6_emit_blit(batch, ring);
817 }
818 }
819
820 /*
821 * transfer from system memory to gmem
822 */
823 static void
824 emit_restore_blits(struct fd_batch *batch, struct fd_ringbuffer *ring)
825 {
826 struct fd_context *ctx = batch->ctx;
827 struct fd_gmem_stateobj *gmem = &ctx->gmem;
828 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
829
830 if (batch->restore & FD_BUFFER_COLOR) {
831 unsigned i;
832 for (i = 0; i < pfb->nr_cbufs; i++) {
833 if (!pfb->cbufs[i])
834 continue;
835 if (!(batch->restore & (PIPE_CLEAR_COLOR0 << i)))
836 continue;
837 emit_restore_blit(batch, ring, gmem->cbuf_base[i], pfb->cbufs[i],
838 fd_resource(pfb->cbufs[i]->texture),
839 FD_BUFFER_COLOR);
840 }
841 }
842
843 if (batch->restore & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
844 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
845
846 if (!rsc->stencil || (batch->restore & FD_BUFFER_DEPTH)) {
847 emit_restore_blit(batch, ring, gmem->zsbuf_base[0], pfb->zsbuf, rsc,
848 FD_BUFFER_DEPTH);
849 }
850 if (rsc->stencil && (batch->restore & FD_BUFFER_STENCIL)) {
851 emit_restore_blit(batch, ring, gmem->zsbuf_base[1], pfb->zsbuf, rsc->stencil,
852 FD_BUFFER_STENCIL);
853 }
854 }
855 }
856
857 static void
858 prepare_tile_setup_ib(struct fd_batch *batch)
859 {
860 batch->tile_setup = fd_submit_new_ringbuffer(batch->submit, 0x1000,
861 FD_RINGBUFFER_STREAMING);
862
863 set_blit_scissor(batch, batch->tile_setup);
864
865 emit_restore_blits(batch, batch->tile_setup);
866 emit_clears(batch, batch->tile_setup);
867 }
868
869 /*
870 * transfer from system memory to gmem
871 */
872 static void
873 fd6_emit_tile_mem2gmem(struct fd_batch *batch, struct fd_tile *tile)
874 {
875 }
876
877 /* before IB to rendering cmds: */
878 static void
879 fd6_emit_tile_renderprep(struct fd_batch *batch, struct fd_tile *tile)
880 {
881 fd6_emit_ib(batch->gmem, batch->tile_setup);
882 }
883
884 static void
885 emit_resolve_blit(struct fd_batch *batch,
886 struct fd_ringbuffer *ring,
887 uint32_t base,
888 struct pipe_surface *psurf,
889 struct fd_resource *rsc,
890 unsigned buffer)
891 {
892 uint32_t info = 0;
893
894 if (!rsc->valid)
895 return;
896
897 switch (buffer) {
898 case FD_BUFFER_COLOR:
899 break;
900 case FD_BUFFER_STENCIL:
901 info |= A6XX_RB_BLIT_INFO_UNK0;
902 break;
903 case FD_BUFFER_DEPTH:
904 info |= A6XX_RB_BLIT_INFO_DEPTH;
905 break;
906 }
907
908 if (util_format_is_pure_integer(psurf->format))
909 info |= A6XX_RB_BLIT_INFO_INTEGER;
910
911 OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
912 OUT_RING(ring, info);
913
914 emit_blit(batch, ring, base, psurf, rsc);
915 }
916
917 /*
918 * transfer from gmem to system memory (ie. normal RAM)
919 */
920
921 static void
922 prepare_tile_fini_ib(struct fd_batch *batch)
923 {
924 struct fd_context *ctx = batch->ctx;
925 struct fd_gmem_stateobj *gmem = &ctx->gmem;
926 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
927 struct fd_ringbuffer *ring;
928
929 batch->tile_fini = fd_submit_new_ringbuffer(batch->submit, 0x1000,
930 FD_RINGBUFFER_STREAMING);
931 ring = batch->tile_fini;
932
933 if (use_hw_binning(batch)) {
934 OUT_PKT7(ring, CP_SET_MARKER, 1);
935 OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(0x5) | 0x10);
936 }
937
938 OUT_PKT7(ring, CP_SET_DRAW_STATE, 3);
939 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
940 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
941 CP_SET_DRAW_STATE__0_GROUP_ID(0));
942 OUT_RING(ring, CP_SET_DRAW_STATE__1_ADDR_LO(0));
943 OUT_RING(ring, CP_SET_DRAW_STATE__2_ADDR_HI(0));
944
945 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
946 OUT_RING(ring, 0x0);
947
948 emit_marker6(ring, 7);
949 OUT_PKT7(ring, CP_SET_MARKER, 1);
950 OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE) | 0x10);
951 emit_marker6(ring, 7);
952
953 set_blit_scissor(batch, ring);
954
955 if (batch->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
956 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
957
958 if (!rsc->stencil || (batch->resolve & FD_BUFFER_DEPTH)) {
959 emit_resolve_blit(batch, ring,
960 gmem->zsbuf_base[0], pfb->zsbuf, rsc,
961 FD_BUFFER_DEPTH);
962 }
963 if (rsc->stencil && (batch->resolve & FD_BUFFER_STENCIL)) {
964 emit_resolve_blit(batch, ring,
965 gmem->zsbuf_base[1], pfb->zsbuf, rsc->stencil,
966 FD_BUFFER_STENCIL);
967 }
968 }
969
970 if (batch->resolve & FD_BUFFER_COLOR) {
971 unsigned i;
972 for (i = 0; i < pfb->nr_cbufs; i++) {
973 if (!pfb->cbufs[i])
974 continue;
975 if (!(batch->resolve & (PIPE_CLEAR_COLOR0 << i)))
976 continue;
977 emit_resolve_blit(batch, ring, gmem->cbuf_base[i], pfb->cbufs[i],
978 fd_resource(pfb->cbufs[i]->texture),
979 FD_BUFFER_COLOR);
980 }
981 }
982 }
983
984 static void
985 fd6_emit_tile_gmem2mem(struct fd_batch *batch, struct fd_tile *tile)
986 {
987 fd6_emit_ib(batch->gmem, batch->tile_fini);
988 }
989
990 static void
991 fd6_emit_tile_fini(struct fd_batch *batch)
992 {
993 struct fd_ringbuffer *ring = batch->gmem;
994
995 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_CNTL, 1);
996 OUT_RING(ring, A6XX_GRAS_LRZ_CNTL_ENABLE | A6XX_GRAS_LRZ_CNTL_UNK3);
997
998 fd6_emit_lrz_flush(ring);
999
1000 fd6_event_write(batch, ring, CACHE_FLUSH_TS, true);
1001 }
1002
1003 static void
1004 fd6_emit_sysmem_prep(struct fd_batch *batch)
1005 {
1006 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
1007 struct fd_ringbuffer *ring = batch->gmem;
1008
1009 fd6_emit_restore(batch, ring);
1010
1011 fd6_emit_lrz_flush(ring);
1012
1013 emit_marker6(ring, 7);
1014 OUT_PKT7(ring, CP_SET_MARKER, 1);
1015 OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(RM6_BYPASS) | 0x10); /* | 0x10 ? */
1016 emit_marker6(ring, 7);
1017
1018 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1019 OUT_RING(ring, 0x0);
1020
1021 fd6_event_write(batch, ring, PC_CCU_INVALIDATE_COLOR, false);
1022 fd6_cache_flush(batch, ring);
1023
1024 #if 0
1025 OUT_PKT4(ring, REG_A6XX_PC_POWER_CNTL, 1);
1026 OUT_RING(ring, 0x00000003); /* PC_POWER_CNTL */
1027 #endif
1028
1029 #if 0
1030 OUT_PKT4(ring, REG_A6XX_VFD_POWER_CNTL, 1);
1031 OUT_RING(ring, 0x00000003); /* VFD_POWER_CNTL */
1032 #endif
1033
1034 /* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */
1035 fd_wfi(batch, ring);
1036 OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
1037 OUT_RING(ring, 0x10000000); /* RB_CCU_CNTL */
1038
1039 set_scissor(ring, 0, 0, pfb->width - 1, pfb->height - 1);
1040
1041 set_window_offset(ring, 0, 0);
1042
1043 set_bin_size(ring, 0, 0, 0xc00000); /* 0xc00000 = BYPASS? */
1044
1045 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
1046 OUT_RING(ring, 0x1);
1047
1048 patch_draws(batch, IGNORE_VISIBILITY);
1049
1050 emit_zs(ring, pfb->zsbuf, NULL);
1051 emit_mrt(ring, pfb, NULL);
1052
1053 disable_msaa(ring);
1054 }
1055
1056 static void
1057 fd6_emit_sysmem_fini(struct fd_batch *batch)
1058 {
1059 struct fd_ringbuffer *ring = batch->gmem;
1060
1061 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1062 OUT_RING(ring, 0x0);
1063
1064 fd6_emit_lrz_flush(ring);
1065
1066 fd6_event_write(batch, ring, UNK_1D, true);
1067 }
1068
1069 void
1070 fd6_gmem_init(struct pipe_context *pctx)
1071 {
1072 struct fd_context *ctx = fd_context(pctx);
1073
1074 ctx->emit_tile_init = fd6_emit_tile_init;
1075 ctx->emit_tile_prep = fd6_emit_tile_prep;
1076 ctx->emit_tile_mem2gmem = fd6_emit_tile_mem2gmem;
1077 ctx->emit_tile_renderprep = fd6_emit_tile_renderprep;
1078 ctx->emit_tile_gmem2mem = fd6_emit_tile_gmem2mem;
1079 ctx->emit_tile_fini = fd6_emit_tile_fini;
1080 ctx->emit_sysmem_prep = fd6_emit_sysmem_prep;
1081 ctx->emit_sysmem_fini = fd6_emit_sysmem_fini;
1082 }