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freedreno/a6xx: Set up multisample sysmem MRTs correctly
[mesa.git] / src / gallium / drivers / freedreno / a6xx / fd6_gmem.c
1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 * Authors:
25 * Rob Clark <robclark@freedesktop.org>
26 */
27
28 #include <stdio.h>
29
30 #include "pipe/p_state.h"
31 #include "util/u_string.h"
32 #include "util/u_memory.h"
33 #include "util/u_inlines.h"
34 #include "util/format/u_format.h"
35
36 #include "freedreno_draw.h"
37 #include "freedreno_state.h"
38 #include "freedreno_resource.h"
39
40 #include "fd6_blitter.h"
41 #include "fd6_gmem.h"
42 #include "fd6_context.h"
43 #include "fd6_draw.h"
44 #include "fd6_emit.h"
45 #include "fd6_program.h"
46 #include "fd6_format.h"
47 #include "fd6_resource.h"
48 #include "fd6_zsa.h"
49 #include "fd6_pack.h"
50
51 /**
52 * Emits the flags registers, suitable for RB_MRT_FLAG_BUFFER,
53 * RB_DEPTH_FLAG_BUFFER, SP_PS_2D_SRC_FLAGS, and RB_BLIT_FLAG_DST.
54 */
55 void
56 fd6_emit_flag_reference(struct fd_ringbuffer *ring, struct fd_resource *rsc,
57 int level, int layer)
58 {
59 if (fd_resource_ubwc_enabled(rsc, level)) {
60 OUT_RELOCW(ring, rsc->bo, fd_resource_ubwc_offset(rsc, level, layer), 0, 0);
61 OUT_RING(ring,
62 A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(rsc->layout.ubwc_slices[level].pitch) |
63 A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(rsc->layout.ubwc_size));
64 } else {
65 OUT_RING(ring, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_LO */
66 OUT_RING(ring, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_HI */
67 OUT_RING(ring, 0x00000000);
68 }
69 }
70
71 static void
72 emit_mrt(struct fd_ringbuffer *ring, struct pipe_framebuffer_state *pfb,
73 struct fd_gmem_stateobj *gmem)
74 {
75 unsigned char mrt_comp[A6XX_MAX_RENDER_TARGETS] = {0};
76 unsigned srgb_cntl = 0;
77 unsigned i;
78
79 bool layered = false;
80 unsigned type = 0;
81
82 for (i = 0; i < pfb->nr_cbufs; i++) {
83 enum a6xx_color_fmt format = 0;
84 enum a3xx_color_swap swap = WZYX;
85 bool sint = false, uint = false;
86 struct fd_resource *rsc = NULL;
87 struct fdl_slice *slice = NULL;
88 uint32_t stride = 0;
89 uint32_t offset;
90 uint32_t tile_mode;
91
92 if (!pfb->cbufs[i])
93 continue;
94
95 mrt_comp[i] = 0xf;
96
97 struct pipe_surface *psurf = pfb->cbufs[i];
98 enum pipe_format pformat = psurf->format;
99 rsc = fd_resource(psurf->texture);
100 if (!rsc->bo)
101 continue;
102
103 uint32_t base = gmem ? gmem->cbuf_base[i] : 0;
104 slice = fd_resource_slice(rsc, psurf->u.tex.level);
105 format = fd6_pipe2color(pformat);
106 sint = util_format_is_pure_sint(pformat);
107 uint = util_format_is_pure_uint(pformat);
108
109 if (util_format_is_srgb(pformat))
110 srgb_cntl |= (1 << i);
111
112 offset = fd_resource_offset(rsc, psurf->u.tex.level,
113 psurf->u.tex.first_layer);
114
115 stride = slice->pitch * rsc->layout.cpp;
116 swap = fd6_resource_swap(rsc, pformat);
117
118 tile_mode = fd_resource_tile_mode(psurf->texture, psurf->u.tex.level);
119
120 if (psurf->u.tex.first_layer < psurf->u.tex.last_layer) {
121 layered = true;
122 if (psurf->texture->target == PIPE_TEXTURE_2D_ARRAY && psurf->texture->nr_samples > 0)
123 type = LAYER_MULTISAMPLE_ARRAY;
124 else if (psurf->texture->target == PIPE_TEXTURE_2D_ARRAY)
125 type = LAYER_2D_ARRAY;
126 else if (psurf->texture->target == PIPE_TEXTURE_CUBE)
127 type = LAYER_CUBEMAP;
128 else if (psurf->texture->target == PIPE_TEXTURE_3D)
129 type = LAYER_3D;
130 }
131
132 debug_assert((offset + slice->size0) <= fd_bo_size(rsc->bo));
133
134 OUT_REG(ring,
135 A6XX_RB_MRT_BUF_INFO(i,
136 .color_format = format,
137 .color_tile_mode = tile_mode,
138 .color_swap = swap),
139 A6XX_RB_MRT_PITCH(i, .a6xx_rb_mrt_pitch = stride),
140 A6XX_RB_MRT_ARRAY_PITCH(i, .a6xx_rb_mrt_array_pitch = slice->size0),
141 A6XX_RB_MRT_BASE(i, .bo = rsc->bo, .bo_offset = offset),
142 A6XX_RB_MRT_BASE_GMEM(i, .unknown = base));
143
144 OUT_REG(ring,
145 A6XX_SP_FS_MRT_REG(i, .color_format = format,
146 .color_sint = sint, .color_uint = uint));
147
148 OUT_PKT4(ring, REG_A6XX_RB_MRT_FLAG_BUFFER(i), 3);
149 fd6_emit_flag_reference(ring, rsc,
150 psurf->u.tex.level, psurf->u.tex.first_layer);
151 }
152
153 OUT_REG(ring, A6XX_RB_SRGB_CNTL(.dword = srgb_cntl));
154 OUT_REG(ring, A6XX_SP_SRGB_CNTL(.dword = srgb_cntl));
155
156 OUT_REG(ring, A6XX_RB_RENDER_COMPONENTS(
157 .rt0 = mrt_comp[0],
158 .rt1 = mrt_comp[1],
159 .rt2 = mrt_comp[2],
160 .rt3 = mrt_comp[3],
161 .rt4 = mrt_comp[4],
162 .rt5 = mrt_comp[5],
163 .rt6 = mrt_comp[6],
164 .rt7 = mrt_comp[7]));
165
166 OUT_REG(ring, A6XX_SP_FS_RENDER_COMPONENTS(
167 .rt0 = mrt_comp[0],
168 .rt1 = mrt_comp[1],
169 .rt2 = mrt_comp[2],
170 .rt3 = mrt_comp[3],
171 .rt4 = mrt_comp[4],
172 .rt5 = mrt_comp[5],
173 .rt6 = mrt_comp[6],
174 .rt7 = mrt_comp[7]));
175
176 OUT_REG(ring, A6XX_GRAS_LAYER_CNTL(.layered = layered, .type = type));
177 }
178
179 static void
180 emit_zs(struct fd_ringbuffer *ring, struct pipe_surface *zsbuf,
181 struct fd_gmem_stateobj *gmem)
182 {
183 if (zsbuf) {
184 struct fd_resource *rsc = fd_resource(zsbuf->texture);
185 enum a6xx_depth_format fmt = fd6_pipe2depth(zsbuf->format);
186 struct fdl_slice *slice = fd_resource_slice(rsc, 0);
187 uint32_t stride = slice->pitch * rsc->layout.cpp;
188 uint32_t size = slice->size0;
189 uint32_t base = gmem ? gmem->zsbuf_base[0] : 0;
190 uint32_t offset = fd_resource_offset(rsc, zsbuf->u.tex.level,
191 zsbuf->u.tex.first_layer);
192
193 OUT_REG(ring,
194 A6XX_RB_DEPTH_BUFFER_INFO(.depth_format = fmt),
195 A6XX_RB_DEPTH_BUFFER_PITCH(.a6xx_rb_depth_buffer_pitch = stride),
196 A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(.a6xx_rb_depth_buffer_array_pitch = size),
197 A6XX_RB_DEPTH_BUFFER_BASE(.bo = rsc->bo, .bo_offset = offset),
198 A6XX_RB_DEPTH_BUFFER_BASE_GMEM(.dword = base));
199
200 OUT_REG(ring, A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format = fmt));
201
202 OUT_PKT4(ring, REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO, 3);
203 fd6_emit_flag_reference(ring, rsc,
204 zsbuf->u.tex.level, zsbuf->u.tex.first_layer);
205
206 if (rsc->lrz) {
207 OUT_REG(ring,
208 A6XX_GRAS_LRZ_BUFFER_BASE(.bo = rsc->lrz),
209 A6XX_GRAS_LRZ_BUFFER_PITCH(.pitch = rsc->lrz_pitch),
210 // XXX a6xx seems to use a different buffer here.. not sure what for..
211 A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO(0),
212 A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI(0));
213 } else {
214 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO, 5);
215 OUT_RING(ring, 0x00000000);
216 OUT_RING(ring, 0x00000000);
217 OUT_RING(ring, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
218 OUT_RING(ring, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO */
219 OUT_RING(ring, 0x00000000);
220 }
221
222 /* NOTE: blob emits GRAS_LRZ_CNTL plus GRAZ_LRZ_BUFFER_BASE
223 * plus this CP_EVENT_WRITE at the end in it's own IB..
224 */
225 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
226 OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(UNK_25));
227
228 if (rsc->stencil) {
229 struct fdl_slice *slice = fd_resource_slice(rsc->stencil, 0);
230 stride = slice->pitch * rsc->stencil->layout.cpp;
231 size = slice->size0;
232 uint32_t base = gmem ? gmem->zsbuf_base[1] : 0;
233
234 OUT_REG(ring,
235 A6XX_RB_STENCIL_INFO(.separate_stencil = true),
236 A6XX_RB_STENCIL_BUFFER_PITCH(.a6xx_rb_stencil_buffer_pitch = stride),
237 A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(.a6xx_rb_stencil_buffer_array_pitch = size),
238 A6XX_RB_STENCIL_BUFFER_BASE(.bo = rsc->stencil->bo),
239 A6XX_RB_STENCIL_BUFFER_BASE_GMEM(.dword = base));
240 } else {
241 OUT_REG(ring, A6XX_RB_STENCIL_INFO(0));
242 }
243 } else {
244 OUT_PKT4(ring, REG_A6XX_RB_DEPTH_BUFFER_INFO, 6);
245 OUT_RING(ring, A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH6_NONE));
246 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_PITCH */
247 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_ARRAY_PITCH */
248 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_BASE_LO */
249 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_BASE_HI */
250 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_BASE_GMEM */
251
252 OUT_REG(ring, A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format = DEPTH6_NONE));
253
254 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO, 5);
255 OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
256 OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
257 OUT_RING(ring, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
258 OUT_RING(ring, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO */
259 OUT_RING(ring, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI */
260
261 OUT_REG(ring, A6XX_RB_STENCIL_INFO(0));
262 }
263 }
264
265 static bool
266 use_hw_binning(struct fd_batch *batch)
267 {
268 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
269
270 // TODO figure out hw limits for binning
271
272 return fd_binning_enabled && ((gmem->nbins_x * gmem->nbins_y) >= 2) &&
273 (batch->num_draws > 0);
274 }
275
276 static void
277 patch_fb_read(struct fd_batch *batch)
278 {
279 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
280
281 for (unsigned i = 0; i < fd_patch_num_elements(&batch->fb_read_patches); i++) {
282 struct fd_cs_patch *patch = fd_patch_element(&batch->fb_read_patches, i);
283 *patch->cs = patch->val | A6XX_TEX_CONST_2_PITCH(gmem->bin_w * gmem->cbuf_cpp[0]);
284 }
285 util_dynarray_clear(&batch->fb_read_patches);
286 }
287
288 static void
289 update_render_cntl(struct fd_batch *batch, struct pipe_framebuffer_state *pfb, bool binning)
290 {
291 struct fd_ringbuffer *ring = batch->gmem;
292 uint32_t cntl = 0;
293 bool depth_ubwc_enable = false;
294 uint32_t mrts_ubwc_enable = 0;
295 int i;
296
297 if (pfb->zsbuf) {
298 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
299 depth_ubwc_enable = fd_resource_ubwc_enabled(rsc, pfb->zsbuf->u.tex.level);
300 }
301
302 for (i = 0; i < pfb->nr_cbufs; i++) {
303 if (!pfb->cbufs[i])
304 continue;
305
306 struct pipe_surface *psurf = pfb->cbufs[i];
307 struct fd_resource *rsc = fd_resource(psurf->texture);
308 if (!rsc->bo)
309 continue;
310
311 if (fd_resource_ubwc_enabled(rsc, psurf->u.tex.level))
312 mrts_ubwc_enable |= 1 << i;
313 }
314
315 cntl |= A6XX_RB_RENDER_CNTL_UNK4;
316 if (binning)
317 cntl |= A6XX_RB_RENDER_CNTL_BINNING;
318
319 OUT_PKT7(ring, CP_REG_WRITE, 3);
320 OUT_RING(ring, 0x2);
321 OUT_RING(ring, REG_A6XX_RB_RENDER_CNTL);
322 OUT_RING(ring, cntl |
323 COND(depth_ubwc_enable, A6XX_RB_RENDER_CNTL_FLAG_DEPTH) |
324 A6XX_RB_RENDER_CNTL_FLAG_MRTS(mrts_ubwc_enable));
325 }
326
327 #define VSC_DATA_SIZE(pitch) ((pitch) * 32 + 0x100) /* extra size to store VSC_SIZE */
328 #define VSC_DATA2_SIZE(pitch) ((pitch) * 32)
329
330 static void
331 update_vsc_pipe(struct fd_batch *batch)
332 {
333 struct fd_context *ctx = batch->ctx;
334 struct fd6_context *fd6_ctx = fd6_context(ctx);
335 struct fd_gmem_stateobj *gmem = &ctx->gmem;
336 struct fd_ringbuffer *ring = batch->gmem;
337 int i;
338
339
340 if (!fd6_ctx->vsc_data) {
341 fd6_ctx->vsc_data = fd_bo_new(ctx->screen->dev,
342 VSC_DATA_SIZE(fd6_ctx->vsc_data_pitch),
343 DRM_FREEDRENO_GEM_TYPE_KMEM, "vsc_data");
344 }
345
346 if (!fd6_ctx->vsc_data2) {
347 fd6_ctx->vsc_data2 = fd_bo_new(ctx->screen->dev,
348 VSC_DATA2_SIZE(fd6_ctx->vsc_data2_pitch),
349 DRM_FREEDRENO_GEM_TYPE_KMEM, "vsc_data2");
350 }
351
352 OUT_REG(ring,
353 A6XX_VSC_BIN_SIZE(.width = gmem->bin_w, .height = gmem->bin_h),
354 A6XX_VSC_SIZE_ADDRESS(.bo = fd6_ctx->vsc_data, .bo_offset = 32 * fd6_ctx->vsc_data_pitch));
355
356 OUT_REG(ring, A6XX_VSC_BIN_COUNT(.nx = gmem->nbins_x,
357 .ny = gmem->nbins_y));
358
359 OUT_PKT4(ring, REG_A6XX_VSC_PIPE_CONFIG_REG(0), 32);
360 for (i = 0; i < 32; i++) {
361 struct fd_vsc_pipe *pipe = &ctx->vsc_pipe[i];
362 OUT_RING(ring, A6XX_VSC_PIPE_CONFIG_REG_X(pipe->x) |
363 A6XX_VSC_PIPE_CONFIG_REG_Y(pipe->y) |
364 A6XX_VSC_PIPE_CONFIG_REG_W(pipe->w) |
365 A6XX_VSC_PIPE_CONFIG_REG_H(pipe->h));
366 }
367
368 OUT_REG(ring,
369 A6XX_VSC_PIPE_DATA2_ADDRESS(.bo = fd6_ctx->vsc_data2),
370 A6XX_VSC_PIPE_DATA2_PITCH(.dword = fd6_ctx->vsc_data2_pitch),
371 A6XX_VSC_PIPE_DATA2_ARRAY_PITCH(.dword = fd_bo_size(fd6_ctx->vsc_data2)));
372
373 OUT_REG(ring,
374 A6XX_VSC_PIPE_DATA_ADDRESS(.bo = fd6_ctx->vsc_data),
375 A6XX_VSC_PIPE_DATA_PITCH(.dword = fd6_ctx->vsc_data_pitch),
376 A6XX_VSC_PIPE_DATA_ARRAY_PITCH(.dword = fd_bo_size(fd6_ctx->vsc_data)));
377 }
378
379 /* TODO we probably have more than 8 scratch regs.. although the first
380 * 8 is what kernel dumps, and it is kinda useful to be able to see
381 * the value in kernel traces
382 */
383 #define OVERFLOW_FLAG_REG REG_A6XX_CP_SCRATCH_REG(0)
384
385 /*
386 * If overflow is detected, either 0x1 (VSC_DATA overflow) or 0x3
387 * (VSC_DATA2 overflow) plus the size of the overflowed buffer is
388 * written to control->vsc_overflow. This allows the CPU to
389 * detect which buffer overflowed (and, since the current size is
390 * encoded as well, this protects against already-submitted but
391 * not executed batches from fooling the CPU into increasing the
392 * size again unnecessarily).
393 *
394 * To conditionally use VSC data in draw pass only if there is no
395 * overflow, we use a scratch reg (OVERFLOW_FLAG_REG) to hold 1
396 * if no overflow, or 0 in case of overflow. The value is inverted
397 * to make the CP_COND_REG_EXEC stuff easier.
398 */
399 static void
400 emit_vsc_overflow_test(struct fd_batch *batch)
401 {
402 struct fd_ringbuffer *ring = batch->gmem;
403 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
404 struct fd6_context *fd6_ctx = fd6_context(batch->ctx);
405
406 debug_assert((fd6_ctx->vsc_data_pitch & 0x3) == 0);
407 debug_assert((fd6_ctx->vsc_data2_pitch & 0x3) == 0);
408
409 /* Clear vsc_scratch: */
410 OUT_PKT7(ring, CP_MEM_WRITE, 3);
411 OUT_RELOCW(ring, control_ptr(fd6_ctx, vsc_scratch));
412 OUT_RING(ring, 0x0);
413
414 /* Check for overflow, write vsc_scratch if detected: */
415 for (int i = 0; i < gmem->num_vsc_pipes; i++) {
416 OUT_PKT7(ring, CP_COND_WRITE5, 8);
417 OUT_RING(ring, CP_COND_WRITE5_0_FUNCTION(WRITE_GE) |
418 CP_COND_WRITE5_0_WRITE_MEMORY);
419 OUT_RING(ring, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_SIZE_REG(i)));
420 OUT_RING(ring, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
421 OUT_RING(ring, CP_COND_WRITE5_3_REF(fd6_ctx->vsc_data_pitch));
422 OUT_RING(ring, CP_COND_WRITE5_4_MASK(~0));
423 OUT_RELOCW(ring, control_ptr(fd6_ctx, vsc_scratch)); /* WRITE_ADDR_LO/HI */
424 OUT_RING(ring, CP_COND_WRITE5_7_WRITE_DATA(1 + fd6_ctx->vsc_data_pitch));
425
426 OUT_PKT7(ring, CP_COND_WRITE5, 8);
427 OUT_RING(ring, CP_COND_WRITE5_0_FUNCTION(WRITE_GE) |
428 CP_COND_WRITE5_0_WRITE_MEMORY);
429 OUT_RING(ring, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_SIZE2_REG(i)));
430 OUT_RING(ring, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
431 OUT_RING(ring, CP_COND_WRITE5_3_REF(fd6_ctx->vsc_data2_pitch));
432 OUT_RING(ring, CP_COND_WRITE5_4_MASK(~0));
433 OUT_RELOCW(ring, control_ptr(fd6_ctx, vsc_scratch)); /* WRITE_ADDR_LO/HI */
434 OUT_RING(ring, CP_COND_WRITE5_7_WRITE_DATA(3 + fd6_ctx->vsc_data2_pitch));
435 }
436
437 OUT_PKT7(ring, CP_WAIT_MEM_WRITES, 0);
438
439 OUT_PKT7(ring, CP_WAIT_FOR_ME, 0);
440
441 OUT_PKT7(ring, CP_MEM_TO_REG, 3);
442 OUT_RING(ring, CP_MEM_TO_REG_0_REG(OVERFLOW_FLAG_REG) |
443 CP_MEM_TO_REG_0_CNT(0));
444 OUT_RELOC(ring, control_ptr(fd6_ctx, vsc_scratch)); /* SRC_LO/HI */
445
446 /*
447 * This is a bit awkward, we really want a way to invert the
448 * CP_REG_TEST/CP_COND_REG_EXEC logic, so that we can conditionally
449 * execute cmds to use hwbinning when a bit is *not* set. This
450 * dance is to invert OVERFLOW_FLAG_REG
451 *
452 * A CP_NOP packet is used to skip executing the 'else' clause
453 * if (b0 set)..
454 */
455
456 BEGIN_RING(ring, 10); /* ensure if/else doesn't get split */
457
458 /* b0 will be set if VSC_DATA or VSC_DATA2 overflow: */
459 OUT_PKT7(ring, CP_REG_TEST, 1);
460 OUT_RING(ring, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG) |
461 A6XX_CP_REG_TEST_0_BIT(0) |
462 A6XX_CP_REG_TEST_0_WAIT_FOR_ME);
463
464 OUT_PKT7(ring, CP_COND_REG_EXEC, 2);
465 OUT_RING(ring, 0x10000000);
466 OUT_RING(ring, 7); /* conditionally execute next 7 dwords */
467
468 /* if (b0 set) */ {
469 /*
470 * On overflow, mirror the value to control->vsc_overflow
471 * which CPU is checking to detect overflow (see
472 * check_vsc_overflow())
473 */
474 OUT_PKT7(ring, CP_REG_TO_MEM, 3);
475 OUT_RING(ring, CP_REG_TO_MEM_0_REG(OVERFLOW_FLAG_REG) |
476 CP_REG_TO_MEM_0_CNT(1 - 1));
477 OUT_RELOCW(ring, control_ptr(fd6_ctx, vsc_overflow));
478
479 OUT_PKT4(ring, OVERFLOW_FLAG_REG, 1);
480 OUT_RING(ring, 0x0);
481
482 OUT_PKT7(ring, CP_NOP, 2); /* skip 'else' when 'if' is taken */
483 } /* else */ {
484 OUT_PKT4(ring, OVERFLOW_FLAG_REG, 1);
485 OUT_RING(ring, 0x1);
486 }
487 }
488
489 static void
490 check_vsc_overflow(struct fd_context *ctx)
491 {
492 struct fd6_context *fd6_ctx = fd6_context(ctx);
493 struct fd6_control *control = fd_bo_map(fd6_ctx->control_mem);
494 uint32_t vsc_overflow = control->vsc_overflow;
495
496 if (!vsc_overflow)
497 return;
498
499 /* clear overflow flag: */
500 control->vsc_overflow = 0;
501
502 unsigned buffer = vsc_overflow & 0x3;
503 unsigned size = vsc_overflow & ~0x3;
504
505 if (buffer == 0x1) {
506 /* VSC_PIPE_DATA overflow: */
507
508 if (size < fd6_ctx->vsc_data_pitch) {
509 /* we've already increased the size, this overflow is
510 * from a batch submitted before resize, but executed
511 * after
512 */
513 return;
514 }
515
516 fd_bo_del(fd6_ctx->vsc_data);
517 fd6_ctx->vsc_data = NULL;
518 fd6_ctx->vsc_data_pitch *= 2;
519
520 debug_printf("resized VSC_DATA_PITCH to: 0x%x\n", fd6_ctx->vsc_data_pitch);
521
522 } else if (buffer == 0x3) {
523 /* VSC_PIPE_DATA2 overflow: */
524
525 if (size < fd6_ctx->vsc_data2_pitch) {
526 /* we've already increased the size */
527 return;
528 }
529
530 fd_bo_del(fd6_ctx->vsc_data2);
531 fd6_ctx->vsc_data2 = NULL;
532 fd6_ctx->vsc_data2_pitch *= 2;
533
534 debug_printf("resized VSC_DATA2_PITCH to: 0x%x\n", fd6_ctx->vsc_data2_pitch);
535
536 } else {
537 /* NOTE: it's possible, for example, for overflow to corrupt the
538 * control page. I mostly just see this hit if I set initial VSC
539 * buffer size extremely small. Things still seem to recover,
540 * but maybe we should pre-emptively realloc vsc_data/vsc_data2
541 * and hope for different memory placement?
542 */
543 DBG("invalid vsc_overflow value: 0x%08x", vsc_overflow);
544 }
545 }
546
547 /*
548 * Emit conditional CP_INDIRECT_BRANCH based on VSC_STATE[p], ie. the IB
549 * is skipped for tiles that have no visible geometry.
550 */
551 static void
552 emit_conditional_ib(struct fd_batch *batch, struct fd_tile *tile,
553 struct fd_ringbuffer *target)
554 {
555 struct fd_ringbuffer *ring = batch->gmem;
556
557 if (target->cur == target->start)
558 return;
559
560 emit_marker6(ring, 6);
561
562 unsigned count = fd_ringbuffer_cmd_count(target);
563
564 BEGIN_RING(ring, 5 + 4 * count); /* ensure conditional doesn't get split */
565
566 OUT_PKT7(ring, CP_REG_TEST, 1);
567 OUT_RING(ring, A6XX_CP_REG_TEST_0_REG(REG_A6XX_VSC_STATE_REG(tile->p)) |
568 A6XX_CP_REG_TEST_0_BIT(tile->n) |
569 A6XX_CP_REG_TEST_0_WAIT_FOR_ME);
570
571 OUT_PKT7(ring, CP_COND_REG_EXEC, 2);
572 OUT_RING(ring, 0x10000000);
573 OUT_RING(ring, 4 * count); /* conditionally execute next 4*count dwords */
574
575 for (unsigned i = 0; i < count; i++) {
576 uint32_t dwords;
577 OUT_PKT7(ring, CP_INDIRECT_BUFFER, 3);
578 dwords = fd_ringbuffer_emit_reloc_ring_full(ring, target, i) / 4;
579 assert(dwords > 0);
580 OUT_RING(ring, dwords);
581 }
582
583 emit_marker6(ring, 6);
584 }
585
586 static void
587 set_scissor(struct fd_ringbuffer *ring, uint32_t x1, uint32_t y1, uint32_t x2, uint32_t y2)
588 {
589 OUT_REG(ring,
590 A6XX_GRAS_SC_WINDOW_SCISSOR_TL(.x = x1, .y = y1),
591 A6XX_GRAS_SC_WINDOW_SCISSOR_BR(.x = x2, .y = y2));
592
593 OUT_REG(ring,
594 A6XX_GRAS_RESOLVE_CNTL_1(.x = x1, .y = y1),
595 A6XX_GRAS_RESOLVE_CNTL_2(.x = x2, .y = y2));
596 }
597
598 static void
599 set_bin_size(struct fd_ringbuffer *ring, uint32_t w, uint32_t h, uint32_t flag)
600 {
601 OUT_REG(ring, A6XX_GRAS_BIN_CONTROL(.binw = w, .binh = h, .dword = flag));
602 OUT_REG(ring, A6XX_RB_BIN_CONTROL(.binw = w, .binh = h, .dword = flag));
603 /* no flag for RB_BIN_CONTROL2... */
604 OUT_REG(ring, A6XX_RB_BIN_CONTROL2(.binw = w, .binh = h));
605 }
606
607 static void
608 emit_binning_pass(struct fd_batch *batch)
609 {
610 struct fd_ringbuffer *ring = batch->gmem;
611 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
612 struct fd6_context *fd6_ctx = fd6_context(batch->ctx);
613
614 uint32_t x1 = gmem->minx;
615 uint32_t y1 = gmem->miny;
616 uint32_t x2 = gmem->minx + gmem->width - 1;
617 uint32_t y2 = gmem->miny + gmem->height - 1;
618
619 debug_assert(!batch->tessellation);
620
621 set_scissor(ring, x1, y1, x2, y2);
622
623 emit_marker6(ring, 7);
624 OUT_PKT7(ring, CP_SET_MARKER, 1);
625 OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_BINNING));
626 emit_marker6(ring, 7);
627
628 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
629 OUT_RING(ring, 0x1);
630
631 OUT_PKT7(ring, CP_SET_MODE, 1);
632 OUT_RING(ring, 0x1);
633
634 OUT_WFI5(ring);
635
636 OUT_REG(ring, A6XX_VFD_MODE_CNTL(.binning_pass = true));
637
638 update_vsc_pipe(batch);
639
640 OUT_PKT4(ring, REG_A6XX_PC_UNKNOWN_9805, 1);
641 OUT_RING(ring, fd6_ctx->magic.PC_UNKNOWN_9805);
642
643 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A0F8, 1);
644 OUT_RING(ring, fd6_ctx->magic.SP_UNKNOWN_A0F8);
645
646 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
647 OUT_RING(ring, UNK_2C);
648
649 OUT_PKT4(ring, REG_A6XX_RB_WINDOW_OFFSET, 1);
650 OUT_RING(ring, A6XX_RB_WINDOW_OFFSET_X(0) |
651 A6XX_RB_WINDOW_OFFSET_Y(0));
652
653 OUT_PKT4(ring, REG_A6XX_SP_TP_WINDOW_OFFSET, 1);
654 OUT_RING(ring, A6XX_SP_TP_WINDOW_OFFSET_X(0) |
655 A6XX_SP_TP_WINDOW_OFFSET_Y(0));
656
657 /* emit IB to binning drawcmds: */
658 fd6_emit_ib(ring, batch->draw);
659
660 fd_reset_wfi(batch);
661
662 OUT_PKT7(ring, CP_SET_DRAW_STATE, 3);
663 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
664 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
665 CP_SET_DRAW_STATE__0_GROUP_ID(0));
666 OUT_RING(ring, CP_SET_DRAW_STATE__1_ADDR_LO(0));
667 OUT_RING(ring, CP_SET_DRAW_STATE__2_ADDR_HI(0));
668
669 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
670 OUT_RING(ring, UNK_2D);
671
672 fd6_cache_inv(batch, ring);
673 fd6_cache_flush(batch, ring);
674 fd_wfi(batch, ring);
675
676 OUT_PKT7(ring, CP_WAIT_FOR_ME, 0);
677
678 emit_vsc_overflow_test(batch);
679
680 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
681 OUT_RING(ring, 0x0);
682
683 OUT_PKT7(ring, CP_SET_MODE, 1);
684 OUT_RING(ring, 0x0);
685
686 OUT_WFI5(ring);
687
688 OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
689 OUT_RING(ring, fd6_ctx->magic.RB_CCU_CNTL_gmem);
690 }
691
692 static void
693 emit_msaa(struct fd_ringbuffer *ring, unsigned nr)
694 {
695 enum a3xx_msaa_samples samples = fd_msaa_samples(nr);
696
697 OUT_PKT4(ring, REG_A6XX_SP_TP_RAS_MSAA_CNTL, 2);
698 OUT_RING(ring, A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(samples));
699 OUT_RING(ring, A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(samples) |
700 COND(samples == MSAA_ONE, A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE));
701
702 OUT_PKT4(ring, REG_A6XX_GRAS_RAS_MSAA_CNTL, 2);
703 OUT_RING(ring, A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(samples));
704 OUT_RING(ring, A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(samples) |
705 COND(samples == MSAA_ONE, A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE));
706
707 OUT_PKT4(ring, REG_A6XX_RB_RAS_MSAA_CNTL, 2);
708 OUT_RING(ring, A6XX_RB_RAS_MSAA_CNTL_SAMPLES(samples));
709 OUT_RING(ring, A6XX_RB_DEST_MSAA_CNTL_SAMPLES(samples) |
710 COND(samples == MSAA_ONE, A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE));
711
712 OUT_PKT4(ring, REG_A6XX_RB_MSAA_CNTL, 1);
713 OUT_RING(ring, A6XX_RB_MSAA_CNTL_SAMPLES(samples));
714 }
715
716 static void prepare_tile_setup_ib(struct fd_batch *batch);
717 static void prepare_tile_fini_ib(struct fd_batch *batch);
718
719 /* before first tile */
720 static void
721 fd6_emit_tile_init(struct fd_batch *batch)
722 {
723 struct fd_context *ctx = batch->ctx;
724 struct fd_ringbuffer *ring = batch->gmem;
725 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
726 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
727
728 fd6_emit_restore(batch, ring);
729
730 fd6_emit_lrz_flush(ring);
731
732 if (batch->lrz_clear)
733 fd6_emit_ib(ring, batch->lrz_clear);
734
735 fd6_cache_inv(batch, ring);
736
737 prepare_tile_setup_ib(batch);
738 prepare_tile_fini_ib(batch);
739
740 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
741 OUT_RING(ring, 0x0);
742
743 fd_wfi(batch, ring);
744 OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
745 OUT_RING(ring, fd6_context(ctx)->magic.RB_CCU_CNTL_gmem);
746
747 emit_zs(ring, pfb->zsbuf, &ctx->gmem);
748 emit_mrt(ring, pfb, &ctx->gmem);
749 emit_msaa(ring, pfb->samples);
750 patch_fb_read(batch);
751
752 if (use_hw_binning(batch)) {
753 /* enable stream-out during binning pass: */
754 OUT_PKT4(ring, REG_A6XX_VPC_SO_OVERRIDE, 1);
755 OUT_RING(ring, 0);
756
757 set_bin_size(ring, gmem->bin_w, gmem->bin_h,
758 A6XX_RB_BIN_CONTROL_BINNING_PASS | 0x6000000);
759 update_render_cntl(batch, pfb, true);
760 emit_binning_pass(batch);
761
762 /* and disable stream-out for draw pass: */
763 OUT_PKT4(ring, REG_A6XX_VPC_SO_OVERRIDE, 1);
764 OUT_RING(ring, A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
765
766 /*
767 * NOTE: even if we detect VSC overflow and disable use of
768 * visibility stream in draw pass, it is still safe to execute
769 * the reset of these cmds:
770 */
771
772 // NOTE a618 not setting .USE_VIZ .. from a quick check on a630, it
773 // does not appear that this bit changes much (ie. it isn't actually
774 // .USE_VIZ like previous gens)
775 set_bin_size(ring, gmem->bin_w, gmem->bin_h,
776 A6XX_RB_BIN_CONTROL_USE_VIZ | 0x6000000);
777
778 OUT_PKT4(ring, REG_A6XX_VFD_MODE_CNTL, 1);
779 OUT_RING(ring, 0x0);
780
781 OUT_PKT4(ring, REG_A6XX_PC_UNKNOWN_9805, 1);
782 OUT_RING(ring, fd6_context(ctx)->magic.PC_UNKNOWN_9805);
783
784 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A0F8, 1);
785 OUT_RING(ring, fd6_context(ctx)->magic.SP_UNKNOWN_A0F8);
786
787 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
788 OUT_RING(ring, 0x1);
789 } else {
790 /* no binning pass, so enable stream-out for draw pass:: */
791 OUT_PKT4(ring, REG_A6XX_VPC_SO_OVERRIDE, 1);
792 OUT_RING(ring, 0);
793
794 set_bin_size(ring, gmem->bin_w, gmem->bin_h, 0x6000000);
795 }
796
797 update_render_cntl(batch, pfb, false);
798 }
799
800 static void
801 set_window_offset(struct fd_ringbuffer *ring, uint32_t x1, uint32_t y1)
802 {
803 OUT_PKT4(ring, REG_A6XX_RB_WINDOW_OFFSET, 1);
804 OUT_RING(ring, A6XX_RB_WINDOW_OFFSET_X(x1) |
805 A6XX_RB_WINDOW_OFFSET_Y(y1));
806
807 OUT_PKT4(ring, REG_A6XX_RB_WINDOW_OFFSET2, 1);
808 OUT_RING(ring, A6XX_RB_WINDOW_OFFSET2_X(x1) |
809 A6XX_RB_WINDOW_OFFSET2_Y(y1));
810
811 OUT_PKT4(ring, REG_A6XX_SP_WINDOW_OFFSET, 1);
812 OUT_RING(ring, A6XX_SP_WINDOW_OFFSET_X(x1) |
813 A6XX_SP_WINDOW_OFFSET_Y(y1));
814
815 OUT_PKT4(ring, REG_A6XX_SP_TP_WINDOW_OFFSET, 1);
816 OUT_RING(ring, A6XX_SP_TP_WINDOW_OFFSET_X(x1) |
817 A6XX_SP_TP_WINDOW_OFFSET_Y(y1));
818 }
819
820 /* before mem2gmem */
821 static void
822 fd6_emit_tile_prep(struct fd_batch *batch, struct fd_tile *tile)
823 {
824 struct fd_context *ctx = batch->ctx;
825 struct fd6_context *fd6_ctx = fd6_context(ctx);
826 struct fd_ringbuffer *ring = batch->gmem;
827
828 emit_marker6(ring, 7);
829 OUT_PKT7(ring, CP_SET_MARKER, 1);
830 OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM) | 0x10);
831 emit_marker6(ring, 7);
832
833 uint32_t x1 = tile->xoff;
834 uint32_t y1 = tile->yoff;
835 uint32_t x2 = tile->xoff + tile->bin_w - 1;
836 uint32_t y2 = tile->yoff + tile->bin_h - 1;
837
838 set_scissor(ring, x1, y1, x2, y2);
839
840 if (use_hw_binning(batch)) {
841 struct fd_vsc_pipe *pipe = &ctx->vsc_pipe[tile->p];
842
843 OUT_PKT7(ring, CP_WAIT_FOR_ME, 0);
844
845 OUT_PKT7(ring, CP_SET_MODE, 1);
846 OUT_RING(ring, 0x0);
847
848 /*
849 * Conditionally execute if no VSC overflow:
850 */
851
852 BEGIN_RING(ring, 18); /* ensure if/else doesn't get split */
853
854 OUT_PKT7(ring, CP_REG_TEST, 1);
855 OUT_RING(ring, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG) |
856 A6XX_CP_REG_TEST_0_BIT(0) |
857 A6XX_CP_REG_TEST_0_WAIT_FOR_ME);
858
859 OUT_PKT7(ring, CP_COND_REG_EXEC, 2);
860 OUT_RING(ring, 0x10000000);
861 OUT_RING(ring, 11); /* conditionally execute next 11 dwords */
862
863 /* if (no overflow) */ {
864 OUT_PKT7(ring, CP_SET_BIN_DATA5, 7);
865 OUT_RING(ring, CP_SET_BIN_DATA5_0_VSC_SIZE(pipe->w * pipe->h) |
866 CP_SET_BIN_DATA5_0_VSC_N(tile->n));
867 OUT_RELOC(ring, fd6_ctx->vsc_data, /* VSC_PIPE[p].DATA_ADDRESS */
868 (tile->p * fd6_ctx->vsc_data_pitch), 0, 0);
869 OUT_RELOC(ring, fd6_ctx->vsc_data, /* VSC_SIZE_ADDRESS + (p * 4) */
870 (tile->p * 4) + (32 * fd6_ctx->vsc_data_pitch), 0, 0);
871 OUT_RELOC(ring, fd6_ctx->vsc_data2,
872 (tile->p * fd6_ctx->vsc_data2_pitch), 0, 0);
873
874 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
875 OUT_RING(ring, 0x0);
876
877 /* use a NOP packet to skip over the 'else' side: */
878 OUT_PKT7(ring, CP_NOP, 2);
879 } /* else */ {
880 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
881 OUT_RING(ring, 0x1);
882 }
883
884 set_window_offset(ring, x1, y1);
885
886 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
887 set_bin_size(ring, gmem->bin_w, gmem->bin_h, 0x6000000);
888
889 OUT_PKT7(ring, CP_SET_MODE, 1);
890 OUT_RING(ring, 0x0);
891
892 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8804, 1);
893 OUT_RING(ring, 0x0);
894
895 OUT_PKT4(ring, REG_A6XX_SP_TP_UNKNOWN_B304, 1);
896 OUT_RING(ring, 0x0);
897
898 OUT_PKT4(ring, REG_A6XX_GRAS_UNKNOWN_80A4, 1);
899 OUT_RING(ring, 0x0);
900 } else {
901 set_window_offset(ring, x1, y1);
902
903 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
904 OUT_RING(ring, 0x1);
905
906 OUT_PKT7(ring, CP_SET_MODE, 1);
907 OUT_RING(ring, 0x0);
908 }
909 }
910
911 static void
912 set_blit_scissor(struct fd_batch *batch, struct fd_ringbuffer *ring)
913 {
914 struct pipe_scissor_state blit_scissor;
915 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
916
917 blit_scissor.minx = 0;
918 blit_scissor.miny = 0;
919 blit_scissor.maxx = align(pfb->width, batch->ctx->screen->gmem_alignw);
920 blit_scissor.maxy = align(pfb->height, batch->ctx->screen->gmem_alignh);
921
922 OUT_PKT4(ring, REG_A6XX_RB_BLIT_SCISSOR_TL, 2);
923 OUT_RING(ring,
924 A6XX_RB_BLIT_SCISSOR_TL_X(blit_scissor.minx) |
925 A6XX_RB_BLIT_SCISSOR_TL_Y(blit_scissor.miny));
926 OUT_RING(ring,
927 A6XX_RB_BLIT_SCISSOR_BR_X(blit_scissor.maxx - 1) |
928 A6XX_RB_BLIT_SCISSOR_BR_Y(blit_scissor.maxy - 1));
929 }
930
931 static void
932 emit_blit(struct fd_batch *batch,
933 struct fd_ringbuffer *ring,
934 uint32_t base,
935 struct pipe_surface *psurf,
936 bool stencil)
937 {
938 struct fdl_slice *slice;
939 struct fd_resource *rsc = fd_resource(psurf->texture);
940 enum pipe_format pfmt = psurf->format;
941 uint32_t offset;
942 bool ubwc_enabled;
943
944 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
945
946 /* separate stencil case: */
947 if (stencil) {
948 rsc = rsc->stencil;
949 pfmt = rsc->base.format;
950 }
951
952 slice = fd_resource_slice(rsc, psurf->u.tex.level);
953 offset = fd_resource_offset(rsc, psurf->u.tex.level,
954 psurf->u.tex.first_layer);
955 ubwc_enabled = fd_resource_ubwc_enabled(rsc, psurf->u.tex.level);
956
957 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
958
959 enum a6xx_color_fmt format = fd6_pipe2color(pfmt);
960 uint32_t stride = slice->pitch * rsc->layout.cpp;
961 uint32_t size = slice->size0;
962 enum a3xx_color_swap swap = fd6_resource_swap(rsc, pfmt);
963 enum a3xx_msaa_samples samples =
964 fd_msaa_samples(rsc->base.nr_samples);
965 uint32_t tile_mode = fd_resource_tile_mode(&rsc->base, psurf->u.tex.level);
966
967 OUT_REG(ring,
968 A6XX_RB_BLIT_DST_INFO(.tile_mode = tile_mode, .samples = samples,
969 .color_format = format, .color_swap = swap, .flags = ubwc_enabled),
970 A6XX_RB_BLIT_DST(.bo = rsc->bo, .bo_offset = offset),
971 A6XX_RB_BLIT_DST_PITCH(.a6xx_rb_blit_dst_pitch = stride),
972 A6XX_RB_BLIT_DST_ARRAY_PITCH(.a6xx_rb_blit_dst_array_pitch = size));
973
974 OUT_REG(ring, A6XX_RB_BLIT_BASE_GMEM(.dword = base));
975
976 if (ubwc_enabled) {
977 OUT_PKT4(ring, REG_A6XX_RB_BLIT_FLAG_DST_LO, 3);
978 fd6_emit_flag_reference(ring, rsc,
979 psurf->u.tex.level, psurf->u.tex.first_layer);
980 }
981
982 fd6_emit_blit(batch, ring);
983 }
984
985 static void
986 emit_restore_blit(struct fd_batch *batch,
987 struct fd_ringbuffer *ring,
988 uint32_t base,
989 struct pipe_surface *psurf,
990 unsigned buffer)
991 {
992 bool stencil = (buffer == FD_BUFFER_STENCIL);
993
994 OUT_REG(ring, A6XX_RB_BLIT_INFO(
995 .gmem = true, .unk0 = true,
996 .depth = (buffer == FD_BUFFER_DEPTH),
997 .integer = util_format_is_pure_integer(psurf->format)));
998
999 emit_blit(batch, ring, base, psurf, stencil);
1000 }
1001
1002 static void
1003 emit_clears(struct fd_batch *batch, struct fd_ringbuffer *ring)
1004 {
1005 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
1006 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
1007 enum a3xx_msaa_samples samples = fd_msaa_samples(pfb->samples);
1008
1009 uint32_t buffers = batch->fast_cleared;
1010
1011 if (buffers & PIPE_CLEAR_COLOR) {
1012
1013 for (int i = 0; i < pfb->nr_cbufs; i++) {
1014 union pipe_color_union *color = &batch->clear_color[i];
1015 union util_color uc = {0};
1016
1017 if (!pfb->cbufs[i])
1018 continue;
1019
1020 if (!(buffers & (PIPE_CLEAR_COLOR0 << i)))
1021 continue;
1022
1023 enum pipe_format pfmt = pfb->cbufs[i]->format;
1024
1025 // XXX I think RB_CLEAR_COLOR_DWn wants to take into account SWAP??
1026 union pipe_color_union swapped;
1027 switch (fd6_pipe2swap(pfmt)) {
1028 case WZYX:
1029 swapped.ui[0] = color->ui[0];
1030 swapped.ui[1] = color->ui[1];
1031 swapped.ui[2] = color->ui[2];
1032 swapped.ui[3] = color->ui[3];
1033 break;
1034 case WXYZ:
1035 swapped.ui[2] = color->ui[0];
1036 swapped.ui[1] = color->ui[1];
1037 swapped.ui[0] = color->ui[2];
1038 swapped.ui[3] = color->ui[3];
1039 break;
1040 case ZYXW:
1041 swapped.ui[3] = color->ui[0];
1042 swapped.ui[0] = color->ui[1];
1043 swapped.ui[1] = color->ui[2];
1044 swapped.ui[2] = color->ui[3];
1045 break;
1046 case XYZW:
1047 swapped.ui[3] = color->ui[0];
1048 swapped.ui[2] = color->ui[1];
1049 swapped.ui[1] = color->ui[2];
1050 swapped.ui[0] = color->ui[3];
1051 break;
1052 }
1053
1054 if (util_format_is_pure_uint(pfmt)) {
1055 util_format_write_4ui(pfmt, swapped.ui, 0, &uc, 0, 0, 0, 1, 1);
1056 } else if (util_format_is_pure_sint(pfmt)) {
1057 util_format_write_4i(pfmt, swapped.i, 0, &uc, 0, 0, 0, 1, 1);
1058 } else {
1059 util_pack_color(swapped.f, pfmt, &uc);
1060 }
1061
1062 OUT_PKT4(ring, REG_A6XX_RB_BLIT_DST_INFO, 1);
1063 OUT_RING(ring, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR) |
1064 A6XX_RB_BLIT_DST_INFO_SAMPLES(samples) |
1065 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(fd6_pipe2color(pfmt)));
1066
1067 OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
1068 OUT_RING(ring, A6XX_RB_BLIT_INFO_GMEM |
1069 A6XX_RB_BLIT_INFO_CLEAR_MASK(0xf));
1070
1071 OUT_PKT4(ring, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
1072 OUT_RING(ring, gmem->cbuf_base[i]);
1073
1074 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_88D0, 1);
1075 OUT_RING(ring, 0);
1076
1077 OUT_PKT4(ring, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 4);
1078 OUT_RING(ring, uc.ui[0]);
1079 OUT_RING(ring, uc.ui[1]);
1080 OUT_RING(ring, uc.ui[2]);
1081 OUT_RING(ring, uc.ui[3]);
1082
1083 fd6_emit_blit(batch, ring);
1084 }
1085 }
1086
1087 const bool has_depth = pfb->zsbuf;
1088 const bool has_separate_stencil =
1089 has_depth && fd_resource(pfb->zsbuf->texture)->stencil;
1090
1091 /* First clear depth or combined depth/stencil. */
1092 if ((has_depth && (buffers & PIPE_CLEAR_DEPTH)) ||
1093 (!has_separate_stencil && (buffers & PIPE_CLEAR_STENCIL))) {
1094 enum pipe_format pfmt = pfb->zsbuf->format;
1095 uint32_t clear_value;
1096 uint32_t mask = 0;
1097
1098 if (has_separate_stencil) {
1099 pfmt = util_format_get_depth_only(pfb->zsbuf->format);
1100 clear_value = util_pack_z(pfmt, batch->clear_depth);
1101 } else {
1102 pfmt = pfb->zsbuf->format;
1103 clear_value = util_pack_z_stencil(pfmt, batch->clear_depth,
1104 batch->clear_stencil);
1105 }
1106
1107 if (buffers & PIPE_CLEAR_DEPTH)
1108 mask |= 0x1;
1109
1110 if (!has_separate_stencil && (buffers & PIPE_CLEAR_STENCIL))
1111 mask |= 0x2;
1112
1113 OUT_PKT4(ring, REG_A6XX_RB_BLIT_DST_INFO, 1);
1114 OUT_RING(ring, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR) |
1115 A6XX_RB_BLIT_DST_INFO_SAMPLES(samples) |
1116 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(fd6_pipe2color(pfmt)));
1117
1118 OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
1119 OUT_RING(ring, A6XX_RB_BLIT_INFO_GMEM |
1120 // XXX UNK0 for separate stencil ??
1121 A6XX_RB_BLIT_INFO_DEPTH |
1122 A6XX_RB_BLIT_INFO_CLEAR_MASK(mask));
1123
1124 OUT_PKT4(ring, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
1125 OUT_RING(ring, gmem->zsbuf_base[0]);
1126
1127 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_88D0, 1);
1128 OUT_RING(ring, 0);
1129
1130 OUT_PKT4(ring, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 1);
1131 OUT_RING(ring, clear_value);
1132
1133 fd6_emit_blit(batch, ring);
1134 }
1135
1136 /* Then clear the separate stencil buffer in case of 32 bit depth
1137 * formats with separate stencil. */
1138 if (has_separate_stencil && (buffers & PIPE_CLEAR_STENCIL)) {
1139 OUT_PKT4(ring, REG_A6XX_RB_BLIT_DST_INFO, 1);
1140 OUT_RING(ring, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR) |
1141 A6XX_RB_BLIT_DST_INFO_SAMPLES(samples) |
1142 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(RB6_R8_UINT));
1143
1144 OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
1145 OUT_RING(ring, A6XX_RB_BLIT_INFO_GMEM |
1146 //A6XX_RB_BLIT_INFO_UNK0 |
1147 A6XX_RB_BLIT_INFO_DEPTH |
1148 A6XX_RB_BLIT_INFO_CLEAR_MASK(0x1));
1149
1150 OUT_PKT4(ring, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
1151 OUT_RING(ring, gmem->zsbuf_base[1]);
1152
1153 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_88D0, 1);
1154 OUT_RING(ring, 0);
1155
1156 OUT_PKT4(ring, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 1);
1157 OUT_RING(ring, batch->clear_stencil & 0xff);
1158
1159 fd6_emit_blit(batch, ring);
1160 }
1161 }
1162
1163 /*
1164 * transfer from system memory to gmem
1165 */
1166 static void
1167 emit_restore_blits(struct fd_batch *batch, struct fd_ringbuffer *ring)
1168 {
1169 struct fd_context *ctx = batch->ctx;
1170 struct fd_gmem_stateobj *gmem = &ctx->gmem;
1171 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
1172
1173 if (batch->restore & FD_BUFFER_COLOR) {
1174 unsigned i;
1175 for (i = 0; i < pfb->nr_cbufs; i++) {
1176 if (!pfb->cbufs[i])
1177 continue;
1178 if (!(batch->restore & (PIPE_CLEAR_COLOR0 << i)))
1179 continue;
1180 emit_restore_blit(batch, ring, gmem->cbuf_base[i], pfb->cbufs[i],
1181 FD_BUFFER_COLOR);
1182 }
1183 }
1184
1185 if (batch->restore & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
1186 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
1187
1188 if (!rsc->stencil || (batch->restore & FD_BUFFER_DEPTH)) {
1189 emit_restore_blit(batch, ring, gmem->zsbuf_base[0], pfb->zsbuf,
1190 FD_BUFFER_DEPTH);
1191 }
1192 if (rsc->stencil && (batch->restore & FD_BUFFER_STENCIL)) {
1193 emit_restore_blit(batch, ring, gmem->zsbuf_base[1], pfb->zsbuf,
1194 FD_BUFFER_STENCIL);
1195 }
1196 }
1197 }
1198
1199 static void
1200 prepare_tile_setup_ib(struct fd_batch *batch)
1201 {
1202 batch->tile_setup = fd_submit_new_ringbuffer(batch->submit, 0x1000,
1203 FD_RINGBUFFER_STREAMING);
1204
1205 set_blit_scissor(batch, batch->tile_setup);
1206
1207 emit_restore_blits(batch, batch->tile_setup);
1208 emit_clears(batch, batch->tile_setup);
1209 }
1210
1211 /*
1212 * transfer from system memory to gmem
1213 */
1214 static void
1215 fd6_emit_tile_mem2gmem(struct fd_batch *batch, struct fd_tile *tile)
1216 {
1217 }
1218
1219 /* before IB to rendering cmds: */
1220 static void
1221 fd6_emit_tile_renderprep(struct fd_batch *batch, struct fd_tile *tile)
1222 {
1223 if (batch->fast_cleared || !use_hw_binning(batch)) {
1224 fd6_emit_ib(batch->gmem, batch->tile_setup);
1225 } else {
1226 emit_conditional_ib(batch, tile, batch->tile_setup);
1227 }
1228 }
1229
1230 static void
1231 emit_resolve_blit(struct fd_batch *batch,
1232 struct fd_ringbuffer *ring,
1233 uint32_t base,
1234 struct pipe_surface *psurf,
1235 unsigned buffer)
1236 {
1237 uint32_t info = 0;
1238 bool stencil = false;
1239
1240 if (!fd_resource(psurf->texture)->valid)
1241 return;
1242
1243 switch (buffer) {
1244 case FD_BUFFER_COLOR:
1245 break;
1246 case FD_BUFFER_STENCIL:
1247 info |= A6XX_RB_BLIT_INFO_UNK0;
1248 stencil = true;
1249 break;
1250 case FD_BUFFER_DEPTH:
1251 info |= A6XX_RB_BLIT_INFO_DEPTH;
1252 break;
1253 }
1254
1255 if (util_format_is_pure_integer(psurf->format))
1256 info |= A6XX_RB_BLIT_INFO_INTEGER;
1257
1258 OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
1259 OUT_RING(ring, info);
1260
1261 emit_blit(batch, ring, base, psurf, stencil);
1262 }
1263
1264 /*
1265 * transfer from gmem to system memory (ie. normal RAM)
1266 */
1267
1268 static void
1269 prepare_tile_fini_ib(struct fd_batch *batch)
1270 {
1271 struct fd_context *ctx = batch->ctx;
1272 struct fd_gmem_stateobj *gmem = &ctx->gmem;
1273 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
1274 struct fd_ringbuffer *ring;
1275
1276 batch->tile_fini = fd_submit_new_ringbuffer(batch->submit, 0x1000,
1277 FD_RINGBUFFER_STREAMING);
1278 ring = batch->tile_fini;
1279
1280 set_blit_scissor(batch, ring);
1281
1282 if (batch->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
1283 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
1284
1285 if (!rsc->stencil || (batch->resolve & FD_BUFFER_DEPTH)) {
1286 emit_resolve_blit(batch, ring,
1287 gmem->zsbuf_base[0], pfb->zsbuf,
1288 FD_BUFFER_DEPTH);
1289 }
1290 if (rsc->stencil && (batch->resolve & FD_BUFFER_STENCIL)) {
1291 emit_resolve_blit(batch, ring,
1292 gmem->zsbuf_base[1], pfb->zsbuf,
1293 FD_BUFFER_STENCIL);
1294 }
1295 }
1296
1297 if (batch->resolve & FD_BUFFER_COLOR) {
1298 unsigned i;
1299 for (i = 0; i < pfb->nr_cbufs; i++) {
1300 if (!pfb->cbufs[i])
1301 continue;
1302 if (!(batch->resolve & (PIPE_CLEAR_COLOR0 << i)))
1303 continue;
1304 emit_resolve_blit(batch, ring, gmem->cbuf_base[i], pfb->cbufs[i],
1305 FD_BUFFER_COLOR);
1306 }
1307 }
1308 }
1309
1310 static void
1311 fd6_emit_tile(struct fd_batch *batch, struct fd_tile *tile)
1312 {
1313 if (!use_hw_binning(batch)) {
1314 fd6_emit_ib(batch->gmem, batch->draw);
1315 } else {
1316 emit_conditional_ib(batch, tile, batch->draw);
1317 }
1318 }
1319
1320 static void
1321 fd6_emit_tile_gmem2mem(struct fd_batch *batch, struct fd_tile *tile)
1322 {
1323 struct fd_ringbuffer *ring = batch->gmem;
1324
1325 if (use_hw_binning(batch)) {
1326 /* Conditionally execute if no VSC overflow: */
1327
1328 BEGIN_RING(ring, 7); /* ensure if/else doesn't get split */
1329
1330 OUT_PKT7(ring, CP_REG_TEST, 1);
1331 OUT_RING(ring, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG) |
1332 A6XX_CP_REG_TEST_0_BIT(0) |
1333 A6XX_CP_REG_TEST_0_WAIT_FOR_ME);
1334
1335 OUT_PKT7(ring, CP_COND_REG_EXEC, 2);
1336 OUT_RING(ring, 0x10000000);
1337 OUT_RING(ring, 2); /* conditionally execute next 2 dwords */
1338
1339 /* if (no overflow) */ {
1340 OUT_PKT7(ring, CP_SET_MARKER, 1);
1341 OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(0x5) | 0x10);
1342 }
1343 }
1344
1345 OUT_PKT7(ring, CP_SET_DRAW_STATE, 3);
1346 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
1347 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
1348 CP_SET_DRAW_STATE__0_GROUP_ID(0));
1349 OUT_RING(ring, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1350 OUT_RING(ring, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1351
1352 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_LOCAL, 1);
1353 OUT_RING(ring, 0x0);
1354
1355 emit_marker6(ring, 7);
1356 OUT_PKT7(ring, CP_SET_MARKER, 1);
1357 OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE) | 0x10);
1358 emit_marker6(ring, 7);
1359
1360 if (batch->fast_cleared || !use_hw_binning(batch)) {
1361 fd6_emit_ib(batch->gmem, batch->tile_fini);
1362 } else {
1363 emit_conditional_ib(batch, tile, batch->tile_fini);
1364 }
1365
1366 OUT_PKT7(ring, CP_SET_MARKER, 1);
1367 OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(0x7));
1368 }
1369
1370 static void
1371 fd6_emit_tile_fini(struct fd_batch *batch)
1372 {
1373 struct fd_ringbuffer *ring = batch->gmem;
1374
1375 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_CNTL, 1);
1376 OUT_RING(ring, A6XX_GRAS_LRZ_CNTL_ENABLE | A6XX_GRAS_LRZ_CNTL_UNK3);
1377
1378 fd6_emit_lrz_flush(ring);
1379
1380 fd6_event_write(batch, ring, CACHE_FLUSH_TS, true);
1381
1382 if (use_hw_binning(batch)) {
1383 check_vsc_overflow(batch->ctx);
1384 }
1385 }
1386
1387 static void
1388 emit_sysmem_clears(struct fd_batch *batch, struct fd_ringbuffer *ring)
1389 {
1390 struct fd_context *ctx = batch->ctx;
1391 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
1392
1393 uint32_t buffers = batch->fast_cleared;
1394
1395 if (buffers & PIPE_CLEAR_COLOR) {
1396 for (int i = 0; i < pfb->nr_cbufs; i++) {
1397 union pipe_color_union *color = &batch->clear_color[i];
1398
1399 if (!pfb->cbufs[i])
1400 continue;
1401
1402 if (!(buffers & (PIPE_CLEAR_COLOR0 << i)))
1403 continue;
1404
1405 fd6_clear_surface(ctx, ring,
1406 pfb->cbufs[i], pfb->width, pfb->height, color);
1407 }
1408 }
1409 if (buffers & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL)) {
1410 union pipe_color_union value = {};
1411
1412 const bool has_depth = pfb->zsbuf;
1413 struct pipe_resource *separate_stencil =
1414 has_depth && fd_resource(pfb->zsbuf->texture)->stencil ?
1415 &fd_resource(pfb->zsbuf->texture)->stencil->base : NULL;
1416
1417 if ((has_depth && (buffers & PIPE_CLEAR_DEPTH)) ||
1418 (!separate_stencil && (buffers & PIPE_CLEAR_STENCIL))) {
1419 value.f[0] = batch->clear_depth;
1420 value.ui[1] = batch->clear_stencil;
1421 fd6_clear_surface(ctx, ring,
1422 pfb->zsbuf, pfb->width, pfb->height, &value);
1423 }
1424
1425 if (separate_stencil && (buffers & PIPE_CLEAR_STENCIL)) {
1426 value.ui[0] = batch->clear_stencil;
1427
1428 struct pipe_surface stencil_surf = *pfb->zsbuf;
1429 stencil_surf.texture = separate_stencil;
1430
1431 fd6_clear_surface(ctx, ring,
1432 &stencil_surf, pfb->width, pfb->height, &value);
1433 }
1434 }
1435
1436 fd6_event_write(batch, ring, 0x1d, true);
1437 }
1438
1439 static void
1440 setup_tess_buffers(struct fd_batch *batch, struct fd_ringbuffer *ring)
1441 {
1442 struct fd_context *ctx = batch->ctx;
1443
1444 batch->tessfactor_bo = fd_bo_new(ctx->screen->dev,
1445 batch->tessfactor_size,
1446 DRM_FREEDRENO_GEM_TYPE_KMEM, "tessfactor");
1447
1448 batch->tessparam_bo = fd_bo_new(ctx->screen->dev,
1449 batch->tessparam_size,
1450 DRM_FREEDRENO_GEM_TYPE_KMEM, "tessparam");
1451
1452 OUT_PKT4(ring, REG_A6XX_PC_TESSFACTOR_ADDR_LO, 2);
1453 OUT_RELOCW(ring, batch->tessfactor_bo, 0, 0, 0);
1454
1455 batch->tess_addrs_constobj->cur = batch->tess_addrs_constobj->start;
1456 OUT_RELOCW(batch->tess_addrs_constobj, batch->tessparam_bo, 0, 0, 0);
1457 OUT_RELOCW(batch->tess_addrs_constobj, batch->tessfactor_bo, 0, 0, 0);
1458 }
1459
1460 static void
1461 fd6_emit_sysmem_prep(struct fd_batch *batch)
1462 {
1463 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
1464 struct fd_ringbuffer *ring = batch->gmem;
1465
1466 fd6_emit_restore(batch, ring);
1467
1468 if (pfb->width > 0 && pfb->height > 0)
1469 set_scissor(ring, 0, 0, pfb->width - 1, pfb->height - 1);
1470 else
1471 set_scissor(ring, 0, 0, 0, 0);
1472
1473 set_window_offset(ring, 0, 0);
1474
1475 set_bin_size(ring, 0, 0, 0xc00000); /* 0xc00000 = BYPASS? */
1476
1477 emit_sysmem_clears(batch, ring);
1478
1479 fd6_emit_lrz_flush(ring);
1480
1481 emit_marker6(ring, 7);
1482 OUT_PKT7(ring, CP_SET_MARKER, 1);
1483 OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_BYPASS) | 0x10); /* | 0x10 ? */
1484 emit_marker6(ring, 7);
1485
1486 if (batch->tessellation)
1487 setup_tess_buffers(batch, ring);
1488
1489 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1490 OUT_RING(ring, 0x0);
1491
1492 fd6_event_write(batch, ring, PC_CCU_INVALIDATE_COLOR, false);
1493 fd6_cache_inv(batch, ring);
1494
1495 fd_wfi(batch, ring);
1496 OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
1497 OUT_RING(ring, fd6_context(batch->ctx)->magic.RB_CCU_CNTL_bypass);
1498
1499 /* enable stream-out, with sysmem there is only one pass: */
1500 OUT_PKT4(ring, REG_A6XX_VPC_SO_OVERRIDE, 1);
1501 OUT_RING(ring, 0);
1502
1503 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
1504 OUT_RING(ring, 0x1);
1505
1506 emit_zs(ring, pfb->zsbuf, NULL);
1507 emit_mrt(ring, pfb, NULL);
1508 emit_msaa(ring, pfb->samples);
1509
1510 update_render_cntl(batch, pfb, false);
1511 }
1512
1513 static void
1514 fd6_emit_sysmem_fini(struct fd_batch *batch)
1515 {
1516 struct fd_ringbuffer *ring = batch->gmem;
1517
1518 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1519 OUT_RING(ring, 0x0);
1520
1521 fd6_emit_lrz_flush(ring);
1522
1523 fd6_event_write(batch, ring, UNK_1D, true);
1524 }
1525
1526 void
1527 fd6_gmem_init(struct pipe_context *pctx)
1528 {
1529 struct fd_context *ctx = fd_context(pctx);
1530
1531 ctx->emit_tile_init = fd6_emit_tile_init;
1532 ctx->emit_tile_prep = fd6_emit_tile_prep;
1533 ctx->emit_tile_mem2gmem = fd6_emit_tile_mem2gmem;
1534 ctx->emit_tile_renderprep = fd6_emit_tile_renderprep;
1535 ctx->emit_tile = fd6_emit_tile;
1536 ctx->emit_tile_gmem2mem = fd6_emit_tile_gmem2mem;
1537 ctx->emit_tile_fini = fd6_emit_tile_fini;
1538 ctx->emit_sysmem_prep = fd6_emit_sysmem_prep;
1539 ctx->emit_sysmem_fini = fd6_emit_sysmem_fini;
1540 }