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a6xx: Add more CP packets
[mesa.git] / src / gallium / drivers / freedreno / a6xx / fd6_gmem.c
1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 * Authors:
25 * Rob Clark <robclark@freedesktop.org>
26 */
27
28 #include <stdio.h>
29
30 #include "pipe/p_state.h"
31 #include "util/u_string.h"
32 #include "util/u_memory.h"
33 #include "util/u_inlines.h"
34 #include "util/format/u_format.h"
35
36 #include "freedreno_draw.h"
37 #include "freedreno_state.h"
38 #include "freedreno_resource.h"
39
40 #include "fd6_blitter.h"
41 #include "fd6_gmem.h"
42 #include "fd6_context.h"
43 #include "fd6_draw.h"
44 #include "fd6_emit.h"
45 #include "fd6_program.h"
46 #include "fd6_format.h"
47 #include "fd6_resource.h"
48 #include "fd6_zsa.h"
49 #include "fd6_pack.h"
50
51 /**
52 * Emits the flags registers, suitable for RB_MRT_FLAG_BUFFER,
53 * RB_DEPTH_FLAG_BUFFER, SP_PS_2D_SRC_FLAGS, and RB_BLIT_FLAG_DST.
54 */
55 void
56 fd6_emit_flag_reference(struct fd_ringbuffer *ring, struct fd_resource *rsc,
57 int level, int layer)
58 {
59 if (fd_resource_ubwc_enabled(rsc, level)) {
60 OUT_RELOCW(ring, rsc->bo, fd_resource_ubwc_offset(rsc, level, layer), 0, 0);
61 OUT_RING(ring,
62 A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(rsc->layout.ubwc_slices[level].pitch) |
63 A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(rsc->layout.ubwc_size));
64 } else {
65 OUT_RING(ring, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_LO */
66 OUT_RING(ring, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_HI */
67 OUT_RING(ring, 0x00000000);
68 }
69 }
70
71 static void
72 emit_mrt(struct fd_ringbuffer *ring, struct pipe_framebuffer_state *pfb,
73 struct fd_gmem_stateobj *gmem)
74 {
75 unsigned char mrt_comp[A6XX_MAX_RENDER_TARGETS] = {0};
76 unsigned srgb_cntl = 0;
77 unsigned i;
78
79 bool layered = false;
80 unsigned type = 0;
81
82 for (i = 0; i < pfb->nr_cbufs; i++) {
83 enum a6xx_color_fmt format = 0;
84 enum a3xx_color_swap swap = WZYX;
85 bool sint = false, uint = false;
86 struct fd_resource *rsc = NULL;
87 struct fdl_slice *slice = NULL;
88 uint32_t stride = 0;
89 uint32_t offset;
90 uint32_t tile_mode;
91
92 if (!pfb->cbufs[i])
93 continue;
94
95 mrt_comp[i] = 0xf;
96
97 struct pipe_surface *psurf = pfb->cbufs[i];
98 enum pipe_format pformat = psurf->format;
99 rsc = fd_resource(psurf->texture);
100 if (!rsc->bo)
101 continue;
102
103 uint32_t base = gmem ? gmem->cbuf_base[i] : 0;
104 slice = fd_resource_slice(rsc, psurf->u.tex.level);
105 format = fd6_pipe2color(pformat);
106 sint = util_format_is_pure_sint(pformat);
107 uint = util_format_is_pure_uint(pformat);
108
109 if (util_format_is_srgb(pformat))
110 srgb_cntl |= (1 << i);
111
112 offset = fd_resource_offset(rsc, psurf->u.tex.level,
113 psurf->u.tex.first_layer);
114
115 stride = slice->pitch * rsc->layout.cpp * pfb->samples;
116 swap = rsc->layout.tile_mode ? WZYX : fd6_pipe2swap(pformat);
117
118 tile_mode = fd_resource_tile_mode(psurf->texture, psurf->u.tex.level);
119
120 if (psurf->u.tex.first_layer < psurf->u.tex.last_layer) {
121 layered = true;
122 if (psurf->texture->target == PIPE_TEXTURE_2D_ARRAY && psurf->texture->nr_samples > 0)
123 type = LAYER_MULTISAMPLE_ARRAY;
124 else if (psurf->texture->target == PIPE_TEXTURE_2D_ARRAY)
125 type = LAYER_2D_ARRAY;
126 else if (psurf->texture->target == PIPE_TEXTURE_CUBE)
127 type = LAYER_CUBEMAP;
128 else if (psurf->texture->target == PIPE_TEXTURE_3D)
129 type = LAYER_3D;
130
131 stride /= pfb->samples;
132 }
133
134 debug_assert((offset + slice->size0) <= fd_bo_size(rsc->bo));
135
136 OUT_REG(ring,
137 A6XX_RB_MRT_BUF_INFO(i,
138 .color_format = format,
139 .color_tile_mode = tile_mode,
140 .color_swap = swap),
141 A6XX_RB_MRT_PITCH(i, .a6xx_rb_mrt_pitch = stride),
142 A6XX_RB_MRT_ARRAY_PITCH(i, .a6xx_rb_mrt_array_pitch = slice->size0),
143 A6XX_RB_MRT_BASE(i, .bo = rsc->bo, .bo_offset = offset),
144 A6XX_RB_MRT_BASE_GMEM(i, .unknown = base));
145
146 OUT_REG(ring,
147 A6XX_SP_FS_MRT_REG(i, .color_format = format,
148 .color_sint = sint, .color_uint = uint));
149
150 OUT_PKT4(ring, REG_A6XX_RB_MRT_FLAG_BUFFER(i), 3);
151 fd6_emit_flag_reference(ring, rsc,
152 psurf->u.tex.level, psurf->u.tex.first_layer);
153 }
154
155 OUT_REG(ring, A6XX_RB_SRGB_CNTL(.dword = srgb_cntl));
156 OUT_REG(ring, A6XX_SP_SRGB_CNTL(.dword = srgb_cntl));
157
158 OUT_REG(ring, A6XX_RB_RENDER_COMPONENTS(
159 .rt0 = mrt_comp[0],
160 .rt1 = mrt_comp[1],
161 .rt2 = mrt_comp[2],
162 .rt3 = mrt_comp[3],
163 .rt4 = mrt_comp[4],
164 .rt5 = mrt_comp[5],
165 .rt6 = mrt_comp[6],
166 .rt7 = mrt_comp[7]));
167
168 OUT_REG(ring, A6XX_SP_FS_RENDER_COMPONENTS(
169 .rt0 = mrt_comp[0],
170 .rt1 = mrt_comp[1],
171 .rt2 = mrt_comp[2],
172 .rt3 = mrt_comp[3],
173 .rt4 = mrt_comp[4],
174 .rt5 = mrt_comp[5],
175 .rt6 = mrt_comp[6],
176 .rt7 = mrt_comp[7]));
177
178 OUT_REG(ring, A6XX_GRAS_LAYER_CNTL(.layered = layered, .type = type));
179 }
180
181 static void
182 emit_zs(struct fd_ringbuffer *ring, struct pipe_surface *zsbuf,
183 struct fd_gmem_stateobj *gmem)
184 {
185 if (zsbuf) {
186 struct fd_resource *rsc = fd_resource(zsbuf->texture);
187 enum a6xx_depth_format fmt = fd6_pipe2depth(zsbuf->format);
188 struct fdl_slice *slice = fd_resource_slice(rsc, 0);
189 uint32_t stride = slice->pitch * rsc->layout.cpp;
190 uint32_t size = slice->size0;
191 uint32_t base = gmem ? gmem->zsbuf_base[0] : 0;
192 uint32_t offset = fd_resource_offset(rsc, zsbuf->u.tex.level,
193 zsbuf->u.tex.first_layer);
194
195 OUT_REG(ring,
196 A6XX_RB_DEPTH_BUFFER_INFO(.depth_format = fmt),
197 A6XX_RB_DEPTH_BUFFER_PITCH(.a6xx_rb_depth_buffer_pitch = stride),
198 A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(.a6xx_rb_depth_buffer_array_pitch = size),
199 A6XX_RB_DEPTH_BUFFER_BASE(.bo = rsc->bo, .bo_offset = offset),
200 A6XX_RB_DEPTH_BUFFER_BASE_GMEM(.dword = base));
201
202 OUT_REG(ring, A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format = fmt));
203
204 OUT_PKT4(ring, REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO, 3);
205 fd6_emit_flag_reference(ring, rsc,
206 zsbuf->u.tex.level, zsbuf->u.tex.first_layer);
207
208 if (rsc->lrz) {
209 OUT_REG(ring,
210 A6XX_GRAS_LRZ_BUFFER_BASE(.bo = rsc->lrz),
211 A6XX_GRAS_LRZ_BUFFER_PITCH(.pitch = rsc->lrz_pitch),
212 // XXX a6xx seems to use a different buffer here.. not sure what for..
213 A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO(0),
214 A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI(0));
215 } else {
216 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO, 5);
217 OUT_RING(ring, 0x00000000);
218 OUT_RING(ring, 0x00000000);
219 OUT_RING(ring, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
220 OUT_RING(ring, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO */
221 OUT_RING(ring, 0x00000000);
222 }
223
224 /* NOTE: blob emits GRAS_LRZ_CNTL plus GRAZ_LRZ_BUFFER_BASE
225 * plus this CP_EVENT_WRITE at the end in it's own IB..
226 */
227 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
228 OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(UNK_25));
229
230 if (rsc->stencil) {
231 struct fdl_slice *slice = fd_resource_slice(rsc->stencil, 0);
232 stride = slice->pitch * rsc->stencil->layout.cpp;
233 size = slice->size0;
234 uint32_t base = gmem ? gmem->zsbuf_base[1] : 0;
235
236 OUT_REG(ring,
237 A6XX_RB_STENCIL_INFO(.separate_stencil = true),
238 A6XX_RB_STENCIL_BUFFER_PITCH(.a6xx_rb_stencil_buffer_pitch = stride),
239 A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(.a6xx_rb_stencil_buffer_array_pitch = size),
240 A6XX_RB_STENCIL_BUFFER_BASE(.bo = rsc->stencil->bo),
241 A6XX_RB_STENCIL_BUFFER_BASE_GMEM(.dword = base));
242 } else {
243 OUT_REG(ring, A6XX_RB_STENCIL_INFO(0));
244 }
245 } else {
246 OUT_PKT4(ring, REG_A6XX_RB_DEPTH_BUFFER_INFO, 6);
247 OUT_RING(ring, A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH6_NONE));
248 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_PITCH */
249 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_ARRAY_PITCH */
250 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_BASE_LO */
251 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_BASE_HI */
252 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_BASE_GMEM */
253
254 OUT_REG(ring, A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format = DEPTH6_NONE));
255
256 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO, 5);
257 OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
258 OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
259 OUT_RING(ring, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
260 OUT_RING(ring, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO */
261 OUT_RING(ring, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI */
262
263 OUT_REG(ring, A6XX_RB_STENCIL_INFO(0));
264 }
265 }
266
267 static bool
268 use_hw_binning(struct fd_batch *batch)
269 {
270 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
271
272 // TODO figure out hw limits for binning
273
274 return fd_binning_enabled && ((gmem->nbins_x * gmem->nbins_y) >= 2) &&
275 (batch->num_draws > 0);
276 }
277
278 static void
279 patch_fb_read(struct fd_batch *batch)
280 {
281 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
282
283 for (unsigned i = 0; i < fd_patch_num_elements(&batch->fb_read_patches); i++) {
284 struct fd_cs_patch *patch = fd_patch_element(&batch->fb_read_patches, i);
285 *patch->cs = patch->val | A6XX_TEX_CONST_2_PITCH(gmem->bin_w * gmem->cbuf_cpp[0]);
286 }
287 util_dynarray_clear(&batch->fb_read_patches);
288 }
289
290 static void
291 update_render_cntl(struct fd_batch *batch, struct pipe_framebuffer_state *pfb, bool binning)
292 {
293 struct fd_ringbuffer *ring = batch->gmem;
294 uint32_t cntl = 0;
295 bool depth_ubwc_enable = false;
296 uint32_t mrts_ubwc_enable = 0;
297 int i;
298
299 if (pfb->zsbuf) {
300 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
301 depth_ubwc_enable = fd_resource_ubwc_enabled(rsc, pfb->zsbuf->u.tex.level);
302 }
303
304 for (i = 0; i < pfb->nr_cbufs; i++) {
305 if (!pfb->cbufs[i])
306 continue;
307
308 struct pipe_surface *psurf = pfb->cbufs[i];
309 struct fd_resource *rsc = fd_resource(psurf->texture);
310 if (!rsc->bo)
311 continue;
312
313 if (fd_resource_ubwc_enabled(rsc, psurf->u.tex.level))
314 mrts_ubwc_enable |= 1 << i;
315 }
316
317 cntl |= A6XX_RB_RENDER_CNTL_UNK4;
318 if (binning)
319 cntl |= A6XX_RB_RENDER_CNTL_BINNING;
320
321 OUT_PKT7(ring, CP_REG_WRITE, 3);
322 OUT_RING(ring, 0x2);
323 OUT_RING(ring, REG_A6XX_RB_RENDER_CNTL);
324 OUT_RING(ring, cntl |
325 COND(depth_ubwc_enable, A6XX_RB_RENDER_CNTL_FLAG_DEPTH) |
326 A6XX_RB_RENDER_CNTL_FLAG_MRTS(mrts_ubwc_enable));
327 }
328
329 #define VSC_DATA_SIZE(pitch) ((pitch) * 32 + 0x100) /* extra size to store VSC_SIZE */
330 #define VSC_DATA2_SIZE(pitch) ((pitch) * 32)
331
332 static void
333 update_vsc_pipe(struct fd_batch *batch)
334 {
335 struct fd_context *ctx = batch->ctx;
336 struct fd6_context *fd6_ctx = fd6_context(ctx);
337 struct fd_gmem_stateobj *gmem = &ctx->gmem;
338 struct fd_ringbuffer *ring = batch->gmem;
339 int i;
340
341
342 if (!fd6_ctx->vsc_data) {
343 fd6_ctx->vsc_data = fd_bo_new(ctx->screen->dev,
344 VSC_DATA_SIZE(fd6_ctx->vsc_data_pitch),
345 DRM_FREEDRENO_GEM_TYPE_KMEM, "vsc_data");
346 }
347
348 if (!fd6_ctx->vsc_data2) {
349 fd6_ctx->vsc_data2 = fd_bo_new(ctx->screen->dev,
350 VSC_DATA2_SIZE(fd6_ctx->vsc_data2_pitch),
351 DRM_FREEDRENO_GEM_TYPE_KMEM, "vsc_data2");
352 }
353
354 OUT_REG(ring,
355 A6XX_VSC_BIN_SIZE(.width = gmem->bin_w, .height = gmem->bin_h),
356 A6XX_VSC_SIZE_ADDRESS(.bo = fd6_ctx->vsc_data, .bo_offset = 32 * fd6_ctx->vsc_data_pitch));
357
358 OUT_REG(ring, A6XX_VSC_BIN_COUNT(.nx = gmem->nbins_x,
359 .ny = gmem->nbins_y));
360
361 OUT_PKT4(ring, REG_A6XX_VSC_PIPE_CONFIG_REG(0), 32);
362 for (i = 0; i < 32; i++) {
363 struct fd_vsc_pipe *pipe = &ctx->vsc_pipe[i];
364 OUT_RING(ring, A6XX_VSC_PIPE_CONFIG_REG_X(pipe->x) |
365 A6XX_VSC_PIPE_CONFIG_REG_Y(pipe->y) |
366 A6XX_VSC_PIPE_CONFIG_REG_W(pipe->w) |
367 A6XX_VSC_PIPE_CONFIG_REG_H(pipe->h));
368 }
369
370 OUT_REG(ring,
371 A6XX_VSC_PIPE_DATA2_ADDRESS(.bo = fd6_ctx->vsc_data2),
372 A6XX_VSC_PIPE_DATA2_PITCH(.dword = fd6_ctx->vsc_data2_pitch),
373 A6XX_VSC_PIPE_DATA2_ARRAY_PITCH(.dword = fd_bo_size(fd6_ctx->vsc_data2)));
374
375 OUT_REG(ring,
376 A6XX_VSC_PIPE_DATA_ADDRESS(.bo = fd6_ctx->vsc_data),
377 A6XX_VSC_PIPE_DATA_PITCH(.dword = fd6_ctx->vsc_data_pitch),
378 A6XX_VSC_PIPE_DATA_ARRAY_PITCH(.dword = fd_bo_size(fd6_ctx->vsc_data)));
379 }
380
381 /* TODO we probably have more than 8 scratch regs.. although the first
382 * 8 is what kernel dumps, and it is kinda useful to be able to see
383 * the value in kernel traces
384 */
385 #define OVERFLOW_FLAG_REG REG_A6XX_CP_SCRATCH_REG(0)
386
387 /*
388 * If overflow is detected, either 0x1 (VSC_DATA overflow) or 0x3
389 * (VSC_DATA2 overflow) plus the size of the overflowed buffer is
390 * written to control->vsc_overflow. This allows the CPU to
391 * detect which buffer overflowed (and, since the current size is
392 * encoded as well, this protects against already-submitted but
393 * not executed batches from fooling the CPU into increasing the
394 * size again unnecessarily).
395 *
396 * To conditionally use VSC data in draw pass only if there is no
397 * overflow, we use a scratch reg (OVERFLOW_FLAG_REG) to hold 1
398 * if no overflow, or 0 in case of overflow. The value is inverted
399 * to make the CP_COND_REG_EXEC stuff easier.
400 */
401 static void
402 emit_vsc_overflow_test(struct fd_batch *batch)
403 {
404 struct fd_ringbuffer *ring = batch->gmem;
405 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
406 struct fd6_context *fd6_ctx = fd6_context(batch->ctx);
407
408 debug_assert((fd6_ctx->vsc_data_pitch & 0x3) == 0);
409 debug_assert((fd6_ctx->vsc_data2_pitch & 0x3) == 0);
410
411 /* Clear vsc_scratch: */
412 OUT_PKT7(ring, CP_MEM_WRITE, 3);
413 OUT_RELOCW(ring, control_ptr(fd6_ctx, vsc_scratch));
414 OUT_RING(ring, 0x0);
415
416 /* Check for overflow, write vsc_scratch if detected: */
417 for (int i = 0; i < gmem->num_vsc_pipes; i++) {
418 OUT_PKT7(ring, CP_COND_WRITE5, 8);
419 OUT_RING(ring, CP_COND_WRITE5_0_FUNCTION(WRITE_GE) |
420 CP_COND_WRITE5_0_WRITE_MEMORY);
421 OUT_RING(ring, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_SIZE_REG(i)));
422 OUT_RING(ring, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
423 OUT_RING(ring, CP_COND_WRITE5_3_REF(fd6_ctx->vsc_data_pitch));
424 OUT_RING(ring, CP_COND_WRITE5_4_MASK(~0));
425 OUT_RELOCW(ring, control_ptr(fd6_ctx, vsc_scratch)); /* WRITE_ADDR_LO/HI */
426 OUT_RING(ring, CP_COND_WRITE5_7_WRITE_DATA(1 + fd6_ctx->vsc_data_pitch));
427
428 OUT_PKT7(ring, CP_COND_WRITE5, 8);
429 OUT_RING(ring, CP_COND_WRITE5_0_FUNCTION(WRITE_GE) |
430 CP_COND_WRITE5_0_WRITE_MEMORY);
431 OUT_RING(ring, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_SIZE2_REG(i)));
432 OUT_RING(ring, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
433 OUT_RING(ring, CP_COND_WRITE5_3_REF(fd6_ctx->vsc_data2_pitch));
434 OUT_RING(ring, CP_COND_WRITE5_4_MASK(~0));
435 OUT_RELOCW(ring, control_ptr(fd6_ctx, vsc_scratch)); /* WRITE_ADDR_LO/HI */
436 OUT_RING(ring, CP_COND_WRITE5_7_WRITE_DATA(3 + fd6_ctx->vsc_data2_pitch));
437 }
438
439 OUT_PKT7(ring, CP_WAIT_MEM_WRITES, 0);
440
441 OUT_PKT7(ring, CP_WAIT_FOR_ME, 0);
442
443 OUT_PKT7(ring, CP_MEM_TO_REG, 3);
444 OUT_RING(ring, CP_MEM_TO_REG_0_REG(OVERFLOW_FLAG_REG) |
445 CP_MEM_TO_REG_0_CNT(0));
446 OUT_RELOC(ring, control_ptr(fd6_ctx, vsc_scratch)); /* SRC_LO/HI */
447
448 /*
449 * This is a bit awkward, we really want a way to invert the
450 * CP_REG_TEST/CP_COND_REG_EXEC logic, so that we can conditionally
451 * execute cmds to use hwbinning when a bit is *not* set. This
452 * dance is to invert OVERFLOW_FLAG_REG
453 *
454 * A CP_NOP packet is used to skip executing the 'else' clause
455 * if (b0 set)..
456 */
457
458 BEGIN_RING(ring, 10); /* ensure if/else doesn't get split */
459
460 /* b0 will be set if VSC_DATA or VSC_DATA2 overflow: */
461 OUT_PKT7(ring, CP_REG_TEST, 1);
462 OUT_RING(ring, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG) |
463 A6XX_CP_REG_TEST_0_BIT(0) |
464 A6XX_CP_REG_TEST_0_WAIT_FOR_ME);
465
466 OUT_PKT7(ring, CP_COND_REG_EXEC, 2);
467 OUT_RING(ring, 0x10000000);
468 OUT_RING(ring, 7); /* conditionally execute next 7 dwords */
469
470 /* if (b0 set) */ {
471 /*
472 * On overflow, mirror the value to control->vsc_overflow
473 * which CPU is checking to detect overflow (see
474 * check_vsc_overflow())
475 */
476 OUT_PKT7(ring, CP_REG_TO_MEM, 3);
477 OUT_RING(ring, CP_REG_TO_MEM_0_REG(OVERFLOW_FLAG_REG) |
478 CP_REG_TO_MEM_0_CNT(1 - 1));
479 OUT_RELOCW(ring, control_ptr(fd6_ctx, vsc_overflow));
480
481 OUT_PKT4(ring, OVERFLOW_FLAG_REG, 1);
482 OUT_RING(ring, 0x0);
483
484 OUT_PKT7(ring, CP_NOP, 2); /* skip 'else' when 'if' is taken */
485 } /* else */ {
486 OUT_PKT4(ring, OVERFLOW_FLAG_REG, 1);
487 OUT_RING(ring, 0x1);
488 }
489 }
490
491 static void
492 check_vsc_overflow(struct fd_context *ctx)
493 {
494 struct fd6_context *fd6_ctx = fd6_context(ctx);
495 struct fd6_control *control = fd_bo_map(fd6_ctx->control_mem);
496 uint32_t vsc_overflow = control->vsc_overflow;
497
498 if (!vsc_overflow)
499 return;
500
501 /* clear overflow flag: */
502 control->vsc_overflow = 0;
503
504 unsigned buffer = vsc_overflow & 0x3;
505 unsigned size = vsc_overflow & ~0x3;
506
507 if (buffer == 0x1) {
508 /* VSC_PIPE_DATA overflow: */
509
510 if (size < fd6_ctx->vsc_data_pitch) {
511 /* we've already increased the size, this overflow is
512 * from a batch submitted before resize, but executed
513 * after
514 */
515 return;
516 }
517
518 fd_bo_del(fd6_ctx->vsc_data);
519 fd6_ctx->vsc_data = NULL;
520 fd6_ctx->vsc_data_pitch *= 2;
521
522 debug_printf("resized VSC_DATA_PITCH to: 0x%x\n", fd6_ctx->vsc_data_pitch);
523
524 } else if (buffer == 0x3) {
525 /* VSC_PIPE_DATA2 overflow: */
526
527 if (size < fd6_ctx->vsc_data2_pitch) {
528 /* we've already increased the size */
529 return;
530 }
531
532 fd_bo_del(fd6_ctx->vsc_data2);
533 fd6_ctx->vsc_data2 = NULL;
534 fd6_ctx->vsc_data2_pitch *= 2;
535
536 debug_printf("resized VSC_DATA2_PITCH to: 0x%x\n", fd6_ctx->vsc_data2_pitch);
537
538 } else {
539 /* NOTE: it's possible, for example, for overflow to corrupt the
540 * control page. I mostly just see this hit if I set initial VSC
541 * buffer size extremely small. Things still seem to recover,
542 * but maybe we should pre-emptively realloc vsc_data/vsc_data2
543 * and hope for different memory placement?
544 */
545 DBG("invalid vsc_overflow value: 0x%08x", vsc_overflow);
546 }
547 }
548
549 /*
550 * Emit conditional CP_INDIRECT_BRANCH based on VSC_STATE[p], ie. the IB
551 * is skipped for tiles that have no visible geometry.
552 */
553 static void
554 emit_conditional_ib(struct fd_batch *batch, struct fd_tile *tile,
555 struct fd_ringbuffer *target)
556 {
557 struct fd_ringbuffer *ring = batch->gmem;
558
559 if (target->cur == target->start)
560 return;
561
562 emit_marker6(ring, 6);
563
564 unsigned count = fd_ringbuffer_cmd_count(target);
565
566 BEGIN_RING(ring, 5 + 4 * count); /* ensure conditional doesn't get split */
567
568 OUT_PKT7(ring, CP_REG_TEST, 1);
569 OUT_RING(ring, A6XX_CP_REG_TEST_0_REG(REG_A6XX_VSC_STATE_REG(tile->p)) |
570 A6XX_CP_REG_TEST_0_BIT(tile->n) |
571 A6XX_CP_REG_TEST_0_WAIT_FOR_ME);
572
573 OUT_PKT7(ring, CP_COND_REG_EXEC, 2);
574 OUT_RING(ring, 0x10000000);
575 OUT_RING(ring, 4 * count); /* conditionally execute next 4*count dwords */
576
577 for (unsigned i = 0; i < count; i++) {
578 uint32_t dwords;
579 OUT_PKT7(ring, CP_INDIRECT_BUFFER, 3);
580 dwords = fd_ringbuffer_emit_reloc_ring_full(ring, target, i) / 4;
581 assert(dwords > 0);
582 OUT_RING(ring, dwords);
583 }
584
585 emit_marker6(ring, 6);
586 }
587
588 static void
589 set_scissor(struct fd_ringbuffer *ring, uint32_t x1, uint32_t y1, uint32_t x2, uint32_t y2)
590 {
591 OUT_REG(ring,
592 A6XX_GRAS_SC_WINDOW_SCISSOR_TL(.x = x1, .y = y1),
593 A6XX_GRAS_SC_WINDOW_SCISSOR_BR(.x = x2, .y = y2));
594
595 OUT_REG(ring,
596 A6XX_GRAS_RESOLVE_CNTL_1(.x = x1, .y = y1),
597 A6XX_GRAS_RESOLVE_CNTL_2(.x = x2, .y = y2));
598 }
599
600 static void
601 set_bin_size(struct fd_ringbuffer *ring, uint32_t w, uint32_t h, uint32_t flag)
602 {
603 OUT_REG(ring, A6XX_GRAS_BIN_CONTROL(.binw = w, .binh = h, .dword = flag));
604 OUT_REG(ring, A6XX_RB_BIN_CONTROL(.binw = w, .binh = h, .dword = flag));
605 /* no flag for RB_BIN_CONTROL2... */
606 OUT_REG(ring, A6XX_RB_BIN_CONTROL2(.binw = w, .binh = h));
607 }
608
609 static void
610 emit_binning_pass(struct fd_batch *batch)
611 {
612 struct fd_ringbuffer *ring = batch->gmem;
613 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
614 struct fd6_context *fd6_ctx = fd6_context(batch->ctx);
615
616 uint32_t x1 = gmem->minx;
617 uint32_t y1 = gmem->miny;
618 uint32_t x2 = gmem->minx + gmem->width - 1;
619 uint32_t y2 = gmem->miny + gmem->height - 1;
620
621 debug_assert(!batch->tessellation);
622
623 set_scissor(ring, x1, y1, x2, y2);
624
625 emit_marker6(ring, 7);
626 OUT_PKT7(ring, CP_SET_MARKER, 1);
627 OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_BINNING));
628 emit_marker6(ring, 7);
629
630 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
631 OUT_RING(ring, 0x1);
632
633 OUT_PKT7(ring, CP_SET_MODE, 1);
634 OUT_RING(ring, 0x1);
635
636 OUT_WFI5(ring);
637
638 OUT_REG(ring, A6XX_VFD_MODE_CNTL(.binning_pass = true));
639
640 update_vsc_pipe(batch);
641
642 OUT_PKT4(ring, REG_A6XX_PC_UNKNOWN_9805, 1);
643 OUT_RING(ring, fd6_ctx->magic.PC_UNKNOWN_9805);
644
645 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A0F8, 1);
646 OUT_RING(ring, fd6_ctx->magic.SP_UNKNOWN_A0F8);
647
648 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
649 OUT_RING(ring, UNK_2C);
650
651 OUT_PKT4(ring, REG_A6XX_RB_WINDOW_OFFSET, 1);
652 OUT_RING(ring, A6XX_RB_WINDOW_OFFSET_X(0) |
653 A6XX_RB_WINDOW_OFFSET_Y(0));
654
655 OUT_PKT4(ring, REG_A6XX_SP_TP_WINDOW_OFFSET, 1);
656 OUT_RING(ring, A6XX_SP_TP_WINDOW_OFFSET_X(0) |
657 A6XX_SP_TP_WINDOW_OFFSET_Y(0));
658
659 /* emit IB to binning drawcmds: */
660 fd6_emit_ib(ring, batch->draw);
661
662 fd_reset_wfi(batch);
663
664 OUT_PKT7(ring, CP_SET_DRAW_STATE, 3);
665 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
666 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
667 CP_SET_DRAW_STATE__0_GROUP_ID(0));
668 OUT_RING(ring, CP_SET_DRAW_STATE__1_ADDR_LO(0));
669 OUT_RING(ring, CP_SET_DRAW_STATE__2_ADDR_HI(0));
670
671 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
672 OUT_RING(ring, UNK_2D);
673
674 fd6_cache_inv(batch, ring);
675 fd6_cache_flush(batch, ring);
676 fd_wfi(batch, ring);
677
678 OUT_PKT7(ring, CP_WAIT_FOR_ME, 0);
679
680 emit_vsc_overflow_test(batch);
681
682 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
683 OUT_RING(ring, 0x0);
684
685 OUT_PKT7(ring, CP_SET_MODE, 1);
686 OUT_RING(ring, 0x0);
687
688 OUT_WFI5(ring);
689
690 OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
691 OUT_RING(ring, fd6_ctx->magic.RB_CCU_CNTL_gmem);
692 }
693
694 static void
695 emit_msaa(struct fd_ringbuffer *ring, unsigned nr)
696 {
697 enum a3xx_msaa_samples samples = fd_msaa_samples(nr);
698
699 OUT_PKT4(ring, REG_A6XX_SP_TP_RAS_MSAA_CNTL, 2);
700 OUT_RING(ring, A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(samples));
701 OUT_RING(ring, A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(samples) |
702 COND(samples == MSAA_ONE, A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE));
703
704 OUT_PKT4(ring, REG_A6XX_GRAS_RAS_MSAA_CNTL, 2);
705 OUT_RING(ring, A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(samples));
706 OUT_RING(ring, A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(samples) |
707 COND(samples == MSAA_ONE, A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE));
708
709 OUT_PKT4(ring, REG_A6XX_RB_RAS_MSAA_CNTL, 2);
710 OUT_RING(ring, A6XX_RB_RAS_MSAA_CNTL_SAMPLES(samples));
711 OUT_RING(ring, A6XX_RB_DEST_MSAA_CNTL_SAMPLES(samples) |
712 COND(samples == MSAA_ONE, A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE));
713
714 OUT_PKT4(ring, REG_A6XX_RB_MSAA_CNTL, 1);
715 OUT_RING(ring, A6XX_RB_MSAA_CNTL_SAMPLES(samples));
716 }
717
718 static void prepare_tile_setup_ib(struct fd_batch *batch);
719 static void prepare_tile_fini_ib(struct fd_batch *batch);
720
721 /* before first tile */
722 static void
723 fd6_emit_tile_init(struct fd_batch *batch)
724 {
725 struct fd_context *ctx = batch->ctx;
726 struct fd_ringbuffer *ring = batch->gmem;
727 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
728 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
729
730 fd6_emit_restore(batch, ring);
731
732 fd6_emit_lrz_flush(ring);
733
734 if (batch->lrz_clear)
735 fd6_emit_ib(ring, batch->lrz_clear);
736
737 fd6_cache_inv(batch, ring);
738
739 prepare_tile_setup_ib(batch);
740 prepare_tile_fini_ib(batch);
741
742 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
743 OUT_RING(ring, 0x0);
744
745 fd_wfi(batch, ring);
746 OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
747 OUT_RING(ring, fd6_context(ctx)->magic.RB_CCU_CNTL_gmem);
748
749 emit_zs(ring, pfb->zsbuf, &ctx->gmem);
750 emit_mrt(ring, pfb, &ctx->gmem);
751 emit_msaa(ring, pfb->samples);
752 patch_fb_read(batch);
753
754 if (use_hw_binning(batch)) {
755 /* enable stream-out during binning pass: */
756 OUT_PKT4(ring, REG_A6XX_VPC_SO_OVERRIDE, 1);
757 OUT_RING(ring, 0);
758
759 set_bin_size(ring, gmem->bin_w, gmem->bin_h,
760 A6XX_RB_BIN_CONTROL_BINNING_PASS | 0x6000000);
761 update_render_cntl(batch, pfb, true);
762 emit_binning_pass(batch);
763
764 /* and disable stream-out for draw pass: */
765 OUT_PKT4(ring, REG_A6XX_VPC_SO_OVERRIDE, 1);
766 OUT_RING(ring, A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
767
768 /*
769 * NOTE: even if we detect VSC overflow and disable use of
770 * visibility stream in draw pass, it is still safe to execute
771 * the reset of these cmds:
772 */
773
774 // NOTE a618 not setting .USE_VIZ .. from a quick check on a630, it
775 // does not appear that this bit changes much (ie. it isn't actually
776 // .USE_VIZ like previous gens)
777 set_bin_size(ring, gmem->bin_w, gmem->bin_h,
778 A6XX_RB_BIN_CONTROL_USE_VIZ | 0x6000000);
779
780 OUT_PKT4(ring, REG_A6XX_VFD_MODE_CNTL, 1);
781 OUT_RING(ring, 0x0);
782
783 OUT_PKT4(ring, REG_A6XX_PC_UNKNOWN_9805, 1);
784 OUT_RING(ring, fd6_context(ctx)->magic.PC_UNKNOWN_9805);
785
786 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A0F8, 1);
787 OUT_RING(ring, fd6_context(ctx)->magic.SP_UNKNOWN_A0F8);
788
789 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
790 OUT_RING(ring, 0x1);
791 } else {
792 /* no binning pass, so enable stream-out for draw pass:: */
793 OUT_PKT4(ring, REG_A6XX_VPC_SO_OVERRIDE, 1);
794 OUT_RING(ring, 0);
795
796 set_bin_size(ring, gmem->bin_w, gmem->bin_h, 0x6000000);
797 }
798
799 update_render_cntl(batch, pfb, false);
800 }
801
802 static void
803 set_window_offset(struct fd_ringbuffer *ring, uint32_t x1, uint32_t y1)
804 {
805 OUT_PKT4(ring, REG_A6XX_RB_WINDOW_OFFSET, 1);
806 OUT_RING(ring, A6XX_RB_WINDOW_OFFSET_X(x1) |
807 A6XX_RB_WINDOW_OFFSET_Y(y1));
808
809 OUT_PKT4(ring, REG_A6XX_RB_WINDOW_OFFSET2, 1);
810 OUT_RING(ring, A6XX_RB_WINDOW_OFFSET2_X(x1) |
811 A6XX_RB_WINDOW_OFFSET2_Y(y1));
812
813 OUT_PKT4(ring, REG_A6XX_SP_WINDOW_OFFSET, 1);
814 OUT_RING(ring, A6XX_SP_WINDOW_OFFSET_X(x1) |
815 A6XX_SP_WINDOW_OFFSET_Y(y1));
816
817 OUT_PKT4(ring, REG_A6XX_SP_TP_WINDOW_OFFSET, 1);
818 OUT_RING(ring, A6XX_SP_TP_WINDOW_OFFSET_X(x1) |
819 A6XX_SP_TP_WINDOW_OFFSET_Y(y1));
820 }
821
822 /* before mem2gmem */
823 static void
824 fd6_emit_tile_prep(struct fd_batch *batch, struct fd_tile *tile)
825 {
826 struct fd_context *ctx = batch->ctx;
827 struct fd6_context *fd6_ctx = fd6_context(ctx);
828 struct fd_ringbuffer *ring = batch->gmem;
829
830 emit_marker6(ring, 7);
831 OUT_PKT7(ring, CP_SET_MARKER, 1);
832 OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM) | 0x10);
833 emit_marker6(ring, 7);
834
835 uint32_t x1 = tile->xoff;
836 uint32_t y1 = tile->yoff;
837 uint32_t x2 = tile->xoff + tile->bin_w - 1;
838 uint32_t y2 = tile->yoff + tile->bin_h - 1;
839
840 set_scissor(ring, x1, y1, x2, y2);
841
842 if (use_hw_binning(batch)) {
843 struct fd_vsc_pipe *pipe = &ctx->vsc_pipe[tile->p];
844
845 OUT_PKT7(ring, CP_WAIT_FOR_ME, 0);
846
847 OUT_PKT7(ring, CP_SET_MODE, 1);
848 OUT_RING(ring, 0x0);
849
850 /*
851 * Conditionally execute if no VSC overflow:
852 */
853
854 BEGIN_RING(ring, 18); /* ensure if/else doesn't get split */
855
856 OUT_PKT7(ring, CP_REG_TEST, 1);
857 OUT_RING(ring, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG) |
858 A6XX_CP_REG_TEST_0_BIT(0) |
859 A6XX_CP_REG_TEST_0_WAIT_FOR_ME);
860
861 OUT_PKT7(ring, CP_COND_REG_EXEC, 2);
862 OUT_RING(ring, 0x10000000);
863 OUT_RING(ring, 11); /* conditionally execute next 11 dwords */
864
865 /* if (no overflow) */ {
866 OUT_PKT7(ring, CP_SET_BIN_DATA5, 7);
867 OUT_RING(ring, CP_SET_BIN_DATA5_0_VSC_SIZE(pipe->w * pipe->h) |
868 CP_SET_BIN_DATA5_0_VSC_N(tile->n));
869 OUT_RELOC(ring, fd6_ctx->vsc_data, /* VSC_PIPE[p].DATA_ADDRESS */
870 (tile->p * fd6_ctx->vsc_data_pitch), 0, 0);
871 OUT_RELOC(ring, fd6_ctx->vsc_data, /* VSC_SIZE_ADDRESS + (p * 4) */
872 (tile->p * 4) + (32 * fd6_ctx->vsc_data_pitch), 0, 0);
873 OUT_RELOC(ring, fd6_ctx->vsc_data2,
874 (tile->p * fd6_ctx->vsc_data2_pitch), 0, 0);
875
876 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
877 OUT_RING(ring, 0x0);
878
879 /* use a NOP packet to skip over the 'else' side: */
880 OUT_PKT7(ring, CP_NOP, 2);
881 } /* else */ {
882 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
883 OUT_RING(ring, 0x1);
884 }
885
886 set_window_offset(ring, x1, y1);
887
888 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
889 set_bin_size(ring, gmem->bin_w, gmem->bin_h, 0x6000000);
890
891 OUT_PKT7(ring, CP_SET_MODE, 1);
892 OUT_RING(ring, 0x0);
893
894 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8804, 1);
895 OUT_RING(ring, 0x0);
896
897 OUT_PKT4(ring, REG_A6XX_SP_TP_UNKNOWN_B304, 1);
898 OUT_RING(ring, 0x0);
899
900 OUT_PKT4(ring, REG_A6XX_GRAS_UNKNOWN_80A4, 1);
901 OUT_RING(ring, 0x0);
902 } else {
903 set_window_offset(ring, x1, y1);
904
905 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
906 OUT_RING(ring, 0x1);
907
908 OUT_PKT7(ring, CP_SET_MODE, 1);
909 OUT_RING(ring, 0x0);
910 }
911 }
912
913 static void
914 set_blit_scissor(struct fd_batch *batch, struct fd_ringbuffer *ring)
915 {
916 struct pipe_scissor_state blit_scissor;
917 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
918
919 blit_scissor.minx = 0;
920 blit_scissor.miny = 0;
921 blit_scissor.maxx = align(pfb->width, batch->ctx->screen->gmem_alignw);
922 blit_scissor.maxy = align(pfb->height, batch->ctx->screen->gmem_alignh);
923
924 OUT_PKT4(ring, REG_A6XX_RB_BLIT_SCISSOR_TL, 2);
925 OUT_RING(ring,
926 A6XX_RB_BLIT_SCISSOR_TL_X(blit_scissor.minx) |
927 A6XX_RB_BLIT_SCISSOR_TL_Y(blit_scissor.miny));
928 OUT_RING(ring,
929 A6XX_RB_BLIT_SCISSOR_BR_X(blit_scissor.maxx - 1) |
930 A6XX_RB_BLIT_SCISSOR_BR_Y(blit_scissor.maxy - 1));
931 }
932
933 static void
934 emit_blit(struct fd_batch *batch,
935 struct fd_ringbuffer *ring,
936 uint32_t base,
937 struct pipe_surface *psurf,
938 bool stencil)
939 {
940 struct fdl_slice *slice;
941 struct fd_resource *rsc = fd_resource(psurf->texture);
942 enum pipe_format pfmt = psurf->format;
943 uint32_t offset;
944 bool ubwc_enabled;
945
946 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
947
948 /* separate stencil case: */
949 if (stencil) {
950 rsc = rsc->stencil;
951 pfmt = rsc->base.format;
952 }
953
954 slice = fd_resource_slice(rsc, psurf->u.tex.level);
955 offset = fd_resource_offset(rsc, psurf->u.tex.level,
956 psurf->u.tex.first_layer);
957 ubwc_enabled = fd_resource_ubwc_enabled(rsc, psurf->u.tex.level);
958
959 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
960
961 enum a6xx_color_fmt format = fd6_pipe2color(pfmt);
962 uint32_t stride = slice->pitch * rsc->layout.cpp;
963 uint32_t size = slice->size0;
964 enum a3xx_color_swap swap = rsc->layout.tile_mode ? WZYX : fd6_pipe2swap(pfmt);
965 enum a3xx_msaa_samples samples =
966 fd_msaa_samples(rsc->base.nr_samples);
967 uint32_t tile_mode = fd_resource_tile_mode(&rsc->base, psurf->u.tex.level);
968
969 OUT_REG(ring,
970 A6XX_RB_BLIT_DST_INFO(.tile_mode = tile_mode, .samples = samples,
971 .color_format = format, .color_swap = swap, .flags = ubwc_enabled),
972 A6XX_RB_BLIT_DST(.bo = rsc->bo, .bo_offset = offset),
973 A6XX_RB_BLIT_DST_PITCH(.a6xx_rb_blit_dst_pitch = stride),
974 A6XX_RB_BLIT_DST_ARRAY_PITCH(.a6xx_rb_blit_dst_array_pitch = size));
975
976 OUT_REG(ring, A6XX_RB_BLIT_BASE_GMEM(.dword = base));
977
978 if (ubwc_enabled) {
979 OUT_PKT4(ring, REG_A6XX_RB_BLIT_FLAG_DST_LO, 3);
980 fd6_emit_flag_reference(ring, rsc,
981 psurf->u.tex.level, psurf->u.tex.first_layer);
982 }
983
984 fd6_emit_blit(batch, ring);
985 }
986
987 static void
988 emit_restore_blit(struct fd_batch *batch,
989 struct fd_ringbuffer *ring,
990 uint32_t base,
991 struct pipe_surface *psurf,
992 unsigned buffer)
993 {
994 bool stencil = (buffer == FD_BUFFER_STENCIL);
995
996 OUT_REG(ring, A6XX_RB_BLIT_INFO(
997 .gmem = true, .unk0 = true,
998 .depth = (buffer == FD_BUFFER_DEPTH),
999 .integer = util_format_is_pure_integer(psurf->format)));
1000
1001 emit_blit(batch, ring, base, psurf, stencil);
1002 }
1003
1004 static void
1005 emit_clears(struct fd_batch *batch, struct fd_ringbuffer *ring)
1006 {
1007 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
1008 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
1009 enum a3xx_msaa_samples samples = fd_msaa_samples(pfb->samples);
1010
1011 uint32_t buffers = batch->fast_cleared;
1012
1013 if (buffers & PIPE_CLEAR_COLOR) {
1014
1015 for (int i = 0; i < pfb->nr_cbufs; i++) {
1016 union pipe_color_union *color = &batch->clear_color[i];
1017 union util_color uc = {0};
1018
1019 if (!pfb->cbufs[i])
1020 continue;
1021
1022 if (!(buffers & (PIPE_CLEAR_COLOR0 << i)))
1023 continue;
1024
1025 enum pipe_format pfmt = pfb->cbufs[i]->format;
1026
1027 // XXX I think RB_CLEAR_COLOR_DWn wants to take into account SWAP??
1028 union pipe_color_union swapped;
1029 switch (fd6_pipe2swap(pfmt)) {
1030 case WZYX:
1031 swapped.ui[0] = color->ui[0];
1032 swapped.ui[1] = color->ui[1];
1033 swapped.ui[2] = color->ui[2];
1034 swapped.ui[3] = color->ui[3];
1035 break;
1036 case WXYZ:
1037 swapped.ui[2] = color->ui[0];
1038 swapped.ui[1] = color->ui[1];
1039 swapped.ui[0] = color->ui[2];
1040 swapped.ui[3] = color->ui[3];
1041 break;
1042 case ZYXW:
1043 swapped.ui[3] = color->ui[0];
1044 swapped.ui[0] = color->ui[1];
1045 swapped.ui[1] = color->ui[2];
1046 swapped.ui[2] = color->ui[3];
1047 break;
1048 case XYZW:
1049 swapped.ui[3] = color->ui[0];
1050 swapped.ui[2] = color->ui[1];
1051 swapped.ui[1] = color->ui[2];
1052 swapped.ui[0] = color->ui[3];
1053 break;
1054 }
1055
1056 if (util_format_is_pure_uint(pfmt)) {
1057 util_format_write_4ui(pfmt, swapped.ui, 0, &uc, 0, 0, 0, 1, 1);
1058 } else if (util_format_is_pure_sint(pfmt)) {
1059 util_format_write_4i(pfmt, swapped.i, 0, &uc, 0, 0, 0, 1, 1);
1060 } else {
1061 util_pack_color(swapped.f, pfmt, &uc);
1062 }
1063
1064 OUT_PKT4(ring, REG_A6XX_RB_BLIT_DST_INFO, 1);
1065 OUT_RING(ring, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR) |
1066 A6XX_RB_BLIT_DST_INFO_SAMPLES(samples) |
1067 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(fd6_pipe2color(pfmt)));
1068
1069 OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
1070 OUT_RING(ring, A6XX_RB_BLIT_INFO_GMEM |
1071 A6XX_RB_BLIT_INFO_CLEAR_MASK(0xf));
1072
1073 OUT_PKT4(ring, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
1074 OUT_RING(ring, gmem->cbuf_base[i]);
1075
1076 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_88D0, 1);
1077 OUT_RING(ring, 0);
1078
1079 OUT_PKT4(ring, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 4);
1080 OUT_RING(ring, uc.ui[0]);
1081 OUT_RING(ring, uc.ui[1]);
1082 OUT_RING(ring, uc.ui[2]);
1083 OUT_RING(ring, uc.ui[3]);
1084
1085 fd6_emit_blit(batch, ring);
1086 }
1087 }
1088
1089 const bool has_depth = pfb->zsbuf;
1090 const bool has_separate_stencil =
1091 has_depth && fd_resource(pfb->zsbuf->texture)->stencil;
1092
1093 /* First clear depth or combined depth/stencil. */
1094 if ((has_depth && (buffers & PIPE_CLEAR_DEPTH)) ||
1095 (!has_separate_stencil && (buffers & PIPE_CLEAR_STENCIL))) {
1096 enum pipe_format pfmt = pfb->zsbuf->format;
1097 uint32_t clear_value;
1098 uint32_t mask = 0;
1099
1100 if (has_separate_stencil) {
1101 pfmt = util_format_get_depth_only(pfb->zsbuf->format);
1102 clear_value = util_pack_z(pfmt, batch->clear_depth);
1103 } else {
1104 pfmt = pfb->zsbuf->format;
1105 clear_value = util_pack_z_stencil(pfmt, batch->clear_depth,
1106 batch->clear_stencil);
1107 }
1108
1109 if (buffers & PIPE_CLEAR_DEPTH)
1110 mask |= 0x1;
1111
1112 if (!has_separate_stencil && (buffers & PIPE_CLEAR_STENCIL))
1113 mask |= 0x2;
1114
1115 OUT_PKT4(ring, REG_A6XX_RB_BLIT_DST_INFO, 1);
1116 OUT_RING(ring, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR) |
1117 A6XX_RB_BLIT_DST_INFO_SAMPLES(samples) |
1118 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(fd6_pipe2color(pfmt)));
1119
1120 OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
1121 OUT_RING(ring, A6XX_RB_BLIT_INFO_GMEM |
1122 // XXX UNK0 for separate stencil ??
1123 A6XX_RB_BLIT_INFO_DEPTH |
1124 A6XX_RB_BLIT_INFO_CLEAR_MASK(mask));
1125
1126 OUT_PKT4(ring, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
1127 OUT_RING(ring, gmem->zsbuf_base[0]);
1128
1129 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_88D0, 1);
1130 OUT_RING(ring, 0);
1131
1132 OUT_PKT4(ring, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 1);
1133 OUT_RING(ring, clear_value);
1134
1135 fd6_emit_blit(batch, ring);
1136 }
1137
1138 /* Then clear the separate stencil buffer in case of 32 bit depth
1139 * formats with separate stencil. */
1140 if (has_separate_stencil && (buffers & PIPE_CLEAR_STENCIL)) {
1141 OUT_PKT4(ring, REG_A6XX_RB_BLIT_DST_INFO, 1);
1142 OUT_RING(ring, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR) |
1143 A6XX_RB_BLIT_DST_INFO_SAMPLES(samples) |
1144 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(RB6_R8_UINT));
1145
1146 OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
1147 OUT_RING(ring, A6XX_RB_BLIT_INFO_GMEM |
1148 //A6XX_RB_BLIT_INFO_UNK0 |
1149 A6XX_RB_BLIT_INFO_DEPTH |
1150 A6XX_RB_BLIT_INFO_CLEAR_MASK(0x1));
1151
1152 OUT_PKT4(ring, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
1153 OUT_RING(ring, gmem->zsbuf_base[1]);
1154
1155 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_88D0, 1);
1156 OUT_RING(ring, 0);
1157
1158 OUT_PKT4(ring, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 1);
1159 OUT_RING(ring, batch->clear_stencil & 0xff);
1160
1161 fd6_emit_blit(batch, ring);
1162 }
1163 }
1164
1165 /*
1166 * transfer from system memory to gmem
1167 */
1168 static void
1169 emit_restore_blits(struct fd_batch *batch, struct fd_ringbuffer *ring)
1170 {
1171 struct fd_context *ctx = batch->ctx;
1172 struct fd_gmem_stateobj *gmem = &ctx->gmem;
1173 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
1174
1175 if (batch->restore & FD_BUFFER_COLOR) {
1176 unsigned i;
1177 for (i = 0; i < pfb->nr_cbufs; i++) {
1178 if (!pfb->cbufs[i])
1179 continue;
1180 if (!(batch->restore & (PIPE_CLEAR_COLOR0 << i)))
1181 continue;
1182 emit_restore_blit(batch, ring, gmem->cbuf_base[i], pfb->cbufs[i],
1183 FD_BUFFER_COLOR);
1184 }
1185 }
1186
1187 if (batch->restore & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
1188 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
1189
1190 if (!rsc->stencil || (batch->restore & FD_BUFFER_DEPTH)) {
1191 emit_restore_blit(batch, ring, gmem->zsbuf_base[0], pfb->zsbuf,
1192 FD_BUFFER_DEPTH);
1193 }
1194 if (rsc->stencil && (batch->restore & FD_BUFFER_STENCIL)) {
1195 emit_restore_blit(batch, ring, gmem->zsbuf_base[1], pfb->zsbuf,
1196 FD_BUFFER_STENCIL);
1197 }
1198 }
1199 }
1200
1201 static void
1202 prepare_tile_setup_ib(struct fd_batch *batch)
1203 {
1204 batch->tile_setup = fd_submit_new_ringbuffer(batch->submit, 0x1000,
1205 FD_RINGBUFFER_STREAMING);
1206
1207 set_blit_scissor(batch, batch->tile_setup);
1208
1209 emit_restore_blits(batch, batch->tile_setup);
1210 emit_clears(batch, batch->tile_setup);
1211 }
1212
1213 /*
1214 * transfer from system memory to gmem
1215 */
1216 static void
1217 fd6_emit_tile_mem2gmem(struct fd_batch *batch, struct fd_tile *tile)
1218 {
1219 }
1220
1221 /* before IB to rendering cmds: */
1222 static void
1223 fd6_emit_tile_renderprep(struct fd_batch *batch, struct fd_tile *tile)
1224 {
1225 if (batch->fast_cleared || !use_hw_binning(batch)) {
1226 fd6_emit_ib(batch->gmem, batch->tile_setup);
1227 } else {
1228 emit_conditional_ib(batch, tile, batch->tile_setup);
1229 }
1230 }
1231
1232 static void
1233 emit_resolve_blit(struct fd_batch *batch,
1234 struct fd_ringbuffer *ring,
1235 uint32_t base,
1236 struct pipe_surface *psurf,
1237 unsigned buffer)
1238 {
1239 uint32_t info = 0;
1240 bool stencil = false;
1241
1242 if (!fd_resource(psurf->texture)->valid)
1243 return;
1244
1245 switch (buffer) {
1246 case FD_BUFFER_COLOR:
1247 break;
1248 case FD_BUFFER_STENCIL:
1249 info |= A6XX_RB_BLIT_INFO_UNK0;
1250 stencil = true;
1251 break;
1252 case FD_BUFFER_DEPTH:
1253 info |= A6XX_RB_BLIT_INFO_DEPTH;
1254 break;
1255 }
1256
1257 if (util_format_is_pure_integer(psurf->format))
1258 info |= A6XX_RB_BLIT_INFO_INTEGER;
1259
1260 OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
1261 OUT_RING(ring, info);
1262
1263 emit_blit(batch, ring, base, psurf, stencil);
1264 }
1265
1266 /*
1267 * transfer from gmem to system memory (ie. normal RAM)
1268 */
1269
1270 static void
1271 prepare_tile_fini_ib(struct fd_batch *batch)
1272 {
1273 struct fd_context *ctx = batch->ctx;
1274 struct fd_gmem_stateobj *gmem = &ctx->gmem;
1275 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
1276 struct fd_ringbuffer *ring;
1277
1278 batch->tile_fini = fd_submit_new_ringbuffer(batch->submit, 0x1000,
1279 FD_RINGBUFFER_STREAMING);
1280 ring = batch->tile_fini;
1281
1282 set_blit_scissor(batch, ring);
1283
1284 if (batch->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
1285 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
1286
1287 if (!rsc->stencil || (batch->resolve & FD_BUFFER_DEPTH)) {
1288 emit_resolve_blit(batch, ring,
1289 gmem->zsbuf_base[0], pfb->zsbuf,
1290 FD_BUFFER_DEPTH);
1291 }
1292 if (rsc->stencil && (batch->resolve & FD_BUFFER_STENCIL)) {
1293 emit_resolve_blit(batch, ring,
1294 gmem->zsbuf_base[1], pfb->zsbuf,
1295 FD_BUFFER_STENCIL);
1296 }
1297 }
1298
1299 if (batch->resolve & FD_BUFFER_COLOR) {
1300 unsigned i;
1301 for (i = 0; i < pfb->nr_cbufs; i++) {
1302 if (!pfb->cbufs[i])
1303 continue;
1304 if (!(batch->resolve & (PIPE_CLEAR_COLOR0 << i)))
1305 continue;
1306 emit_resolve_blit(batch, ring, gmem->cbuf_base[i], pfb->cbufs[i],
1307 FD_BUFFER_COLOR);
1308 }
1309 }
1310 }
1311
1312 static void
1313 fd6_emit_tile(struct fd_batch *batch, struct fd_tile *tile)
1314 {
1315 if (!use_hw_binning(batch)) {
1316 fd6_emit_ib(batch->gmem, batch->draw);
1317 } else {
1318 emit_conditional_ib(batch, tile, batch->draw);
1319 }
1320 }
1321
1322 static void
1323 fd6_emit_tile_gmem2mem(struct fd_batch *batch, struct fd_tile *tile)
1324 {
1325 struct fd_ringbuffer *ring = batch->gmem;
1326
1327 if (use_hw_binning(batch)) {
1328 /* Conditionally execute if no VSC overflow: */
1329
1330 BEGIN_RING(ring, 7); /* ensure if/else doesn't get split */
1331
1332 OUT_PKT7(ring, CP_REG_TEST, 1);
1333 OUT_RING(ring, A6XX_CP_REG_TEST_0_REG(OVERFLOW_FLAG_REG) |
1334 A6XX_CP_REG_TEST_0_BIT(0) |
1335 A6XX_CP_REG_TEST_0_WAIT_FOR_ME);
1336
1337 OUT_PKT7(ring, CP_COND_REG_EXEC, 2);
1338 OUT_RING(ring, 0x10000000);
1339 OUT_RING(ring, 2); /* conditionally execute next 2 dwords */
1340
1341 /* if (no overflow) */ {
1342 OUT_PKT7(ring, CP_SET_MARKER, 1);
1343 OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(0x5) | 0x10);
1344 }
1345 }
1346
1347 OUT_PKT7(ring, CP_SET_DRAW_STATE, 3);
1348 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
1349 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
1350 CP_SET_DRAW_STATE__0_GROUP_ID(0));
1351 OUT_RING(ring, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1352 OUT_RING(ring, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1353
1354 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_LOCAL, 1);
1355 OUT_RING(ring, 0x0);
1356
1357 emit_marker6(ring, 7);
1358 OUT_PKT7(ring, CP_SET_MARKER, 1);
1359 OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE) | 0x10);
1360 emit_marker6(ring, 7);
1361
1362 if (batch->fast_cleared || !use_hw_binning(batch)) {
1363 fd6_emit_ib(batch->gmem, batch->tile_fini);
1364 } else {
1365 emit_conditional_ib(batch, tile, batch->tile_fini);
1366 }
1367
1368 OUT_PKT7(ring, CP_SET_MARKER, 1);
1369 OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(0x7));
1370 }
1371
1372 static void
1373 fd6_emit_tile_fini(struct fd_batch *batch)
1374 {
1375 struct fd_ringbuffer *ring = batch->gmem;
1376
1377 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_CNTL, 1);
1378 OUT_RING(ring, A6XX_GRAS_LRZ_CNTL_ENABLE | A6XX_GRAS_LRZ_CNTL_UNK3);
1379
1380 fd6_emit_lrz_flush(ring);
1381
1382 fd6_event_write(batch, ring, CACHE_FLUSH_TS, true);
1383
1384 if (use_hw_binning(batch)) {
1385 check_vsc_overflow(batch->ctx);
1386 }
1387 }
1388
1389 static void
1390 emit_sysmem_clears(struct fd_batch *batch, struct fd_ringbuffer *ring)
1391 {
1392 struct fd_context *ctx = batch->ctx;
1393 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
1394
1395 uint32_t buffers = batch->fast_cleared;
1396
1397 if (buffers & PIPE_CLEAR_COLOR) {
1398 for (int i = 0; i < pfb->nr_cbufs; i++) {
1399 union pipe_color_union *color = &batch->clear_color[i];
1400
1401 if (!pfb->cbufs[i])
1402 continue;
1403
1404 if (!(buffers & (PIPE_CLEAR_COLOR0 << i)))
1405 continue;
1406
1407 fd6_clear_surface(ctx, ring,
1408 pfb->cbufs[i], pfb->width, pfb->height, color);
1409 }
1410 }
1411 if (buffers & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL)) {
1412 union pipe_color_union value = {};
1413
1414 const bool has_depth = pfb->zsbuf;
1415 struct pipe_resource *separate_stencil =
1416 has_depth && fd_resource(pfb->zsbuf->texture)->stencil ?
1417 &fd_resource(pfb->zsbuf->texture)->stencil->base : NULL;
1418
1419 if ((has_depth && (buffers & PIPE_CLEAR_DEPTH)) ||
1420 (!separate_stencil && (buffers & PIPE_CLEAR_STENCIL))) {
1421 value.f[0] = batch->clear_depth;
1422 value.ui[1] = batch->clear_stencil;
1423 fd6_clear_surface(ctx, ring,
1424 pfb->zsbuf, pfb->width, pfb->height, &value);
1425 }
1426
1427 if (separate_stencil && (buffers & PIPE_CLEAR_STENCIL)) {
1428 value.ui[0] = batch->clear_stencil;
1429
1430 struct pipe_surface stencil_surf = *pfb->zsbuf;
1431 stencil_surf.texture = separate_stencil;
1432
1433 fd6_clear_surface(ctx, ring,
1434 &stencil_surf, pfb->width, pfb->height, &value);
1435 }
1436 }
1437
1438 fd6_event_write(batch, ring, 0x1d, true);
1439 }
1440
1441 static void
1442 setup_tess_buffers(struct fd_batch *batch, struct fd_ringbuffer *ring)
1443 {
1444 struct fd_context *ctx = batch->ctx;
1445
1446 batch->tessfactor_bo = fd_bo_new(ctx->screen->dev,
1447 batch->tessfactor_size,
1448 DRM_FREEDRENO_GEM_TYPE_KMEM, "tessfactor");
1449
1450 batch->tessparam_bo = fd_bo_new(ctx->screen->dev,
1451 batch->tessparam_size,
1452 DRM_FREEDRENO_GEM_TYPE_KMEM, "tessparam");
1453
1454 OUT_PKT4(ring, REG_A6XX_PC_TESSFACTOR_ADDR_LO, 2);
1455 OUT_RELOCW(ring, batch->tessfactor_bo, 0, 0, 0);
1456
1457 batch->tess_addrs_constobj->cur = batch->tess_addrs_constobj->start;
1458 OUT_RELOCW(batch->tess_addrs_constobj, batch->tessparam_bo, 0, 0, 0);
1459 OUT_RELOCW(batch->tess_addrs_constobj, batch->tessfactor_bo, 0, 0, 0);
1460 }
1461
1462 static void
1463 fd6_emit_sysmem_prep(struct fd_batch *batch)
1464 {
1465 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
1466 struct fd_ringbuffer *ring = batch->gmem;
1467
1468 fd6_emit_restore(batch, ring);
1469
1470 if (pfb->width > 0 && pfb->height > 0)
1471 set_scissor(ring, 0, 0, pfb->width - 1, pfb->height - 1);
1472 else
1473 set_scissor(ring, 0, 0, 0, 0);
1474
1475 set_window_offset(ring, 0, 0);
1476
1477 set_bin_size(ring, 0, 0, 0xc00000); /* 0xc00000 = BYPASS? */
1478
1479 emit_sysmem_clears(batch, ring);
1480
1481 fd6_emit_lrz_flush(ring);
1482
1483 emit_marker6(ring, 7);
1484 OUT_PKT7(ring, CP_SET_MARKER, 1);
1485 OUT_RING(ring, A6XX_CP_SET_MARKER_0_MODE(RM6_BYPASS) | 0x10); /* | 0x10 ? */
1486 emit_marker6(ring, 7);
1487
1488 if (batch->tessellation)
1489 setup_tess_buffers(batch, ring);
1490
1491 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1492 OUT_RING(ring, 0x0);
1493
1494 fd6_event_write(batch, ring, PC_CCU_INVALIDATE_COLOR, false);
1495 fd6_cache_inv(batch, ring);
1496
1497 fd_wfi(batch, ring);
1498 OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
1499 OUT_RING(ring, fd6_context(batch->ctx)->magic.RB_CCU_CNTL_bypass);
1500
1501 /* enable stream-out, with sysmem there is only one pass: */
1502 OUT_PKT4(ring, REG_A6XX_VPC_SO_OVERRIDE, 1);
1503 OUT_RING(ring, 0);
1504
1505 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
1506 OUT_RING(ring, 0x1);
1507
1508 emit_zs(ring, pfb->zsbuf, NULL);
1509 emit_mrt(ring, pfb, NULL);
1510 emit_msaa(ring, pfb->samples);
1511
1512 update_render_cntl(batch, pfb, false);
1513 }
1514
1515 static void
1516 fd6_emit_sysmem_fini(struct fd_batch *batch)
1517 {
1518 struct fd_ringbuffer *ring = batch->gmem;
1519
1520 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1521 OUT_RING(ring, 0x0);
1522
1523 fd6_emit_lrz_flush(ring);
1524
1525 fd6_event_write(batch, ring, UNK_1D, true);
1526 }
1527
1528 void
1529 fd6_gmem_init(struct pipe_context *pctx)
1530 {
1531 struct fd_context *ctx = fd_context(pctx);
1532
1533 ctx->emit_tile_init = fd6_emit_tile_init;
1534 ctx->emit_tile_prep = fd6_emit_tile_prep;
1535 ctx->emit_tile_mem2gmem = fd6_emit_tile_mem2gmem;
1536 ctx->emit_tile_renderprep = fd6_emit_tile_renderprep;
1537 ctx->emit_tile = fd6_emit_tile;
1538 ctx->emit_tile_gmem2mem = fd6_emit_tile_gmem2mem;
1539 ctx->emit_tile_fini = fd6_emit_tile_fini;
1540 ctx->emit_sysmem_prep = fd6_emit_sysmem_prep;
1541 ctx->emit_sysmem_fini = fd6_emit_sysmem_fini;
1542 }