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freedreno/a6xx: separate stencil restore/resolve fixes
[mesa.git] / src / gallium / drivers / freedreno / a6xx / fd6_gmem.c
1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 * Authors:
25 * Rob Clark <robclark@freedesktop.org>
26 */
27
28 #include <stdio.h>
29
30 #include "pipe/p_state.h"
31 #include "util/u_string.h"
32 #include "util/u_memory.h"
33 #include "util/u_inlines.h"
34 #include "util/u_format.h"
35
36 #include "freedreno_draw.h"
37 #include "freedreno_state.h"
38 #include "freedreno_resource.h"
39
40 #include "fd6_gmem.h"
41 #include "fd6_context.h"
42 #include "fd6_draw.h"
43 #include "fd6_emit.h"
44 #include "fd6_program.h"
45 #include "fd6_format.h"
46 #include "fd6_zsa.h"
47
48 /* some bits in common w/ a4xx: */
49 #include "a4xx/fd4_draw.h"
50
51 static void
52 emit_mrt(struct fd_ringbuffer *ring, struct pipe_framebuffer_state *pfb,
53 struct fd_gmem_stateobj *gmem)
54 {
55 unsigned char mrt_comp[A6XX_MAX_RENDER_TARGETS] = {0};
56 unsigned srgb_cntl = 0;
57 unsigned i;
58
59 for (i = 0; i < pfb->nr_cbufs; i++) {
60 enum a6xx_color_fmt format = 0;
61 enum a3xx_color_swap swap = WZYX;
62 bool sint = false, uint = false;
63 struct fd_resource *rsc = NULL;
64 struct fd_resource_slice *slice = NULL;
65 uint32_t stride = 0;
66 uint32_t offset = 0;
67
68 if (!pfb->cbufs[i])
69 continue;
70
71 mrt_comp[i] = 0xf;
72
73 struct pipe_surface *psurf = pfb->cbufs[i];
74 enum pipe_format pformat = psurf->format;
75 rsc = fd_resource(psurf->texture);
76 if (!rsc->bo)
77 continue;
78
79 uint32_t base = gmem ? gmem->cbuf_base[i] : 0;
80 slice = fd_resource_slice(rsc, psurf->u.tex.level);
81 format = fd6_pipe2color(pformat);
82 swap = fd6_pipe2swap(pformat);
83 sint = util_format_is_pure_sint(pformat);
84 uint = util_format_is_pure_uint(pformat);
85
86 if (util_format_is_srgb(pformat))
87 srgb_cntl |= (1 << i);
88
89 offset = fd_resource_offset(rsc, psurf->u.tex.level,
90 psurf->u.tex.first_layer);
91
92 stride = slice->pitch * rsc->cpp * pfb->samples;
93
94 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
95 debug_assert((offset + slice->size0) <= fd_bo_size(rsc->bo));
96
97 OUT_PKT4(ring, REG_A6XX_RB_MRT_BUF_INFO(i), 6);
98 OUT_RING(ring, A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format) |
99 A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(rsc->tile_mode) |
100 A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(swap));
101 OUT_RING(ring, A6XX_RB_MRT_PITCH(stride));
102 OUT_RING(ring, A6XX_RB_MRT_ARRAY_PITCH(slice->size0));
103 OUT_RELOCW(ring, rsc->bo, offset, 0, 0); /* BASE_LO/HI */
104 OUT_RING(ring, base); /* RB_MRT[i].BASE_GMEM */
105 OUT_PKT4(ring, REG_A6XX_SP_FS_MRT_REG(i), 1);
106 OUT_RING(ring, A6XX_SP_FS_MRT_REG_COLOR_FORMAT(format) |
107 COND(sint, A6XX_SP_FS_MRT_REG_COLOR_SINT) |
108 COND(uint, A6XX_SP_FS_MRT_REG_COLOR_UINT));
109
110 #if 0
111 /* when we support UBWC, these would be the system memory
112 * addr/pitch/etc:
113 */
114 OUT_PKT4(ring, REG_A6XX_RB_MRT_FLAG_BUFFER(i), 4);
115 OUT_RING(ring, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_LO */
116 OUT_RING(ring, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_HI */
117 OUT_RING(ring, A6XX_RB_MRT_FLAG_BUFFER_PITCH(0));
118 OUT_RING(ring, A6XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(0));
119 #endif
120 }
121
122 OUT_PKT4(ring, REG_A6XX_RB_SRGB_CNTL, 1);
123 OUT_RING(ring, srgb_cntl);
124
125 OUT_PKT4(ring, REG_A6XX_SP_SRGB_CNTL, 1);
126 OUT_RING(ring, srgb_cntl);
127
128 OUT_PKT4(ring, REG_A6XX_RB_RENDER_COMPONENTS, 1);
129 OUT_RING(ring, A6XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
130 A6XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
131 A6XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
132 A6XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
133 A6XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
134 A6XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
135 A6XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
136 A6XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
137
138 OUT_PKT4(ring, REG_A6XX_SP_FS_RENDER_COMPONENTS, 1);
139 OUT_RING(ring,
140 A6XX_SP_FS_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
141 A6XX_SP_FS_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
142 A6XX_SP_FS_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
143 A6XX_SP_FS_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
144 A6XX_SP_FS_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
145 A6XX_SP_FS_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
146 A6XX_SP_FS_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
147 A6XX_SP_FS_RENDER_COMPONENTS_RT7(mrt_comp[7]));
148 }
149
150 static void
151 emit_zs(struct fd_ringbuffer *ring, struct pipe_surface *zsbuf,
152 struct fd_gmem_stateobj *gmem)
153 {
154 if (zsbuf) {
155 struct fd_resource *rsc = fd_resource(zsbuf->texture);
156 enum a6xx_depth_format fmt = fd6_pipe2depth(zsbuf->format);
157 struct fd_resource_slice *slice = fd_resource_slice(rsc, 0);
158 uint32_t stride = slice->pitch * rsc->cpp;
159 uint32_t size = slice->size0;
160 uint32_t base = gmem ? gmem->zsbuf_base[0] : 0;
161
162 OUT_PKT4(ring, REG_A6XX_RB_DEPTH_BUFFER_INFO, 6);
163 OUT_RING(ring, A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(fmt));
164 OUT_RING(ring, A6XX_RB_DEPTH_BUFFER_PITCH(stride));
165 OUT_RING(ring, A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(size));
166 OUT_RELOCW(ring, rsc->bo, 0, 0, 0); /* RB_DEPTH_BUFFER_BASE_LO/HI */
167 OUT_RING(ring, base); /* RB_DEPTH_BUFFER_BASE_GMEM */
168
169 OUT_PKT4(ring, REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO, 1);
170 OUT_RING(ring, A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(fmt));
171
172 OUT_PKT4(ring, REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO, 3);
173 OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
174 OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
175 OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_PITCH */
176
177 if (rsc->lrz) {
178 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO, 5);
179 OUT_RELOCW(ring, rsc->lrz, 0, 0, 0);
180 OUT_RING(ring, A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH(rsc->lrz_pitch));
181 //OUT_RELOCW(ring, rsc->lrz, 0, 0, 0); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO/HI */
182 // XXX a6xx seems to use a different buffer here.. not sure what for..
183 OUT_RING(ring, 0x00000000);
184 OUT_RING(ring, 0x00000000);
185 } else {
186 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO, 5);
187 OUT_RING(ring, 0x00000000);
188 OUT_RING(ring, 0x00000000);
189 OUT_RING(ring, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
190 OUT_RING(ring, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO */
191 OUT_RING(ring, 0x00000000);
192 }
193
194 if (rsc->stencil) {
195 struct fd_resource_slice *slice = fd_resource_slice(rsc->stencil, 0);
196 stride = slice->pitch * rsc->cpp;
197 size = slice->size0;
198 uint32_t base = gmem ? gmem->zsbuf_base[1] : 0;
199
200 OUT_PKT4(ring, REG_A6XX_RB_STENCIL_INFO, 6);
201 OUT_RING(ring, A6XX_RB_STENCIL_INFO_SEPARATE_STENCIL);
202 OUT_RING(ring, A6XX_RB_STENCIL_BUFFER_PITCH(stride));
203 OUT_RING(ring, A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(size));
204 OUT_RELOCW(ring, rsc->stencil->bo, 0, 0, 0); /* RB_STENCIL_BASE_LO/HI */
205 OUT_RING(ring, base); /* RB_STENCIL_BASE_LO */
206 } else {
207 OUT_PKT4(ring, REG_A6XX_RB_STENCIL_INFO, 1);
208 OUT_RING(ring, 0x00000000); /* RB_STENCIL_INFO */
209 }
210 } else {
211 OUT_PKT4(ring, REG_A6XX_RB_DEPTH_BUFFER_INFO, 6);
212 OUT_RING(ring, A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH6_NONE));
213 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_PITCH */
214 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_ARRAY_PITCH */
215 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_BASE_LO */
216 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_BASE_HI */
217 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_BASE_GMEM */
218
219 OUT_PKT4(ring, REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO, 1);
220 OUT_RING(ring, A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH6_NONE));
221
222 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO, 5);
223 OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
224 OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
225 OUT_RING(ring, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
226 OUT_RING(ring, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO */
227 OUT_RING(ring, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI */
228
229 OUT_PKT4(ring, REG_A6XX_RB_STENCIL_INFO, 1);
230 OUT_RING(ring, 0x00000000); /* RB_STENCIL_INFO */
231 }
232 }
233
234 static bool
235 use_hw_binning(struct fd_batch *batch)
236 {
237 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
238
239 // TODO figure out hw limits for binning
240
241 return fd_binning_enabled && ((gmem->nbins_x * gmem->nbins_y) > 2) &&
242 (batch->num_draws > 0);
243 }
244
245 static void
246 patch_draws(struct fd_batch *batch, enum pc_di_vis_cull_mode vismode)
247 {
248 unsigned i;
249 for (i = 0; i < fd_patch_num_elements(&batch->draw_patches); i++) {
250 struct fd_cs_patch *patch = fd_patch_element(&batch->draw_patches, i);
251 *patch->cs = patch->val | DRAW4(0, 0, 0, vismode);
252 }
253 util_dynarray_resize(&batch->draw_patches, 0);
254 }
255
256 static void
257 update_render_cntl(struct fd_batch *batch, bool binning)
258 {
259 struct fd_ringbuffer *ring = batch->gmem;
260 uint32_t cntl = 0;
261
262 cntl |= A6XX_RB_RENDER_CNTL_UNK4;
263 if (binning)
264 cntl |= A6XX_RB_RENDER_CNTL_BINNING;
265
266 OUT_PKT7(ring, CP_REG_WRITE, 3);
267 OUT_RING(ring, 0x2);
268 OUT_RING(ring, REG_A6XX_RB_RENDER_CNTL);
269 OUT_RING(ring, cntl);
270 }
271
272 static void
273 update_vsc_pipe(struct fd_batch *batch)
274 {
275 struct fd_context *ctx = batch->ctx;
276 struct fd6_context *fd6_ctx = fd6_context(ctx);
277 struct fd_gmem_stateobj *gmem = &ctx->gmem;
278 struct fd_ringbuffer *ring = batch->gmem;
279 int i;
280
281 OUT_PKT4(ring, REG_A6XX_VSC_BIN_SIZE, 3);
282 OUT_RING(ring, A6XX_VSC_BIN_SIZE_WIDTH(gmem->bin_w) |
283 A6XX_VSC_BIN_SIZE_HEIGHT(gmem->bin_h));
284 OUT_RELOCW(ring, fd6_ctx->vsc_data,
285 32 * A6XX_VSC_DATA_PITCH, 0, 0); /* VSC_SIZE_ADDRESS_LO/HI */
286
287 OUT_PKT4(ring, REG_A6XX_VSC_BIN_COUNT, 1);
288 OUT_RING(ring, A6XX_VSC_BIN_COUNT_NX(gmem->nbins_x) |
289 A6XX_VSC_BIN_COUNT_NY(gmem->nbins_y));
290
291 OUT_PKT4(ring, REG_A6XX_VSC_PIPE_CONFIG_REG(0), 32);
292 for (i = 0; i < 32; i++) {
293 struct fd_vsc_pipe *pipe = &ctx->vsc_pipe[i];
294 OUT_RING(ring, A6XX_VSC_PIPE_CONFIG_REG_X(pipe->x) |
295 A6XX_VSC_PIPE_CONFIG_REG_Y(pipe->y) |
296 A6XX_VSC_PIPE_CONFIG_REG_W(pipe->w) |
297 A6XX_VSC_PIPE_CONFIG_REG_H(pipe->h));
298 }
299
300 OUT_PKT4(ring, REG_A6XX_VSC_PIPE_DATA2_ADDRESS_LO, 4);
301 OUT_RELOCW(ring, fd6_ctx->vsc_data2, 0, 0, 0);
302 OUT_RING(ring, A6XX_VSC_DATA2_PITCH);
303 OUT_RING(ring, fd_bo_size(fd6_ctx->vsc_data2));
304
305 OUT_PKT4(ring, REG_A6XX_VSC_PIPE_DATA_ADDRESS_LO, 4);
306 OUT_RELOCW(ring, fd6_ctx->vsc_data, 0, 0, 0);
307 OUT_RING(ring, A6XX_VSC_DATA_PITCH);
308 OUT_RING(ring, fd_bo_size(fd6_ctx->vsc_data));
309 }
310
311 static void
312 set_scissor(struct fd_ringbuffer *ring, uint32_t x1, uint32_t y1, uint32_t x2, uint32_t y2)
313 {
314 OUT_PKT4(ring, REG_A6XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
315 OUT_RING(ring, A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X(x1) |
316 A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(y1));
317 OUT_RING(ring, A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X(x2) |
318 A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(y2));
319
320 OUT_PKT4(ring, REG_A6XX_GRAS_RESOLVE_CNTL_1, 2);
321 OUT_RING(ring, A6XX_GRAS_RESOLVE_CNTL_1_X(x1) |
322 A6XX_GRAS_RESOLVE_CNTL_1_Y(y1));
323 OUT_RING(ring, A6XX_GRAS_RESOLVE_CNTL_2_X(x2) |
324 A6XX_GRAS_RESOLVE_CNTL_2_Y(y2));
325 }
326
327 static void
328 set_bin_size(struct fd_ringbuffer *ring, uint32_t w, uint32_t h, uint32_t flag)
329 {
330 OUT_PKT4(ring, REG_A6XX_GRAS_BIN_CONTROL, 1);
331 OUT_RING(ring, A6XX_GRAS_BIN_CONTROL_BINW(w) |
332 A6XX_GRAS_BIN_CONTROL_BINH(h) | flag);
333
334 OUT_PKT4(ring, REG_A6XX_RB_BIN_CONTROL, 1);
335 OUT_RING(ring, A6XX_RB_BIN_CONTROL_BINW(w) |
336 A6XX_RB_BIN_CONTROL_BINH(h) | flag);
337
338 /* no flag for RB_BIN_CONTROL2... */
339 OUT_PKT4(ring, REG_A6XX_RB_BIN_CONTROL2, 1);
340 OUT_RING(ring, A6XX_RB_BIN_CONTROL2_BINW(w) |
341 A6XX_RB_BIN_CONTROL2_BINH(h));
342 }
343
344 static void
345 emit_binning_pass(struct fd_batch *batch)
346 {
347 struct fd_context *ctx = batch->ctx;
348 struct fd_ringbuffer *ring = batch->gmem;
349 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
350
351 uint32_t x1 = gmem->minx;
352 uint32_t y1 = gmem->miny;
353 uint32_t x2 = gmem->minx + gmem->width - 1;
354 uint32_t y2 = gmem->miny + gmem->height - 1;
355
356 set_scissor(ring, x1, y1, x2, y2);
357
358 emit_marker6(ring, 7);
359 OUT_PKT7(ring, CP_SET_MARKER, 1);
360 OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(RM6_BINNING));
361 emit_marker6(ring, 7);
362
363 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
364 OUT_RING(ring, 0x1);
365
366 OUT_PKT7(ring, CP_SET_MODE, 1);
367 OUT_RING(ring, 0x1);
368
369 OUT_WFI5(ring);
370
371 OUT_PKT4(ring, REG_A6XX_VFD_MODE_CNTL, 1);
372 OUT_RING(ring, A6XX_VFD_MODE_CNTL_BINNING_PASS);
373
374 update_vsc_pipe(batch);
375
376 OUT_PKT4(ring, REG_A6XX_PC_UNKNOWN_9805, 1);
377 OUT_RING(ring, 0x1);
378
379 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A0F8, 1);
380 OUT_RING(ring, 0x1);
381
382 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
383 OUT_RING(ring, UNK_2C);
384
385 OUT_PKT4(ring, REG_A6XX_RB_WINDOW_OFFSET, 1);
386 OUT_RING(ring, A6XX_RB_WINDOW_OFFSET_X(0) |
387 A6XX_RB_WINDOW_OFFSET_Y(0));
388
389 OUT_PKT4(ring, REG_A6XX_SP_TP_WINDOW_OFFSET, 1);
390 OUT_RING(ring, A6XX_SP_TP_WINDOW_OFFSET_X(0) |
391 A6XX_SP_TP_WINDOW_OFFSET_Y(0));
392
393 /* emit IB to binning drawcmds: */
394 fd6_emit_ib(ring, batch->draw);
395
396 fd_reset_wfi(batch);
397
398 OUT_PKT7(ring, CP_SET_DRAW_STATE, 3);
399 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
400 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
401 CP_SET_DRAW_STATE__0_GROUP_ID(0));
402 OUT_RING(ring, CP_SET_DRAW_STATE__1_ADDR_LO(0));
403 OUT_RING(ring, CP_SET_DRAW_STATE__2_ADDR_HI(0));
404
405 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
406 OUT_RING(ring, UNK_2D);
407
408 OUT_PKT7(ring, CP_EVENT_WRITE, 4);
409 OUT_RING(ring, CACHE_FLUSH_TS);
410 OUT_RELOCW(ring, fd6_context(ctx)->blit_mem, 0, 0, 0); /* ADDR_LO/HI */
411 OUT_RING(ring, 0x00000000);
412
413 fd_wfi(batch, ring);
414 }
415
416 static void
417 emit_msaa(struct fd_ringbuffer *ring, unsigned nr)
418 {
419 enum a3xx_msaa_samples samples = fd_msaa_samples(nr);
420
421 OUT_PKT4(ring, REG_A6XX_SP_TP_RAS_MSAA_CNTL, 2);
422 OUT_RING(ring, A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(samples));
423 OUT_RING(ring, A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(samples) |
424 COND(samples == MSAA_ONE, A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE));
425
426 OUT_PKT4(ring, REG_A6XX_GRAS_RAS_MSAA_CNTL, 2);
427 OUT_RING(ring, A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(samples));
428 OUT_RING(ring, A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(samples) |
429 COND(samples == MSAA_ONE, A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE));
430
431 OUT_PKT4(ring, REG_A6XX_RB_RAS_MSAA_CNTL, 2);
432 OUT_RING(ring, A6XX_RB_RAS_MSAA_CNTL_SAMPLES(samples));
433 OUT_RING(ring, A6XX_RB_DEST_MSAA_CNTL_SAMPLES(samples) |
434 COND(samples == MSAA_ONE, A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE));
435
436 OUT_PKT4(ring, REG_A6XX_RB_MSAA_CNTL, 1);
437 OUT_RING(ring, A6XX_RB_MSAA_CNTL_SAMPLES(samples));
438 }
439
440 static void prepare_tile_setup_ib(struct fd_batch *batch);
441 static void prepare_tile_fini_ib(struct fd_batch *batch);
442
443 /* before first tile */
444 static void
445 fd6_emit_tile_init(struct fd_batch *batch)
446 {
447 struct fd_context *ctx = batch->ctx;
448 struct fd_ringbuffer *ring = batch->gmem;
449 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
450 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
451
452 fd6_emit_restore(batch, ring);
453
454 fd6_emit_lrz_flush(ring);
455
456 if (batch->lrz_clear)
457 fd6_emit_ib(ring, batch->lrz_clear);
458
459 fd6_cache_flush(batch, ring);
460
461 prepare_tile_setup_ib(batch);
462 prepare_tile_fini_ib(batch);
463
464 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
465 OUT_RING(ring, 0x0);
466
467 /* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */
468 fd_wfi(batch, ring);
469 OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
470 OUT_RING(ring, 0x7c400004); /* RB_CCU_CNTL */
471
472 emit_zs(ring, pfb->zsbuf, &ctx->gmem);
473 emit_mrt(ring, pfb, &ctx->gmem);
474 emit_msaa(ring, pfb->samples);
475
476 if (use_hw_binning(batch)) {
477 set_bin_size(ring, gmem->bin_w, gmem->bin_h,
478 A6XX_RB_BIN_CONTROL_BINNING_PASS | 0x6000000);
479 update_render_cntl(batch, true);
480 emit_binning_pass(batch);
481 patch_draws(batch, USE_VISIBILITY);
482
483 set_bin_size(ring, gmem->bin_w, gmem->bin_h,
484 A6XX_RB_BIN_CONTROL_USE_VIZ | 0x6000000);
485
486 OUT_PKT4(ring, REG_A6XX_VFD_MODE_CNTL, 1);
487 OUT_RING(ring, 0x0);
488 } else {
489 set_bin_size(ring, gmem->bin_w, gmem->bin_h, 0x6000000);
490 patch_draws(batch, IGNORE_VISIBILITY);
491 }
492
493 update_render_cntl(batch, false);
494 }
495
496 static void
497 set_window_offset(struct fd_ringbuffer *ring, uint32_t x1, uint32_t y1)
498 {
499 OUT_PKT4(ring, REG_A6XX_RB_WINDOW_OFFSET, 1);
500 OUT_RING(ring, A6XX_RB_WINDOW_OFFSET_X(x1) |
501 A6XX_RB_WINDOW_OFFSET_Y(y1));
502
503 OUT_PKT4(ring, REG_A6XX_RB_WINDOW_OFFSET2, 1);
504 OUT_RING(ring, A6XX_RB_WINDOW_OFFSET2_X(x1) |
505 A6XX_RB_WINDOW_OFFSET2_Y(y1));
506
507 OUT_PKT4(ring, REG_A6XX_SP_WINDOW_OFFSET, 1);
508 OUT_RING(ring, A6XX_SP_WINDOW_OFFSET_X(x1) |
509 A6XX_SP_WINDOW_OFFSET_Y(y1));
510
511 OUT_PKT4(ring, REG_A6XX_SP_TP_WINDOW_OFFSET, 1);
512 OUT_RING(ring, A6XX_SP_TP_WINDOW_OFFSET_X(x1) |
513 A6XX_SP_TP_WINDOW_OFFSET_Y(y1));
514 }
515
516 /* before mem2gmem */
517 static void
518 fd6_emit_tile_prep(struct fd_batch *batch, struct fd_tile *tile)
519 {
520 struct fd_context *ctx = batch->ctx;
521 struct fd6_context *fd6_ctx = fd6_context(ctx);
522 struct fd_ringbuffer *ring = batch->gmem;
523
524 OUT_PKT7(ring, CP_SET_MARKER, 1);
525 OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(0x7));
526
527 emit_marker6(ring, 7);
528 OUT_PKT7(ring, CP_SET_MARKER, 1);
529 OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(RM6_GMEM) | 0x10);
530 emit_marker6(ring, 7);
531
532 uint32_t x1 = tile->xoff;
533 uint32_t y1 = tile->yoff;
534 uint32_t x2 = tile->xoff + tile->bin_w - 1;
535 uint32_t y2 = tile->yoff + tile->bin_h - 1;
536
537 set_scissor(ring, x1, y1, x2, y2);
538
539 set_window_offset(ring, x1, y1);
540
541 OUT_PKT4(ring, REG_A6XX_VPC_SO_OVERRIDE, 1);
542 OUT_RING(ring, A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
543
544 if (use_hw_binning(batch)) {
545 struct fd_vsc_pipe *pipe = &ctx->vsc_pipe[tile->p];
546
547 OUT_PKT7(ring, CP_WAIT_FOR_ME, 0);
548
549 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
550 OUT_RING(ring, 0x0);
551
552 OUT_PKT7(ring, CP_SET_MODE, 1);
553 OUT_RING(ring, 0x0);
554
555 OUT_PKT7(ring, CP_SET_BIN_DATA5, 7);
556 OUT_RING(ring, CP_SET_BIN_DATA5_0_VSC_SIZE(pipe->w * pipe->h) |
557 CP_SET_BIN_DATA5_0_VSC_N(tile->n));
558 OUT_RELOC(ring, fd6_ctx->vsc_data, /* VSC_PIPE[p].DATA_ADDRESS */
559 (tile->p * A6XX_VSC_DATA_PITCH), 0, 0);
560 OUT_RELOC(ring, fd6_ctx->vsc_data, /* VSC_SIZE_ADDRESS + (p * 4) */
561 (tile->p * 4) + (32 * A6XX_VSC_DATA_PITCH), 0, 0);
562 OUT_RELOC(ring, fd6_ctx->vsc_data2,
563 (tile->p * A6XX_VSC_DATA2_PITCH), 0, 0);
564 } else {
565 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
566 OUT_RING(ring, 0x1);
567
568 OUT_PKT7(ring, CP_SET_MODE, 1);
569 OUT_RING(ring, 0x0);
570 }
571 }
572
573 static void
574 set_blit_scissor(struct fd_batch *batch, struct fd_ringbuffer *ring)
575 {
576 struct pipe_scissor_state blit_scissor;
577 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
578
579 blit_scissor.minx = batch->max_scissor.minx;
580 blit_scissor.miny = batch->max_scissor.miny;
581 blit_scissor.maxx = MIN2(pfb->width, batch->max_scissor.maxx);
582 blit_scissor.maxy = MIN2(pfb->height, batch->max_scissor.maxy);
583
584 OUT_PKT4(ring, REG_A6XX_RB_BLIT_SCISSOR_TL, 2);
585 OUT_RING(ring,
586 A6XX_RB_BLIT_SCISSOR_TL_X(blit_scissor.minx) |
587 A6XX_RB_BLIT_SCISSOR_TL_Y(blit_scissor.miny));
588 OUT_RING(ring,
589 A6XX_RB_BLIT_SCISSOR_BR_X(blit_scissor.maxx - 1) |
590 A6XX_RB_BLIT_SCISSOR_BR_Y(blit_scissor.maxy - 1));
591 }
592
593 static void
594 emit_blit(struct fd_batch *batch,
595 struct fd_ringbuffer *ring,
596 uint32_t base,
597 struct pipe_surface *psurf,
598 bool stencil)
599 {
600 struct fd_resource_slice *slice;
601 struct fd_resource *rsc = fd_resource(psurf->texture);
602 enum pipe_format pfmt = psurf->format;
603 uint32_t offset;
604
605 /* separate stencil case: */
606 if (stencil) {
607 rsc = rsc->stencil;
608 pfmt = rsc->base.format;
609 }
610
611 slice = fd_resource_slice(rsc, psurf->u.tex.level);
612 offset = fd_resource_offset(rsc, psurf->u.tex.level,
613 psurf->u.tex.first_layer);
614
615 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
616
617 enum a6xx_color_fmt format = fd6_pipe2color(pfmt);
618 uint32_t stride = slice->pitch * rsc->cpp;
619 uint32_t size = slice->size0;
620 enum a3xx_color_swap swap = fd6_pipe2swap(pfmt);
621 enum a3xx_msaa_samples samples =
622 fd_msaa_samples(rsc->base.nr_samples);
623
624 // TODO: tile mode
625 // bool tiled;
626 // tiled = rsc->tile_mode &&
627 // !fd_resource_level_linear(&rsc->base, psurf->u.tex.level);
628
629 OUT_PKT4(ring, REG_A6XX_RB_BLIT_DST_INFO, 5);
630 OUT_RING(ring,
631 A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR) |
632 A6XX_RB_BLIT_DST_INFO_SAMPLES(samples) |
633 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(format) |
634 A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(swap));
635 OUT_RELOCW(ring, rsc->bo, offset, 0, 0); /* RB_BLIT_DST_LO/HI */
636 OUT_RING(ring, A6XX_RB_BLIT_DST_PITCH(stride));
637 OUT_RING(ring, A6XX_RB_BLIT_DST_ARRAY_PITCH(size));
638
639 OUT_PKT4(ring, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
640 OUT_RING(ring, base);
641
642 fd6_emit_blit(batch, ring);
643 }
644
645 static void
646 emit_restore_blit(struct fd_batch *batch,
647 struct fd_ringbuffer *ring,
648 uint32_t base,
649 struct pipe_surface *psurf,
650 unsigned buffer)
651 {
652 uint32_t info = 0;
653 bool stencil = false;
654
655 switch (buffer) {
656 case FD_BUFFER_COLOR:
657 info |= A6XX_RB_BLIT_INFO_UNK0;
658 break;
659 case FD_BUFFER_STENCIL:
660 info |= A6XX_RB_BLIT_INFO_UNK0;
661 stencil = true;
662 break;
663 case FD_BUFFER_DEPTH:
664 info |= A6XX_RB_BLIT_INFO_DEPTH | A6XX_RB_BLIT_INFO_UNK0;
665 break;
666 }
667
668 if (util_format_is_pure_integer(psurf->format))
669 info |= A6XX_RB_BLIT_INFO_INTEGER;
670
671 OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
672 OUT_RING(ring, info | A6XX_RB_BLIT_INFO_GMEM);
673
674 emit_blit(batch, ring, base, psurf, stencil);
675 }
676
677 static void
678 emit_clears(struct fd_batch *batch, struct fd_ringbuffer *ring)
679 {
680 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
681 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
682 enum a3xx_msaa_samples samples = fd_msaa_samples(pfb->samples);
683
684 uint32_t buffers = batch->fast_cleared;
685
686 if (buffers & PIPE_CLEAR_COLOR) {
687
688 for (int i = 0; i < pfb->nr_cbufs; i++) {
689 union pipe_color_union *color = &batch->clear_color[i];
690 union util_color uc = {0};
691
692 if (!pfb->cbufs[i])
693 continue;
694
695 if (!(buffers & (PIPE_CLEAR_COLOR0 << i)))
696 continue;
697
698 enum pipe_format pfmt = pfb->cbufs[i]->format;
699
700 // XXX I think RB_CLEAR_COLOR_DWn wants to take into account SWAP??
701 union pipe_color_union swapped;
702 switch (fd6_pipe2swap(pfmt)) {
703 case WZYX:
704 swapped.ui[0] = color->ui[0];
705 swapped.ui[1] = color->ui[1];
706 swapped.ui[2] = color->ui[2];
707 swapped.ui[3] = color->ui[3];
708 break;
709 case WXYZ:
710 swapped.ui[2] = color->ui[0];
711 swapped.ui[1] = color->ui[1];
712 swapped.ui[0] = color->ui[2];
713 swapped.ui[3] = color->ui[3];
714 break;
715 case ZYXW:
716 swapped.ui[3] = color->ui[0];
717 swapped.ui[0] = color->ui[1];
718 swapped.ui[1] = color->ui[2];
719 swapped.ui[2] = color->ui[3];
720 break;
721 case XYZW:
722 swapped.ui[3] = color->ui[0];
723 swapped.ui[2] = color->ui[1];
724 swapped.ui[1] = color->ui[2];
725 swapped.ui[0] = color->ui[3];
726 break;
727 }
728
729 if (util_format_is_pure_uint(pfmt)) {
730 util_format_write_4ui(pfmt, swapped.ui, 0, &uc, 0, 0, 0, 1, 1);
731 } else if (util_format_is_pure_sint(pfmt)) {
732 util_format_write_4i(pfmt, swapped.i, 0, &uc, 0, 0, 0, 1, 1);
733 } else {
734 util_pack_color(swapped.f, pfmt, &uc);
735 }
736
737 OUT_PKT4(ring, REG_A6XX_RB_BLIT_DST_INFO, 1);
738 OUT_RING(ring, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR) |
739 A6XX_RB_BLIT_DST_INFO_SAMPLES(samples) |
740 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(fd6_pipe2color(pfmt)));
741
742 OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
743 OUT_RING(ring, A6XX_RB_BLIT_INFO_GMEM |
744 A6XX_RB_BLIT_INFO_CLEAR_MASK(0xf));
745
746 OUT_PKT4(ring, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
747 OUT_RING(ring, gmem->cbuf_base[i]);
748
749 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_88D0, 1);
750 OUT_RING(ring, 0);
751
752 OUT_PKT4(ring, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 4);
753 OUT_RING(ring, uc.ui[0]);
754 OUT_RING(ring, uc.ui[1]);
755 OUT_RING(ring, uc.ui[2]);
756 OUT_RING(ring, uc.ui[3]);
757
758 fd6_emit_blit(batch, ring);
759 }
760 }
761
762 const bool has_depth = pfb->zsbuf;
763 const bool has_separate_stencil =
764 has_depth && fd_resource(pfb->zsbuf->texture)->stencil;
765
766 /* First clear depth or combined depth/stencil. */
767 if ((has_depth && (buffers & PIPE_CLEAR_DEPTH)) ||
768 (!has_separate_stencil && (buffers & PIPE_CLEAR_STENCIL))) {
769 enum pipe_format pfmt = pfb->zsbuf->format;
770 uint32_t clear_value;
771 uint32_t mask = 0;
772
773 if (has_separate_stencil) {
774 pfmt = util_format_get_depth_only(pfb->zsbuf->format);
775 clear_value = util_pack_z(pfmt, batch->clear_depth);
776 } else {
777 pfmt = pfb->zsbuf->format;
778 clear_value = util_pack_z_stencil(pfmt, batch->clear_depth,
779 batch->clear_stencil);
780 }
781
782 if (buffers & PIPE_CLEAR_DEPTH)
783 mask |= 0x1;
784
785 if (!has_separate_stencil && (buffers & PIPE_CLEAR_STENCIL))
786 mask |= 0x2;
787
788 OUT_PKT4(ring, REG_A6XX_RB_BLIT_DST_INFO, 1);
789 OUT_RING(ring, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR) |
790 A6XX_RB_BLIT_DST_INFO_SAMPLES(samples) |
791 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(fd6_pipe2color(pfmt)));
792
793 OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
794 OUT_RING(ring, A6XX_RB_BLIT_INFO_GMEM |
795 // XXX UNK0 for separate stencil ??
796 A6XX_RB_BLIT_INFO_DEPTH |
797 A6XX_RB_BLIT_INFO_CLEAR_MASK(mask));
798
799 OUT_PKT4(ring, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
800 OUT_RING(ring, gmem->zsbuf_base[0]);
801
802 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_88D0, 1);
803 OUT_RING(ring, 0);
804
805 OUT_PKT4(ring, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 1);
806 OUT_RING(ring, clear_value);
807
808 fd6_emit_blit(batch, ring);
809 }
810
811 /* Then clear the separate stencil buffer in case of 32 bit depth
812 * formats with separate stencil. */
813 if (has_separate_stencil && (buffers & PIPE_CLEAR_STENCIL)) {
814 OUT_PKT4(ring, REG_A6XX_RB_BLIT_DST_INFO, 1);
815 OUT_RING(ring, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR) |
816 A6XX_RB_BLIT_DST_INFO_SAMPLES(samples) |
817 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(RB6_R8_UINT));
818
819 OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
820 OUT_RING(ring, A6XX_RB_BLIT_INFO_GMEM |
821 //A6XX_RB_BLIT_INFO_UNK0 |
822 A6XX_RB_BLIT_INFO_DEPTH |
823 A6XX_RB_BLIT_INFO_CLEAR_MASK(0x1));
824
825 OUT_PKT4(ring, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
826 OUT_RING(ring, gmem->zsbuf_base[1]);
827
828 OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_88D0, 1);
829 OUT_RING(ring, 0);
830
831 OUT_PKT4(ring, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 1);
832 OUT_RING(ring, batch->clear_stencil & 0xff);
833
834 fd6_emit_blit(batch, ring);
835 }
836 }
837
838 /*
839 * transfer from system memory to gmem
840 */
841 static void
842 emit_restore_blits(struct fd_batch *batch, struct fd_ringbuffer *ring)
843 {
844 struct fd_context *ctx = batch->ctx;
845 struct fd_gmem_stateobj *gmem = &ctx->gmem;
846 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
847
848 if (batch->restore & FD_BUFFER_COLOR) {
849 unsigned i;
850 for (i = 0; i < pfb->nr_cbufs; i++) {
851 if (!pfb->cbufs[i])
852 continue;
853 if (!(batch->restore & (PIPE_CLEAR_COLOR0 << i)))
854 continue;
855 emit_restore_blit(batch, ring, gmem->cbuf_base[i], pfb->cbufs[i],
856 FD_BUFFER_COLOR);
857 }
858 }
859
860 if (batch->restore & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
861 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
862
863 if (!rsc->stencil || (batch->restore & FD_BUFFER_DEPTH)) {
864 emit_restore_blit(batch, ring, gmem->zsbuf_base[0], pfb->zsbuf,
865 FD_BUFFER_DEPTH);
866 }
867 if (rsc->stencil && (batch->restore & FD_BUFFER_STENCIL)) {
868 emit_restore_blit(batch, ring, gmem->zsbuf_base[1], pfb->zsbuf,
869 FD_BUFFER_STENCIL);
870 }
871 }
872 }
873
874 static void
875 prepare_tile_setup_ib(struct fd_batch *batch)
876 {
877 batch->tile_setup = fd_submit_new_ringbuffer(batch->submit, 0x1000,
878 FD_RINGBUFFER_STREAMING);
879
880 set_blit_scissor(batch, batch->tile_setup);
881
882 emit_restore_blits(batch, batch->tile_setup);
883 emit_clears(batch, batch->tile_setup);
884 }
885
886 /*
887 * transfer from system memory to gmem
888 */
889 static void
890 fd6_emit_tile_mem2gmem(struct fd_batch *batch, struct fd_tile *tile)
891 {
892 }
893
894 /* before IB to rendering cmds: */
895 static void
896 fd6_emit_tile_renderprep(struct fd_batch *batch, struct fd_tile *tile)
897 {
898 fd6_emit_ib(batch->gmem, batch->tile_setup);
899 }
900
901 static void
902 emit_resolve_blit(struct fd_batch *batch,
903 struct fd_ringbuffer *ring,
904 uint32_t base,
905 struct pipe_surface *psurf,
906 unsigned buffer)
907 {
908 uint32_t info = 0;
909 bool stencil = false;
910
911 if (!fd_resource(psurf->texture)->valid)
912 return;
913
914 switch (buffer) {
915 case FD_BUFFER_COLOR:
916 break;
917 case FD_BUFFER_STENCIL:
918 info |= A6XX_RB_BLIT_INFO_UNK0;
919 stencil = true;
920 break;
921 case FD_BUFFER_DEPTH:
922 info |= A6XX_RB_BLIT_INFO_DEPTH;
923 break;
924 }
925
926 if (util_format_is_pure_integer(psurf->format))
927 info |= A6XX_RB_BLIT_INFO_INTEGER;
928
929 OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
930 OUT_RING(ring, info);
931
932 emit_blit(batch, ring, base, psurf, stencil);
933 }
934
935 /*
936 * transfer from gmem to system memory (ie. normal RAM)
937 */
938
939 static void
940 prepare_tile_fini_ib(struct fd_batch *batch)
941 {
942 struct fd_context *ctx = batch->ctx;
943 struct fd_gmem_stateobj *gmem = &ctx->gmem;
944 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
945 struct fd_ringbuffer *ring;
946
947 batch->tile_fini = fd_submit_new_ringbuffer(batch->submit, 0x1000,
948 FD_RINGBUFFER_STREAMING);
949 ring = batch->tile_fini;
950
951 if (use_hw_binning(batch)) {
952 OUT_PKT7(ring, CP_SET_MARKER, 1);
953 OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(0x5) | 0x10);
954 }
955
956 OUT_PKT7(ring, CP_SET_DRAW_STATE, 3);
957 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
958 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
959 CP_SET_DRAW_STATE__0_GROUP_ID(0));
960 OUT_RING(ring, CP_SET_DRAW_STATE__1_ADDR_LO(0));
961 OUT_RING(ring, CP_SET_DRAW_STATE__2_ADDR_HI(0));
962
963 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
964 OUT_RING(ring, 0x0);
965
966 emit_marker6(ring, 7);
967 OUT_PKT7(ring, CP_SET_MARKER, 1);
968 OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE) | 0x10);
969 emit_marker6(ring, 7);
970
971 set_blit_scissor(batch, ring);
972
973 if (batch->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
974 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
975
976 if (!rsc->stencil || (batch->resolve & FD_BUFFER_DEPTH)) {
977 emit_resolve_blit(batch, ring,
978 gmem->zsbuf_base[0], pfb->zsbuf,
979 FD_BUFFER_DEPTH);
980 }
981 if (rsc->stencil && (batch->resolve & FD_BUFFER_STENCIL)) {
982 emit_resolve_blit(batch, ring,
983 gmem->zsbuf_base[1], pfb->zsbuf,
984 FD_BUFFER_STENCIL);
985 }
986 }
987
988 if (batch->resolve & FD_BUFFER_COLOR) {
989 unsigned i;
990 for (i = 0; i < pfb->nr_cbufs; i++) {
991 if (!pfb->cbufs[i])
992 continue;
993 if (!(batch->resolve & (PIPE_CLEAR_COLOR0 << i)))
994 continue;
995 emit_resolve_blit(batch, ring, gmem->cbuf_base[i], pfb->cbufs[i],
996 FD_BUFFER_COLOR);
997 }
998 }
999 }
1000
1001 static void
1002 fd6_emit_tile_gmem2mem(struct fd_batch *batch, struct fd_tile *tile)
1003 {
1004 fd6_emit_ib(batch->gmem, batch->tile_fini);
1005 }
1006
1007 static void
1008 fd6_emit_tile_fini(struct fd_batch *batch)
1009 {
1010 struct fd_ringbuffer *ring = batch->gmem;
1011
1012 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_CNTL, 1);
1013 OUT_RING(ring, A6XX_GRAS_LRZ_CNTL_ENABLE | A6XX_GRAS_LRZ_CNTL_UNK3);
1014
1015 fd6_emit_lrz_flush(ring);
1016
1017 fd6_event_write(batch, ring, CACHE_FLUSH_TS, true);
1018 }
1019
1020 static void
1021 fd6_emit_sysmem_prep(struct fd_batch *batch)
1022 {
1023 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
1024 struct fd_ringbuffer *ring = batch->gmem;
1025
1026 fd6_emit_restore(batch, ring);
1027
1028 fd6_emit_lrz_flush(ring);
1029
1030 emit_marker6(ring, 7);
1031 OUT_PKT7(ring, CP_SET_MARKER, 1);
1032 OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(RM6_BYPASS) | 0x10); /* | 0x10 ? */
1033 emit_marker6(ring, 7);
1034
1035 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1036 OUT_RING(ring, 0x0);
1037
1038 fd6_event_write(batch, ring, PC_CCU_INVALIDATE_COLOR, false);
1039 fd6_cache_flush(batch, ring);
1040
1041 #if 0
1042 OUT_PKT4(ring, REG_A6XX_PC_POWER_CNTL, 1);
1043 OUT_RING(ring, 0x00000003); /* PC_POWER_CNTL */
1044 #endif
1045
1046 #if 0
1047 OUT_PKT4(ring, REG_A6XX_VFD_POWER_CNTL, 1);
1048 OUT_RING(ring, 0x00000003); /* VFD_POWER_CNTL */
1049 #endif
1050
1051 /* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */
1052 fd_wfi(batch, ring);
1053 OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
1054 OUT_RING(ring, 0x10000000); /* RB_CCU_CNTL */
1055
1056 set_scissor(ring, 0, 0, pfb->width - 1, pfb->height - 1);
1057
1058 set_window_offset(ring, 0, 0);
1059
1060 set_bin_size(ring, 0, 0, 0xc00000); /* 0xc00000 = BYPASS? */
1061
1062 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
1063 OUT_RING(ring, 0x1);
1064
1065 patch_draws(batch, IGNORE_VISIBILITY);
1066
1067 emit_zs(ring, pfb->zsbuf, NULL);
1068 emit_mrt(ring, pfb, NULL);
1069 emit_msaa(ring, pfb->samples);
1070 }
1071
1072 static void
1073 fd6_emit_sysmem_fini(struct fd_batch *batch)
1074 {
1075 struct fd_ringbuffer *ring = batch->gmem;
1076
1077 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
1078 OUT_RING(ring, 0x0);
1079
1080 fd6_emit_lrz_flush(ring);
1081
1082 fd6_event_write(batch, ring, UNK_1D, true);
1083 }
1084
1085 void
1086 fd6_gmem_init(struct pipe_context *pctx)
1087 {
1088 struct fd_context *ctx = fd_context(pctx);
1089
1090 ctx->emit_tile_init = fd6_emit_tile_init;
1091 ctx->emit_tile_prep = fd6_emit_tile_prep;
1092 ctx->emit_tile_mem2gmem = fd6_emit_tile_mem2gmem;
1093 ctx->emit_tile_renderprep = fd6_emit_tile_renderprep;
1094 ctx->emit_tile_gmem2mem = fd6_emit_tile_gmem2mem;
1095 ctx->emit_tile_fini = fd6_emit_tile_fini;
1096 ctx->emit_sysmem_prep = fd6_emit_sysmem_prep;
1097 ctx->emit_sysmem_fini = fd6_emit_sysmem_fini;
1098 }