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freedreno/a6xx: Clear z32 and separate stencil with blitter
[mesa.git] / src / gallium / drivers / freedreno / a6xx / fd6_gmem.c
1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 * Authors:
25 * Rob Clark <robclark@freedesktop.org>
26 */
27
28 #include <stdio.h>
29
30 #include "pipe/p_state.h"
31 #include "util/u_string.h"
32 #include "util/u_memory.h"
33 #include "util/u_inlines.h"
34 #include "util/u_format.h"
35
36 #include "freedreno_draw.h"
37 #include "freedreno_state.h"
38 #include "freedreno_resource.h"
39
40 #include "fd6_gmem.h"
41 #include "fd6_context.h"
42 #include "fd6_draw.h"
43 #include "fd6_emit.h"
44 #include "fd6_program.h"
45 #include "fd6_format.h"
46 #include "fd6_zsa.h"
47
48 /* some bits in common w/ a4xx: */
49 #include "a4xx/fd4_draw.h"
50
51 static void
52 emit_mrt(struct fd_ringbuffer *ring, struct pipe_framebuffer_state *pfb,
53 struct fd_gmem_stateobj *gmem)
54 {
55 unsigned char mrt_comp[A6XX_MAX_RENDER_TARGETS] = {0};
56 unsigned srgb_cntl = 0;
57 unsigned i;
58
59 for (i = 0; i < pfb->nr_cbufs; i++) {
60 enum a6xx_color_fmt format = 0;
61 enum a3xx_color_swap swap = WZYX;
62 bool sint = false, uint = false;
63 struct fd_resource *rsc = NULL;
64 struct fd_resource_slice *slice = NULL;
65 uint32_t stride = 0;
66 uint32_t offset = 0;
67
68 if (!pfb->cbufs[i])
69 continue;
70
71 mrt_comp[i] = 0xf;
72
73 struct pipe_surface *psurf = pfb->cbufs[i];
74 enum pipe_format pformat = psurf->format;
75 rsc = fd_resource(psurf->texture);
76 if (!rsc->bo)
77 continue;
78
79 uint32_t base = gmem ? gmem->cbuf_base[i] : 0;
80 slice = fd_resource_slice(rsc, psurf->u.tex.level);
81 format = fd6_pipe2color(pformat);
82 swap = fd6_pipe2swap(pformat);
83 sint = util_format_is_pure_sint(pformat);
84 uint = util_format_is_pure_uint(pformat);
85
86 if (util_format_is_srgb(pformat))
87 srgb_cntl |= (1 << i);
88
89 offset = fd_resource_offset(rsc, psurf->u.tex.level,
90 psurf->u.tex.first_layer);
91
92 stride = slice->pitch * rsc->cpp;
93
94 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
95 debug_assert((offset + slice->size0) <= fd_bo_size(rsc->bo));
96
97 OUT_PKT4(ring, REG_A6XX_RB_MRT_BUF_INFO(i), 6);
98 OUT_RING(ring, A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format) |
99 A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(rsc->tile_mode) |
100 A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(swap));
101 OUT_RING(ring, A6XX_RB_MRT_PITCH(stride));
102 OUT_RING(ring, A6XX_RB_MRT_ARRAY_PITCH(slice->size0));
103 OUT_RELOCW(ring, rsc->bo, offset, 0, 0); /* BASE_LO/HI */
104 OUT_RING(ring, base); /* RB_MRT[i].BASE_GMEM */
105 OUT_PKT4(ring, REG_A6XX_SP_FS_MRT_REG(i), 1);
106 OUT_RING(ring, A6XX_SP_FS_MRT_REG_COLOR_FORMAT(format) |
107 COND(sint, A6XX_SP_FS_MRT_REG_COLOR_SINT) |
108 COND(uint, A6XX_SP_FS_MRT_REG_COLOR_UINT));
109
110 #if 0
111 /* when we support UBWC, these would be the system memory
112 * addr/pitch/etc:
113 */
114 OUT_PKT4(ring, REG_A6XX_RB_MRT_FLAG_BUFFER(i), 4);
115 OUT_RING(ring, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_LO */
116 OUT_RING(ring, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_HI */
117 OUT_RING(ring, A6XX_RB_MRT_FLAG_BUFFER_PITCH(0));
118 OUT_RING(ring, A6XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(0));
119 #endif
120 }
121
122 OUT_PKT4(ring, REG_A6XX_RB_SRGB_CNTL, 1);
123 OUT_RING(ring, srgb_cntl);
124
125 OUT_PKT4(ring, REG_A6XX_SP_SRGB_CNTL, 1);
126 OUT_RING(ring, srgb_cntl);
127
128 OUT_PKT4(ring, REG_A6XX_RB_RENDER_COMPONENTS, 1);
129 OUT_RING(ring, A6XX_RB_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
130 A6XX_RB_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
131 A6XX_RB_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
132 A6XX_RB_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
133 A6XX_RB_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
134 A6XX_RB_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
135 A6XX_RB_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
136 A6XX_RB_RENDER_COMPONENTS_RT7(mrt_comp[7]));
137
138 OUT_PKT4(ring, REG_A6XX_SP_FS_RENDER_COMPONENTS, 1);
139 OUT_RING(ring,
140 A6XX_SP_FS_RENDER_COMPONENTS_RT0(mrt_comp[0]) |
141 A6XX_SP_FS_RENDER_COMPONENTS_RT1(mrt_comp[1]) |
142 A6XX_SP_FS_RENDER_COMPONENTS_RT2(mrt_comp[2]) |
143 A6XX_SP_FS_RENDER_COMPONENTS_RT3(mrt_comp[3]) |
144 A6XX_SP_FS_RENDER_COMPONENTS_RT4(mrt_comp[4]) |
145 A6XX_SP_FS_RENDER_COMPONENTS_RT5(mrt_comp[5]) |
146 A6XX_SP_FS_RENDER_COMPONENTS_RT6(mrt_comp[6]) |
147 A6XX_SP_FS_RENDER_COMPONENTS_RT7(mrt_comp[7]));
148 }
149
150 static void
151 emit_zs(struct fd_ringbuffer *ring, struct pipe_surface *zsbuf,
152 struct fd_gmem_stateobj *gmem)
153 {
154 if (zsbuf) {
155 struct fd_resource *rsc = fd_resource(zsbuf->texture);
156 enum a6xx_depth_format fmt = fd6_pipe2depth(zsbuf->format);
157 struct fd_resource_slice *slice = fd_resource_slice(rsc, 0);
158 uint32_t stride = slice->pitch * rsc->cpp;
159 uint32_t size = slice->size0;
160 uint32_t base = gmem ? gmem->zsbuf_base[0] : 0;
161
162 OUT_PKT4(ring, REG_A6XX_RB_DEPTH_BUFFER_INFO, 6);
163 OUT_RING(ring, A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(fmt));
164 OUT_RING(ring, A6XX_RB_DEPTH_BUFFER_PITCH(stride));
165 OUT_RING(ring, A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(size));
166 OUT_RELOCW(ring, rsc->bo, 0, 0, 0); /* RB_DEPTH_BUFFER_BASE_LO/HI */
167 OUT_RING(ring, base); /* RB_DEPTH_BUFFER_BASE_GMEM */
168
169 OUT_PKT4(ring, REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO, 1);
170 OUT_RING(ring, A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(fmt));
171
172 OUT_PKT4(ring, REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO, 3);
173 OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
174 OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
175 OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_PITCH */
176
177 if (rsc->lrz) {
178 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO, 5);
179 OUT_RELOCW(ring, rsc->lrz, 0, 0, 0);
180 OUT_RING(ring, A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH(rsc->lrz_pitch));
181 //OUT_RELOCW(ring, rsc->lrz, 0, 0, 0); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO/HI */
182 // XXX a6xx seems to use a different buffer here.. not sure what for..
183 OUT_RING(ring, 0x00000000);
184 OUT_RING(ring, 0x00000000);
185 } else {
186 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO, 5);
187 OUT_RING(ring, 0x00000000);
188 OUT_RING(ring, 0x00000000);
189 OUT_RING(ring, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
190 OUT_RING(ring, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO */
191 OUT_RING(ring, 0x00000000);
192 }
193
194 if (rsc->stencil) {
195 struct fd_resource_slice *slice = fd_resource_slice(rsc->stencil, 0);
196 stride = slice->pitch * rsc->cpp;
197 size = slice->size0;
198 uint32_t base = gmem ? gmem->zsbuf_base[1] : 0;
199
200 OUT_PKT4(ring, REG_A6XX_RB_STENCIL_INFO, 6);
201 OUT_RING(ring, A6XX_RB_STENCIL_INFO_SEPARATE_STENCIL);
202 OUT_RING(ring, A6XX_RB_STENCIL_BUFFER_PITCH(stride));
203 OUT_RING(ring, A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(size));
204 OUT_RELOCW(ring, rsc->stencil->bo, 0, 0, 0); /* RB_STENCIL_BASE_LO/HI */
205 OUT_RING(ring, base); /* RB_STENCIL_BASE_LO */
206 } else {
207 OUT_PKT4(ring, REG_A6XX_RB_STENCIL_INFO, 1);
208 OUT_RING(ring, 0x00000000); /* RB_STENCIL_INFO */
209 }
210 } else {
211 OUT_PKT4(ring, REG_A6XX_RB_DEPTH_BUFFER_INFO, 6);
212 OUT_RING(ring, A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH6_NONE));
213 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_PITCH */
214 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_ARRAY_PITCH */
215 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_BASE_LO */
216 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_BASE_HI */
217 OUT_RING(ring, 0x00000000); /* RB_DEPTH_BUFFER_BASE_GMEM */
218
219 OUT_PKT4(ring, REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO, 1);
220 OUT_RING(ring, A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH6_NONE));
221
222 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO, 5);
223 OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
224 OUT_RING(ring, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
225 OUT_RING(ring, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
226 OUT_RING(ring, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO */
227 OUT_RING(ring, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI */
228
229 OUT_PKT4(ring, REG_A6XX_RB_STENCIL_INFO, 1);
230 OUT_RING(ring, 0x00000000); /* RB_STENCIL_INFO */
231 }
232 }
233
234 static bool
235 use_hw_binning(struct fd_batch *batch)
236 {
237 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
238
239 // TODO figure out hw limits for binning
240
241 return fd_binning_enabled && ((gmem->nbins_x * gmem->nbins_y) > 2) &&
242 (batch->num_draws > 0);
243 }
244
245 static void
246 patch_draws(struct fd_batch *batch, enum pc_di_vis_cull_mode vismode)
247 {
248 unsigned i;
249 for (i = 0; i < fd_patch_num_elements(&batch->draw_patches); i++) {
250 struct fd_cs_patch *patch = fd_patch_element(&batch->draw_patches, i);
251 *patch->cs = patch->val | DRAW4(0, 0, 0, vismode);
252 }
253 util_dynarray_resize(&batch->draw_patches, 0);
254 }
255
256 static void
257 patch_gmem_bases(struct fd_batch *batch)
258 {
259 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
260 unsigned i;
261
262 for (i = 0; i < fd_patch_num_elements(&batch->gmem_patches); i++) {
263 struct fd_cs_patch *patch = fd_patch_element(&batch->gmem_patches, i);
264 if (patch->val < MAX_RENDER_TARGETS)
265 *patch->cs = gmem->cbuf_base[patch->val];
266 else
267 *patch->cs = gmem->zsbuf_base[patch->val - MAX_RENDER_TARGETS];
268 }
269 util_dynarray_resize(&batch->gmem_patches, 0);
270 }
271
272 static void
273 update_render_cntl(struct fd_batch *batch, bool binning)
274 {
275 struct fd_ringbuffer *ring = batch->gmem;
276 uint32_t cntl = 0;
277
278 cntl |= A6XX_RB_RENDER_CNTL_UNK4;
279 if (binning)
280 cntl |= A6XX_RB_RENDER_CNTL_BINNING;
281
282 OUT_PKT7(ring, CP_REG_WRITE, 3);
283 OUT_RING(ring, 0x2);
284 OUT_RING(ring, REG_A6XX_RB_RENDER_CNTL);
285 OUT_RING(ring, cntl);
286 }
287
288 static void
289 update_vsc_pipe(struct fd_batch *batch)
290 {
291 struct fd_context *ctx = batch->ctx;
292 struct fd6_context *fd6_ctx = fd6_context(ctx);
293 struct fd_gmem_stateobj *gmem = &ctx->gmem;
294 struct fd_ringbuffer *ring = batch->gmem;
295 int i;
296
297 OUT_PKT4(ring, REG_A6XX_VSC_BIN_SIZE, 3);
298 OUT_RING(ring, A6XX_VSC_BIN_SIZE_WIDTH(gmem->bin_w) |
299 A6XX_VSC_BIN_SIZE_HEIGHT(gmem->bin_h));
300 OUT_RELOCW(ring, fd6_ctx->vsc_data,
301 32 * A6XX_VSC_DATA_PITCH, 0, 0); /* VSC_SIZE_ADDRESS_LO/HI */
302
303 OUT_PKT4(ring, REG_A6XX_VSC_BIN_COUNT, 1);
304 OUT_RING(ring, A6XX_VSC_BIN_COUNT_NX(gmem->nbins_x) |
305 A6XX_VSC_BIN_COUNT_NY(gmem->nbins_y));
306
307 OUT_PKT4(ring, REG_A6XX_VSC_PIPE_CONFIG_REG(0), 32);
308 for (i = 0; i < 32; i++) {
309 struct fd_vsc_pipe *pipe = &ctx->vsc_pipe[i];
310 OUT_RING(ring, A6XX_VSC_PIPE_CONFIG_REG_X(pipe->x) |
311 A6XX_VSC_PIPE_CONFIG_REG_Y(pipe->y) |
312 A6XX_VSC_PIPE_CONFIG_REG_W(pipe->w) |
313 A6XX_VSC_PIPE_CONFIG_REG_H(pipe->h));
314 }
315
316 OUT_PKT4(ring, REG_A6XX_VSC_PIPE_DATA2_ADDRESS_LO, 4);
317 OUT_RELOCW(ring, fd6_ctx->vsc_data2, 0, 0, 0);
318 OUT_RING(ring, A6XX_VSC_DATA2_PITCH);
319 OUT_RING(ring, fd_bo_size(fd6_ctx->vsc_data2));
320
321 OUT_PKT4(ring, REG_A6XX_VSC_PIPE_DATA_ADDRESS_LO, 4);
322 OUT_RELOCW(ring, fd6_ctx->vsc_data, 0, 0, 0);
323 OUT_RING(ring, A6XX_VSC_DATA_PITCH);
324 OUT_RING(ring, fd_bo_size(fd6_ctx->vsc_data));
325 }
326
327 static void
328 set_scissor(struct fd_ringbuffer *ring, uint32_t x1, uint32_t y1, uint32_t x2, uint32_t y2)
329 {
330 OUT_PKT4(ring, REG_A6XX_GRAS_SC_WINDOW_SCISSOR_TL, 2);
331 OUT_RING(ring, A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X(x1) |
332 A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(y1));
333 OUT_RING(ring, A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X(x2) |
334 A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(y2));
335
336 OUT_PKT4(ring, REG_A6XX_GRAS_RESOLVE_CNTL_1, 2);
337 OUT_RING(ring, A6XX_GRAS_RESOLVE_CNTL_1_X(x1) |
338 A6XX_GRAS_RESOLVE_CNTL_1_Y(y1));
339 OUT_RING(ring, A6XX_GRAS_RESOLVE_CNTL_2_X(x2) |
340 A6XX_GRAS_RESOLVE_CNTL_2_Y(y2));
341 }
342
343 static void
344 set_bin_size(struct fd_ringbuffer *ring, uint32_t w, uint32_t h, uint32_t flag)
345 {
346 OUT_PKT4(ring, REG_A6XX_GRAS_BIN_CONTROL, 1);
347 OUT_RING(ring, A6XX_GRAS_BIN_CONTROL_BINW(w) |
348 A6XX_GRAS_BIN_CONTROL_BINH(h) | flag);
349
350 OUT_PKT4(ring, REG_A6XX_RB_BIN_CONTROL, 1);
351 OUT_RING(ring, A6XX_RB_BIN_CONTROL_BINW(w) |
352 A6XX_RB_BIN_CONTROL_BINH(h) | flag);
353
354 /* no flag for RB_BIN_CONTROL2... */
355 OUT_PKT4(ring, REG_A6XX_RB_BIN_CONTROL2, 1);
356 OUT_RING(ring, A6XX_RB_BIN_CONTROL2_BINW(w) |
357 A6XX_RB_BIN_CONTROL2_BINH(h));
358 }
359
360 static void
361 emit_binning_pass(struct fd_batch *batch)
362 {
363 struct fd_context *ctx = batch->ctx;
364 struct fd_ringbuffer *ring = batch->gmem;
365 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
366
367 uint32_t x1 = gmem->minx;
368 uint32_t y1 = gmem->miny;
369 uint32_t x2 = gmem->minx + gmem->width - 1;
370 uint32_t y2 = gmem->miny + gmem->height - 1;
371
372 set_scissor(ring, x1, y1, x2, y2);
373
374 emit_marker6(ring, 7);
375 OUT_PKT7(ring, CP_SET_MARKER, 1);
376 OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(RM6_BINNING));
377 emit_marker6(ring, 7);
378
379 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
380 OUT_RING(ring, 0x1);
381
382 OUT_PKT7(ring, CP_SET_MODE, 1);
383 OUT_RING(ring, 0x1);
384
385 OUT_WFI5(ring);
386
387 OUT_PKT4(ring, REG_A6XX_VFD_MODE_CNTL, 1);
388 OUT_RING(ring, A6XX_VFD_MODE_CNTL_BINNING_PASS);
389
390 update_vsc_pipe(batch);
391
392 OUT_PKT4(ring, REG_A6XX_PC_UNKNOWN_9805, 1);
393 OUT_RING(ring, 0x1);
394
395 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A0F8, 1);
396 OUT_RING(ring, 0x1);
397
398 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
399 OUT_RING(ring, UNK_2C);
400
401 OUT_PKT4(ring, REG_A6XX_RB_WINDOW_OFFSET, 1);
402 OUT_RING(ring, A6XX_RB_WINDOW_OFFSET_X(0) |
403 A6XX_RB_WINDOW_OFFSET_Y(0));
404
405 OUT_PKT4(ring, REG_A6XX_SP_TP_WINDOW_OFFSET, 1);
406 OUT_RING(ring, A6XX_SP_TP_WINDOW_OFFSET_X(0) |
407 A6XX_SP_TP_WINDOW_OFFSET_Y(0));
408
409 /* emit IB to binning drawcmds: */
410 fd6_emit_ib(ring, batch->draw);
411
412 fd_reset_wfi(batch);
413
414 OUT_PKT7(ring, CP_SET_DRAW_STATE, 3);
415 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
416 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
417 CP_SET_DRAW_STATE__0_GROUP_ID(0));
418 OUT_RING(ring, CP_SET_DRAW_STATE__1_ADDR_LO(0));
419 OUT_RING(ring, CP_SET_DRAW_STATE__2_ADDR_HI(0));
420
421 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
422 OUT_RING(ring, UNK_2D);
423
424 OUT_PKT7(ring, CP_EVENT_WRITE, 4);
425 OUT_RING(ring, CACHE_FLUSH_TS);
426 OUT_RELOCW(ring, fd6_context(ctx)->blit_mem, 0, 0, 0); /* ADDR_LO/HI */
427 OUT_RING(ring, 0x00000000);
428
429 fd_wfi(batch, ring);
430 }
431
432 static void
433 disable_msaa(struct fd_ringbuffer *ring)
434 {
435 // TODO MSAA
436 OUT_PKT4(ring, REG_A6XX_SP_TP_RAS_MSAA_CNTL, 2);
437 OUT_RING(ring, A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(MSAA_ONE));
438 OUT_RING(ring, A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(MSAA_ONE) |
439 A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE);
440
441 OUT_PKT4(ring, REG_A6XX_GRAS_RAS_MSAA_CNTL, 2);
442 OUT_RING(ring, A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(MSAA_ONE));
443 OUT_RING(ring, A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(MSAA_ONE) |
444 A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE);
445
446 OUT_PKT4(ring, REG_A6XX_RB_RAS_MSAA_CNTL, 2);
447 OUT_RING(ring, A6XX_RB_RAS_MSAA_CNTL_SAMPLES(MSAA_ONE));
448 OUT_RING(ring, A6XX_RB_DEST_MSAA_CNTL_SAMPLES(MSAA_ONE) |
449 A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE);
450 }
451
452 /* before first tile */
453 static void
454 fd6_emit_tile_init(struct fd_batch *batch)
455 {
456 struct fd_context *ctx = batch->ctx;
457 struct fd_ringbuffer *ring = batch->gmem;
458 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
459 struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
460
461 fd6_emit_restore(batch, ring);
462
463 fd6_emit_lrz_flush(ring);
464
465 if (batch->lrz_clear)
466 fd6_emit_ib(ring, batch->lrz_clear);
467
468 fd6_cache_flush(batch, ring);
469
470 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
471 OUT_RING(ring, 0x0);
472
473 /* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */
474 fd_wfi(batch, ring);
475 OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
476 OUT_RING(ring, 0x7c400004); /* RB_CCU_CNTL */
477
478 emit_zs(ring, pfb->zsbuf, &ctx->gmem);
479 emit_mrt(ring, pfb, &ctx->gmem);
480
481 patch_gmem_bases(batch);
482
483 disable_msaa(ring);
484
485 if (use_hw_binning(batch)) {
486 set_bin_size(ring, gmem->bin_w, gmem->bin_h,
487 A6XX_RB_BIN_CONTROL_BINNING_PASS | 0x6000000);
488 update_render_cntl(batch, true);
489 emit_binning_pass(batch);
490 patch_draws(batch, USE_VISIBILITY);
491
492 set_bin_size(ring, gmem->bin_w, gmem->bin_h,
493 A6XX_RB_BIN_CONTROL_USE_VIZ | 0x6000000);
494
495 OUT_PKT4(ring, REG_A6XX_VFD_MODE_CNTL, 1);
496 OUT_RING(ring, 0x0);
497 } else {
498 set_bin_size(ring, gmem->bin_w, gmem->bin_h, 0x6000000);
499 patch_draws(batch, IGNORE_VISIBILITY);
500 }
501
502 update_render_cntl(batch, false);
503 }
504
505 static void
506 set_window_offset(struct fd_ringbuffer *ring, uint32_t x1, uint32_t y1)
507 {
508 OUT_PKT4(ring, REG_A6XX_RB_WINDOW_OFFSET, 1);
509 OUT_RING(ring, A6XX_RB_WINDOW_OFFSET_X(x1) |
510 A6XX_RB_WINDOW_OFFSET_Y(y1));
511
512 OUT_PKT4(ring, REG_A6XX_RB_WINDOW_OFFSET2, 1);
513 OUT_RING(ring, A6XX_RB_WINDOW_OFFSET2_X(x1) |
514 A6XX_RB_WINDOW_OFFSET2_Y(y1));
515
516 OUT_PKT4(ring, REG_A6XX_SP_WINDOW_OFFSET, 1);
517 OUT_RING(ring, A6XX_SP_WINDOW_OFFSET_X(x1) |
518 A6XX_SP_WINDOW_OFFSET_Y(y1));
519
520 OUT_PKT4(ring, REG_A6XX_SP_TP_WINDOW_OFFSET, 1);
521 OUT_RING(ring, A6XX_SP_TP_WINDOW_OFFSET_X(x1) |
522 A6XX_SP_TP_WINDOW_OFFSET_Y(y1));
523 }
524
525 /* before mem2gmem */
526 static void
527 fd6_emit_tile_prep(struct fd_batch *batch, struct fd_tile *tile)
528 {
529 struct fd_context *ctx = batch->ctx;
530 struct fd6_context *fd6_ctx = fd6_context(ctx);
531 struct fd_ringbuffer *ring = batch->gmem;
532
533 OUT_PKT7(ring, CP_SET_MARKER, 1);
534 OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(0x7));
535
536 emit_marker6(ring, 7);
537 OUT_PKT7(ring, CP_SET_MARKER, 1);
538 OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(RM6_GMEM) | 0x10);
539 emit_marker6(ring, 7);
540
541 uint32_t x1 = tile->xoff;
542 uint32_t y1 = tile->yoff;
543 uint32_t x2 = tile->xoff + tile->bin_w - 1;
544 uint32_t y2 = tile->yoff + tile->bin_h - 1;
545
546 set_scissor(ring, x1, y1, x2, y2);
547
548 set_window_offset(ring, x1, y1);
549
550 OUT_PKT4(ring, REG_A6XX_VPC_SO_OVERRIDE, 1);
551 OUT_RING(ring, A6XX_VPC_SO_OVERRIDE_SO_DISABLE);
552
553 if (use_hw_binning(batch)) {
554 struct fd_vsc_pipe *pipe = &ctx->vsc_pipe[tile->p];
555
556 OUT_PKT7(ring, CP_WAIT_FOR_ME, 0);
557
558 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
559 OUT_RING(ring, 0x0);
560
561 OUT_PKT7(ring, CP_SET_MODE, 1);
562 OUT_RING(ring, 0x0);
563
564 OUT_PKT7(ring, CP_SET_BIN_DATA5, 7);
565 OUT_RING(ring, CP_SET_BIN_DATA5_0_VSC_SIZE(pipe->w * pipe->h) |
566 CP_SET_BIN_DATA5_0_VSC_N(tile->n));
567 OUT_RELOC(ring, fd6_ctx->vsc_data, /* VSC_PIPE[p].DATA_ADDRESS */
568 (tile->p * A6XX_VSC_DATA_PITCH), 0, 0);
569 OUT_RELOC(ring, fd6_ctx->vsc_data, /* VSC_SIZE_ADDRESS + (p * 4) */
570 (tile->p * 4) + (32 * A6XX_VSC_DATA_PITCH), 0, 0);
571 OUT_RELOC(ring, fd6_ctx->vsc_data2,
572 (tile->p * A6XX_VSC_DATA2_PITCH), 0, 0);
573 } else {
574 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
575 OUT_RING(ring, 0x1);
576
577 OUT_PKT7(ring, CP_SET_MODE, 1);
578 OUT_RING(ring, 0x0);
579 }
580 }
581
582 static void
583 set_blit_scissor(struct fd_batch *batch)
584 {
585 struct fd_ringbuffer *ring = batch->gmem;
586 struct pipe_scissor_state blit_scissor;
587 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
588
589 blit_scissor.minx = batch->max_scissor.minx;
590 blit_scissor.miny = batch->max_scissor.miny;
591 blit_scissor.maxx = MIN2(pfb->width, batch->max_scissor.maxx);
592 blit_scissor.maxy = MIN2(pfb->height, batch->max_scissor.maxy);
593
594 OUT_PKT4(ring, REG_A6XX_RB_BLIT_SCISSOR_TL, 2);
595 OUT_RING(ring,
596 A6XX_RB_BLIT_SCISSOR_TL_X(blit_scissor.minx) |
597 A6XX_RB_BLIT_SCISSOR_TL_Y(blit_scissor.miny));
598 OUT_RING(ring,
599 A6XX_RB_BLIT_SCISSOR_BR_X(blit_scissor.maxx - 1) |
600 A6XX_RB_BLIT_SCISSOR_BR_Y(blit_scissor.maxy - 1));
601 }
602
603 static void
604 emit_blit(struct fd_batch *batch, uint32_t base,
605 struct pipe_surface *psurf,
606 struct fd_resource *rsc)
607 {
608 struct fd_ringbuffer *ring = batch->gmem;
609 struct fd_resource_slice *slice;
610 uint32_t offset;
611
612 slice = fd_resource_slice(rsc, psurf->u.tex.level);
613 offset = fd_resource_offset(rsc, psurf->u.tex.level,
614 psurf->u.tex.first_layer);
615
616 debug_assert(psurf->u.tex.first_layer == psurf->u.tex.last_layer);
617
618 enum pipe_format pfmt = psurf->format;
619 enum a6xx_color_fmt format = fd6_pipe2color(pfmt);
620 uint32_t stride = slice->pitch * rsc->cpp;
621 uint32_t size = slice->size0;
622 enum a3xx_color_swap swap = fd6_pipe2swap(pfmt);
623
624 // TODO: tile mode
625 // bool tiled;
626 // tiled = rsc->tile_mode &&
627 // !fd_resource_level_linear(psurf->texture, psurf->u.tex.level);
628
629 OUT_PKT4(ring, REG_A6XX_RB_BLIT_DST_INFO, 5);
630 OUT_RING(ring,
631 A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR) |
632 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(format) |
633 A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(swap));
634 OUT_RELOCW(ring, rsc->bo, offset, 0, 0); /* RB_BLIT_DST_LO/HI */
635 OUT_RING(ring, A6XX_RB_BLIT_DST_PITCH(stride));
636 OUT_RING(ring, A6XX_RB_BLIT_DST_ARRAY_PITCH(size));
637
638 OUT_PKT4(ring, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
639 OUT_RING(ring, base);
640
641 fd6_emit_blit(batch, ring);
642 }
643
644 static void
645 emit_restore_blit(struct fd_batch *batch, uint32_t base,
646 struct pipe_surface *psurf,
647 struct fd_resource *rsc,
648 unsigned buffer)
649 {
650 struct fd_ringbuffer *ring = batch->gmem;
651 uint32_t info = 0;
652
653 switch (buffer) {
654 case FD_BUFFER_COLOR:
655 info |= A6XX_RB_BLIT_INFO_UNK0;
656 break;
657 case FD_BUFFER_STENCIL:
658 info |= A6XX_RB_BLIT_INFO_UNK0;
659 break;
660 case FD_BUFFER_DEPTH:
661 info |= A6XX_RB_BLIT_INFO_DEPTH | A6XX_RB_BLIT_INFO_UNK0;
662 break;
663 }
664
665 if (util_format_is_pure_integer(psurf->format))
666 info |= A6XX_RB_BLIT_INFO_INTEGER;
667
668 OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
669 OUT_RING(ring, info | A6XX_RB_BLIT_INFO_GMEM);
670
671 emit_blit(batch, base, psurf, rsc);
672 }
673
674 /*
675 * transfer from system memory to gmem
676 */
677 static void
678 fd6_emit_tile_mem2gmem(struct fd_batch *batch, struct fd_tile *tile)
679 {
680 struct fd_context *ctx = batch->ctx;
681 struct fd_gmem_stateobj *gmem = &ctx->gmem;
682 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
683
684 set_blit_scissor(batch);
685
686 if (fd_gmem_needs_restore(batch, tile, FD_BUFFER_COLOR)) {
687 unsigned i;
688 for (i = 0; i < pfb->nr_cbufs; i++) {
689 if (!pfb->cbufs[i])
690 continue;
691 if (!(batch->restore & (PIPE_CLEAR_COLOR0 << i)))
692 continue;
693 emit_restore_blit(batch, gmem->cbuf_base[i], pfb->cbufs[i],
694 fd_resource(pfb->cbufs[i]->texture),
695 FD_BUFFER_COLOR);
696 }
697 }
698
699 if (fd_gmem_needs_restore(batch, tile, FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
700 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
701
702 if (!rsc->stencil || fd_gmem_needs_restore(batch, tile, FD_BUFFER_DEPTH)) {
703 emit_restore_blit(batch, gmem->zsbuf_base[0], pfb->zsbuf, rsc,
704 FD_BUFFER_DEPTH);
705 }
706 if (rsc->stencil && fd_gmem_needs_restore(batch, tile, FD_BUFFER_STENCIL)) {
707 emit_restore_blit(batch, gmem->zsbuf_base[1], pfb->zsbuf, rsc->stencil,
708 FD_BUFFER_STENCIL);
709 }
710 }
711 }
712
713 /* before IB to rendering cmds: */
714 static void
715 fd6_emit_tile_renderprep(struct fd_batch *batch, struct fd_tile *tile)
716 {
717 }
718
719 static void
720 emit_resolve_blit(struct fd_batch *batch, uint32_t base,
721 struct pipe_surface *psurf,
722 struct fd_resource *rsc,
723 unsigned buffer)
724 {
725 struct fd_ringbuffer *ring = batch->gmem;
726 uint32_t info = 0;
727
728 if (!rsc->valid)
729 return;
730
731 switch (buffer) {
732 case FD_BUFFER_COLOR:
733 break;
734 case FD_BUFFER_STENCIL:
735 info |= A6XX_RB_BLIT_INFO_UNK0;
736 break;
737 case FD_BUFFER_DEPTH:
738 info |= A6XX_RB_BLIT_INFO_DEPTH;
739 break;
740 }
741
742 if (util_format_is_pure_integer(psurf->format))
743 info |= A6XX_RB_BLIT_INFO_INTEGER;
744
745 OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
746 OUT_RING(ring, info);
747
748 emit_blit(batch, base, psurf, rsc);
749 }
750
751 /*
752 * transfer from gmem to system memory (ie. normal RAM)
753 */
754
755 static void
756 fd6_emit_tile_gmem2mem(struct fd_batch *batch, struct fd_tile *tile)
757 {
758 struct fd_context *ctx = batch->ctx;
759 struct fd_gmem_stateobj *gmem = &ctx->gmem;
760 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
761 struct fd_ringbuffer *ring = batch->gmem;
762
763 if (use_hw_binning(batch)) {
764 OUT_PKT7(ring, CP_SET_MARKER, 1);
765 OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(0x5) | 0x10);
766 }
767
768 OUT_PKT7(ring, CP_SET_DRAW_STATE, 3);
769 OUT_RING(ring, CP_SET_DRAW_STATE__0_COUNT(0) |
770 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS |
771 CP_SET_DRAW_STATE__0_GROUP_ID(0));
772 OUT_RING(ring, CP_SET_DRAW_STATE__1_ADDR_LO(0));
773 OUT_RING(ring, CP_SET_DRAW_STATE__2_ADDR_HI(0));
774
775 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
776 OUT_RING(ring, 0x0);
777
778 emit_marker6(ring, 7);
779 OUT_PKT7(ring, CP_SET_MARKER, 1);
780 OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE) | 0x10);
781 emit_marker6(ring, 7);
782
783 set_blit_scissor(batch);
784
785 if (batch->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
786 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
787
788 if (!rsc->stencil || (batch->resolve & FD_BUFFER_DEPTH)) {
789 emit_resolve_blit(batch, gmem->zsbuf_base[0], pfb->zsbuf, rsc,
790 FD_BUFFER_DEPTH);
791 }
792 if (rsc->stencil && (batch->resolve & FD_BUFFER_STENCIL)) {
793 emit_resolve_blit(batch, gmem->zsbuf_base[1], pfb->zsbuf, rsc->stencil,
794 FD_BUFFER_STENCIL);
795 }
796 }
797
798 if (batch->resolve & FD_BUFFER_COLOR) {
799 unsigned i;
800 for (i = 0; i < pfb->nr_cbufs; i++) {
801 if (!pfb->cbufs[i])
802 continue;
803 if (!(batch->resolve & (PIPE_CLEAR_COLOR0 << i)))
804 continue;
805 emit_resolve_blit(batch, gmem->cbuf_base[i], pfb->cbufs[i],
806 fd_resource(pfb->cbufs[i]->texture),
807 FD_BUFFER_COLOR);
808 }
809 }
810 }
811
812 static void
813 fd6_emit_tile_fini(struct fd_batch *batch)
814 {
815 struct fd_ringbuffer *ring = batch->gmem;
816
817 OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_CNTL, 1);
818 OUT_RING(ring, A6XX_GRAS_LRZ_CNTL_ENABLE | A6XX_GRAS_LRZ_CNTL_UNK3);
819
820 fd6_emit_lrz_flush(ring);
821
822 fd6_event_write(batch, ring, CACHE_FLUSH_TS, true);
823 }
824
825 static void
826 fd6_emit_sysmem_prep(struct fd_batch *batch)
827 {
828 struct pipe_framebuffer_state *pfb = &batch->framebuffer;
829 struct fd_ringbuffer *ring = batch->gmem;
830
831 fd6_emit_restore(batch, ring);
832
833 fd6_emit_lrz_flush(ring);
834
835 emit_marker6(ring, 7);
836 OUT_PKT7(ring, CP_SET_MARKER, 1);
837 OUT_RING(ring, A2XX_CP_SET_MARKER_0_MODE(RM6_BYPASS) | 0x10); /* | 0x10 ? */
838 emit_marker6(ring, 7);
839
840 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
841 OUT_RING(ring, 0x0);
842
843 fd6_event_write(batch, ring, PC_CCU_INVALIDATE_COLOR, false);
844 fd6_cache_flush(batch, ring);
845
846 #if 0
847 OUT_PKT4(ring, REG_A6XX_PC_POWER_CNTL, 1);
848 OUT_RING(ring, 0x00000003); /* PC_POWER_CNTL */
849 #endif
850
851 #if 0
852 OUT_PKT4(ring, REG_A6XX_VFD_POWER_CNTL, 1);
853 OUT_RING(ring, 0x00000003); /* VFD_POWER_CNTL */
854 #endif
855
856 /* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */
857 fd_wfi(batch, ring);
858 OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
859 OUT_RING(ring, 0x10000000); /* RB_CCU_CNTL */
860
861 set_scissor(ring, 0, 0, pfb->width - 1, pfb->height - 1);
862
863 set_window_offset(ring, 0, 0);
864
865 set_bin_size(ring, 0, 0, 0xc00000); /* 0xc00000 = BYPASS? */
866
867 OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
868 OUT_RING(ring, 0x1);
869
870 patch_draws(batch, IGNORE_VISIBILITY);
871
872 emit_zs(ring, pfb->zsbuf, NULL);
873 emit_mrt(ring, pfb, NULL);
874
875 disable_msaa(ring);
876 }
877
878 static void
879 fd6_emit_sysmem_fini(struct fd_batch *batch)
880 {
881 struct fd_ringbuffer *ring = batch->gmem;
882
883 OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
884 OUT_RING(ring, 0x0);
885
886 fd6_emit_lrz_flush(ring);
887
888 fd6_event_write(batch, ring, UNK_1D, true);
889 }
890
891 void
892 fd6_gmem_init(struct pipe_context *pctx)
893 {
894 struct fd_context *ctx = fd_context(pctx);
895
896 ctx->emit_tile_init = fd6_emit_tile_init;
897 ctx->emit_tile_prep = fd6_emit_tile_prep;
898 ctx->emit_tile_mem2gmem = fd6_emit_tile_mem2gmem;
899 ctx->emit_tile_renderprep = fd6_emit_tile_renderprep;
900 ctx->emit_tile_gmem2mem = fd6_emit_tile_gmem2mem;
901 ctx->emit_tile_fini = fd6_emit_tile_fini;
902 ctx->emit_sysmem_prep = fd6_emit_sysmem_prep;
903 ctx->emit_sysmem_fini = fd6_emit_sysmem_fini;
904 }