src/gallium/drivers/freedreno/a6xx/fd6_image.c

   1 /*
   2  * Copyright (C) 2017 Rob Clark <robclark@freedesktop.org>
   3  * Copyright © 2018 Google, Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  22  * SOFTWARE.
  23  *
  24  * Authors:
  25  *    Rob Clark <robclark@freedesktop.org>
  26  */
  27
  28 #include "pipe/p_state.h"
  29
  30 #include "freedreno_resource.h"
  31 #include "fd6_image.h"
  32 #include "fd6_format.h"
  33 #include "fd6_texture.h"
  34
  35 static enum a6xx_state_block texsb[] = {
  36         [PIPE_SHADER_COMPUTE] = SB6_CS_TEX,
  37         [PIPE_SHADER_FRAGMENT] = SB6_FS_TEX,
  38 };
  39
  40 static enum a6xx_state_block imgsb[] = {
  41         [PIPE_SHADER_COMPUTE] = SB6_CS_SSBO,
  42         [PIPE_SHADER_FRAGMENT] = SB6_SSBO,
  43 };
  44
  45 struct fd6_image {
  46         struct pipe_resource *prsc;
  47         enum pipe_format pfmt;
  48         enum a6xx_tex_fmt fmt;
  49         enum a6xx_tex_fetchsize fetchsize;
  50         enum a6xx_tex_type type;
  51         bool srgb;
  52         uint32_t cpp;
  53         uint32_t width;
  54         uint32_t height;
  55         uint32_t depth;
  56         uint32_t pitch;
  57         uint32_t array_pitch;
  58         struct fd_bo *bo;
  59         uint32_t offset;
  60 };
  61
  62 static void translate_image(struct fd6_image *img, struct pipe_image_view *pimg)
  63 {
  64         enum pipe_format format = pimg->format;
  65         struct pipe_resource *prsc = pimg->resource;
  66         struct fd_resource *rsc = fd_resource(prsc);
  67         unsigned lvl;
  68
  69         if (!pimg->resource) {
  70                 memset(img, 0, sizeof(*img));
  71                 return;
  72         }
  73
  74         img->prsc      = prsc;
  75         img->pfmt      = format;
  76         img->fmt       = fd6_pipe2tex(format);
  77         img->fetchsize = fd6_pipe2fetchsize(format);
  78         img->type      = fd6_tex_type(prsc->target);
  79         img->srgb      = util_format_is_srgb(format);
  80         img->cpp       = rsc->cpp;
  81         img->bo        = rsc->bo;
  82
  83         if (prsc->target == PIPE_BUFFER) {
  84                 lvl = 0;
  85                 img->offset = pimg->u.buf.offset;
  86                 img->pitch  = pimg->u.buf.size;
  87                 img->array_pitch = 0;
  88         } else {
  89                 lvl = pimg->u.tex.level;
  90                 img->offset = rsc->slices[lvl].offset;
  91                 img->pitch  = rsc->slices[lvl].pitch * rsc->cpp;
  92                 img->array_pitch = rsc->layer_size;
  93         }
  94
  95         img->width     = u_minify(prsc->width0, lvl);
  96         img->height    = u_minify(prsc->height0, lvl);
  97         img->depth     = u_minify(prsc->depth0, lvl);
  98 }
  99
 100 static void emit_image_tex(struct fd_ringbuffer *ring, unsigned slot,
 101                 struct fd6_image *img, enum pipe_shader_type shader)
 102 {
 103         unsigned opcode = CP_LOAD_STATE6_FRAG;
 104
 105         assert(shader == PIPE_SHADER_COMPUTE || shader == PIPE_SHADER_FRAGMENT);
 106
 107         OUT_PKT7(ring, opcode, 3 + 12);
 108         OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(slot) |
 109                 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
 110                 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
 111                 CP_LOAD_STATE6_0_STATE_BLOCK(texsb[shader]) |
 112                 CP_LOAD_STATE6_0_NUM_UNIT(1));
 113         OUT_RING(ring, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
 114         OUT_RING(ring, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
 115
 116         OUT_RING(ring, A6XX_TEX_CONST_0_FMT(img->fmt) |
 117                 fd6_tex_swiz(img->prsc, img->fmt, PIPE_SWIZZLE_X, PIPE_SWIZZLE_Y,
 118                         PIPE_SWIZZLE_Z, PIPE_SWIZZLE_W) |
 119                 COND(img->srgb, A6XX_TEX_CONST_0_SRGB));
 120         OUT_RING(ring, A6XX_TEX_CONST_1_WIDTH(img->width) |
 121                 A6XX_TEX_CONST_1_HEIGHT(img->height));
 122         OUT_RING(ring, A6XX_TEX_CONST_2_FETCHSIZE(img->fetchsize) |
 123                 A6XX_TEX_CONST_2_TYPE(img->type) |
 124                 A6XX_TEX_CONST_2_PITCH(img->pitch));
 125         OUT_RING(ring, A6XX_TEX_CONST_3_ARRAY_PITCH(img->array_pitch));
 126         if (img->bo) {
 127                 OUT_RELOC(ring, img->bo, img->offset,
 128                                 (uint64_t)A6XX_TEX_CONST_5_DEPTH(img->depth) << 32, 0);
 129         } else {
 130                 OUT_RING(ring, 0x00000000);
 131                 OUT_RING(ring, A6XX_TEX_CONST_5_DEPTH(img->depth));
 132         }
 133         OUT_RING(ring, 0x00000000);
 134         OUT_RING(ring, 0x00000000);
 135         OUT_RING(ring, 0x00000000);
 136         OUT_RING(ring, 0x00000000);
 137         OUT_RING(ring, 0x00000000);
 138         OUT_RING(ring, 0x00000000);
 139 }
 140
 141 static void emit_image_ssbo(struct fd_ringbuffer *ring, unsigned slot,
 142                 struct fd6_image *img, enum pipe_shader_type shader)
 143 {
 144         unsigned opcode = CP_LOAD_STATE6_FRAG;
 145
 146         assert(shader == PIPE_SHADER_COMPUTE || shader == PIPE_SHADER_FRAGMENT);
 147
 148 #if 0
 149         OUT_PKT7(ring, opcode, 3 + 4);
 150         OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(slot) |
 151                 CP_LOAD_STATE6_0_STATE_TYPE(0) |
 152                 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
 153                 CP_LOAD_STATE6_0_STATE_BLOCK(imgsb[shader]) |
 154                 CP_LOAD_STATE6_0_NUM_UNIT(1));
 155         OUT_RING(ring, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
 156         OUT_RING(ring, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
 157         OUT_RING(ring, A6XX_SSBO_0_0_BASE_LO(0));
 158         OUT_RING(ring, A6XX_SSBO_0_1_PITCH(img->pitch));
 159         OUT_RING(ring, A6XX_SSBO_0_2_ARRAY_PITCH(img->array_pitch));
 160         OUT_RING(ring, A6XX_SSBO_0_3_CPP(img->cpp));
 161 #endif
 162
 163 #if 0
 164         OUT_PKT7(ring, opcode, 3 + 2);
 165         OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(slot) |
 166                 CP_LOAD_STATE6_0_STATE_TYPE(1) |
 167                 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
 168                 CP_LOAD_STATE6_0_STATE_BLOCK(imgsb[shader]) |
 169                 CP_LOAD_STATE6_0_NUM_UNIT(1));
 170         OUT_RING(ring, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
 171         OUT_RING(ring, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
 172         OUT_RING(ring, A6XX_SSBO_1_0_FMT(img->fmt) |
 173                 A6XX_SSBO_1_0_WIDTH(img->width));
 174         OUT_RING(ring, A6XX_SSBO_1_1_HEIGHT(img->height) |
 175                 A6XX_SSBO_1_1_DEPTH(img->depth));
 176 #endif
 177
 178         OUT_PKT7(ring, opcode, 3 + 2);
 179         OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(slot) |
 180                 CP_LOAD_STATE6_0_STATE_TYPE(2) |
 181                 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
 182                 CP_LOAD_STATE6_0_STATE_BLOCK(imgsb[shader]) |
 183                 CP_LOAD_STATE6_0_NUM_UNIT(1));
 184         OUT_RING(ring, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
 185         OUT_RING(ring, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
 186         if (img->bo) {
 187                 OUT_RELOCW(ring, img->bo, img->offset, 0, 0);
 188         } else {
 189                 OUT_RING(ring, 0x00000000);
 190                 OUT_RING(ring, 0x00000000);
 191         }
 192 }
 193
 194 /* Note that to avoid conflicts with textures and non-image "SSBO"s, images
 195  * are placedd, in reverse order, at the end of the state block, so for
 196  * example the sampler state:
 197  *
 198  *   0:   first texture
 199  *   1:   second texture
 200  *   ....
 201  *   N-1: second image
 202  *   N:   first image
 203  */
 204 static unsigned
 205 get_image_slot(unsigned index)
 206 {
 207         /* TODO figure out real limit per generation, and don't hardcode.
 208          * This needs to match get_image_slot() in ir3_compiler_nir.
 209          * Possibly should be factored out into shared helper?
 210          */
 211         const unsigned max_samplers = 16;
 212         return max_samplers - index - 1;
 213 }
 214
 215 /* Emit required "SSBO" and sampler state.  The sampler state is used by the
 216  * hw for imageLoad(), and "SSBO" state for imageStore().  Returns max sampler
 217  * used.
 218  */
 219 void
 220 fd6_emit_images(struct fd_context *ctx, struct fd_ringbuffer *ring,
 221                 enum pipe_shader_type shader)
 222 {
 223         struct fd_shaderimg_stateobj *so = &ctx->shaderimg[shader];
 224         unsigned enabled_mask = so->enabled_mask;
 225
 226         while (enabled_mask) {
 227                 unsigned index = u_bit_scan(&enabled_mask);
 228                 unsigned slot = get_image_slot(index);
 229                 struct fd6_image img;
 230
 231                 translate_image(&img, &so->si[index]);
 232
 233                 emit_image_tex(ring, slot, &img, shader);
 234                 emit_image_ssbo(ring, slot, &img, shader);
 235         }
 236 }