src/gallium/drivers/freedreno/a6xx/fd6_perfcntr.c

   1 /*
   2  * Copyright (C) 2019 Rob Clark <robclark@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Rob Clark <robclark@freedesktop.org>
  25  */
  26
  27 #ifndef FD6_PERFCNTR_H_
  28 #define FD6_PERFCNTR_H_
  29
  30 #include "freedreno_perfcntr.h"
  31 #include "fd6_format.h"
  32
  33 #define REG(_x) REG_A6XX_ ## _x
  34
  35 #define COUNTER(_sel, _lo, _hi) {  \
  36         .select_reg = REG(_sel),       \
  37         .counter_reg_lo = REG(_lo),    \
  38         .counter_reg_hi = REG(_hi),    \
  39 }
  40
  41 #define COUNTER2(_sel, _lo, _hi, _en, _clr) { \
  42         .select_reg     = REG(_sel),  \
  43         .counter_reg_lo = REG(_lo),   \
  44         .counter_reg_hi = REG(_hi),   \
  45         .enable         = REG(_en),   \
  46         .clear          = REG(_clr),  \
  47 }
  48
  49 #define COUNTABLE(_selector, _query_type, _result_type) {            \
  50         .name        = #_selector,                                       \
  51         .selector    = _selector,                                        \
  52         .query_type  = PIPE_DRIVER_QUERY_TYPE_ ## _query_type,           \
  53         .result_type = PIPE_DRIVER_QUERY_RESULT_TYPE_ ## _result_type,   \
  54 }
  55
  56 #define GROUP(_name, _counters, _countables) {   \
  57         .name           = _name,                     \
  58         .num_counters   = ARRAY_SIZE(_counters),     \
  59         .counters       = _counters,                 \
  60         .num_countables = ARRAY_SIZE(_countables),   \
  61         .countables     = _countables,               \
  62 }
  63
  64 static const struct fd_perfcntr_counter cp_counters[] = {
  65 //RESERVED: for kernel
  66 //      COUNTER(CP_PERFCTR_CP_SEL_0,  RBBM_PERFCTR_CP_0_LO,  RBBM_PERFCTR_CP_0_HI),
  67         COUNTER(CP_PERFCTR_CP_SEL_1,  RBBM_PERFCTR_CP_1_LO,  RBBM_PERFCTR_CP_1_HI),
  68         COUNTER(CP_PERFCTR_CP_SEL_2,  RBBM_PERFCTR_CP_2_LO,  RBBM_PERFCTR_CP_2_HI),
  69         COUNTER(CP_PERFCTR_CP_SEL_3,  RBBM_PERFCTR_CP_3_LO,  RBBM_PERFCTR_CP_3_HI),
  70         COUNTER(CP_PERFCTR_CP_SEL_4,  RBBM_PERFCTR_CP_4_LO,  RBBM_PERFCTR_CP_4_HI),
  71         COUNTER(CP_PERFCTR_CP_SEL_5,  RBBM_PERFCTR_CP_5_LO,  RBBM_PERFCTR_CP_5_HI),
  72         COUNTER(CP_PERFCTR_CP_SEL_6,  RBBM_PERFCTR_CP_6_LO,  RBBM_PERFCTR_CP_6_HI),
  73         COUNTER(CP_PERFCTR_CP_SEL_7,  RBBM_PERFCTR_CP_7_LO,  RBBM_PERFCTR_CP_7_HI),
  74         COUNTER(CP_PERFCTR_CP_SEL_8,  RBBM_PERFCTR_CP_8_LO,  RBBM_PERFCTR_CP_8_HI),
  75         COUNTER(CP_PERFCTR_CP_SEL_9,  RBBM_PERFCTR_CP_9_LO,  RBBM_PERFCTR_CP_9_HI),
  76         COUNTER(CP_PERFCTR_CP_SEL_10, RBBM_PERFCTR_CP_10_LO, RBBM_PERFCTR_CP_10_HI),
  77         COUNTER(CP_PERFCTR_CP_SEL_11, RBBM_PERFCTR_CP_11_LO, RBBM_PERFCTR_CP_11_HI),
  78         COUNTER(CP_PERFCTR_CP_SEL_12, RBBM_PERFCTR_CP_12_LO, RBBM_PERFCTR_CP_12_HI),
  79         COUNTER(CP_PERFCTR_CP_SEL_13, RBBM_PERFCTR_CP_13_LO, RBBM_PERFCTR_CP_13_HI),
  80 };
  81
  82 static const struct fd_perfcntr_countable cp_countables[] = {
  83         COUNTABLE(PERF_CP_ALWAYS_COUNT, UINT64, AVERAGE),
  84         COUNTABLE(PERF_CP_BUSY_GFX_CORE_IDLE, UINT64, AVERAGE),
  85         COUNTABLE(PERF_CP_BUSY_CYCLES, UINT64, AVERAGE),
  86         COUNTABLE(PERF_CP_NUM_PREEMPTIONS, UINT64, AVERAGE),
  87         COUNTABLE(PERF_CP_PREEMPTION_REACTION_DELAY, UINT64, AVERAGE),
  88         COUNTABLE(PERF_CP_PREEMPTION_SWITCH_OUT_TIME, UINT64, AVERAGE),
  89         COUNTABLE(PERF_CP_PREEMPTION_SWITCH_IN_TIME, UINT64, AVERAGE),
  90         COUNTABLE(PERF_CP_DEAD_DRAWS_IN_BIN_RENDER, UINT64, AVERAGE),
  91         COUNTABLE(PERF_CP_PREDICATED_DRAWS_KILLED, UINT64, AVERAGE),
  92         COUNTABLE(PERF_CP_MODE_SWITCH, UINT64, AVERAGE),
  93         COUNTABLE(PERF_CP_ZPASS_DONE, UINT64, AVERAGE),
  94         COUNTABLE(PERF_CP_CONTEXT_DONE, UINT64, AVERAGE),
  95         COUNTABLE(PERF_CP_CACHE_FLUSH, UINT64, AVERAGE),
  96         COUNTABLE(PERF_CP_LONG_PREEMPTIONS, UINT64, AVERAGE),
  97         COUNTABLE(PERF_CP_SQE_I_CACHE_STARVE, UINT64, AVERAGE),
  98         COUNTABLE(PERF_CP_SQE_IDLE, UINT64, AVERAGE),
  99         COUNTABLE(PERF_CP_SQE_PM4_STARVE_RB_IB, UINT64, AVERAGE),
 100         COUNTABLE(PERF_CP_SQE_PM4_STARVE_SDS, UINT64, AVERAGE),
 101         COUNTABLE(PERF_CP_SQE_MRB_STARVE, UINT64, AVERAGE),
 102         COUNTABLE(PERF_CP_SQE_RRB_STARVE, UINT64, AVERAGE),
 103         COUNTABLE(PERF_CP_SQE_VSD_STARVE, UINT64, AVERAGE),
 104         COUNTABLE(PERF_CP_VSD_DECODE_STARVE, UINT64, AVERAGE),
 105         COUNTABLE(PERF_CP_SQE_PIPE_OUT_STALL, UINT64, AVERAGE),
 106         COUNTABLE(PERF_CP_SQE_SYNC_STALL, UINT64, AVERAGE),
 107         COUNTABLE(PERF_CP_SQE_PM4_WFI_STALL, UINT64, AVERAGE),
 108         COUNTABLE(PERF_CP_SQE_SYS_WFI_STALL, UINT64, AVERAGE),
 109         COUNTABLE(PERF_CP_SQE_T4_EXEC, UINT64, AVERAGE),
 110         COUNTABLE(PERF_CP_SQE_LOAD_STATE_EXEC, UINT64, AVERAGE),
 111         COUNTABLE(PERF_CP_SQE_SAVE_SDS_STATE, UINT64, AVERAGE),
 112         COUNTABLE(PERF_CP_SQE_DRAW_EXEC, UINT64, AVERAGE),
 113         COUNTABLE(PERF_CP_SQE_CTXT_REG_BUNCH_EXEC, UINT64, AVERAGE),
 114         COUNTABLE(PERF_CP_SQE_EXEC_PROFILED, UINT64, AVERAGE),
 115         COUNTABLE(PERF_CP_MEMORY_POOL_EMPTY, UINT64, AVERAGE),
 116         COUNTABLE(PERF_CP_MEMORY_POOL_SYNC_STALL, UINT64, AVERAGE),
 117         COUNTABLE(PERF_CP_MEMORY_POOL_ABOVE_THRESH, UINT64, AVERAGE),
 118         COUNTABLE(PERF_CP_AHB_WR_STALL_PRE_DRAWS, UINT64, AVERAGE),
 119         COUNTABLE(PERF_CP_AHB_STALL_SQE_GMU, UINT64, AVERAGE),
 120         COUNTABLE(PERF_CP_AHB_STALL_SQE_WR_OTHER, UINT64, AVERAGE),
 121         COUNTABLE(PERF_CP_AHB_STALL_SQE_RD_OTHER, UINT64, AVERAGE),
 122         COUNTABLE(PERF_CP_CLUSTER0_EMPTY, UINT64, AVERAGE),
 123         COUNTABLE(PERF_CP_CLUSTER1_EMPTY, UINT64, AVERAGE),
 124         COUNTABLE(PERF_CP_CLUSTER2_EMPTY, UINT64, AVERAGE),
 125         COUNTABLE(PERF_CP_CLUSTER3_EMPTY, UINT64, AVERAGE),
 126         COUNTABLE(PERF_CP_CLUSTER4_EMPTY, UINT64, AVERAGE),
 127         COUNTABLE(PERF_CP_CLUSTER5_EMPTY, UINT64, AVERAGE),
 128         COUNTABLE(PERF_CP_PM4_DATA, UINT64, AVERAGE),
 129         COUNTABLE(PERF_CP_PM4_HEADERS, UINT64, AVERAGE),
 130         COUNTABLE(PERF_CP_VBIF_READ_BEATS, UINT64, AVERAGE),
 131         COUNTABLE(PERF_CP_VBIF_WRITE_BEATS, UINT64, AVERAGE),
 132         COUNTABLE(PERF_CP_SQE_INSTR_COUNTER, UINT64, AVERAGE),
 133 };
 134
 135 static const struct fd_perfcntr_counter ccu_counters[] = {
 136         COUNTER(RB_PERFCTR_CCU_SEL_0, RBBM_PERFCTR_CCU_0_LO, RBBM_PERFCTR_CCU_0_HI),
 137         COUNTER(RB_PERFCTR_CCU_SEL_1, RBBM_PERFCTR_CCU_1_LO, RBBM_PERFCTR_CCU_1_HI),
 138         COUNTER(RB_PERFCTR_CCU_SEL_2, RBBM_PERFCTR_CCU_2_LO, RBBM_PERFCTR_CCU_2_HI),
 139         COUNTER(RB_PERFCTR_CCU_SEL_3, RBBM_PERFCTR_CCU_3_LO, RBBM_PERFCTR_CCU_3_HI),
 140         COUNTER(RB_PERFCTR_CCU_SEL_4, RBBM_PERFCTR_CCU_4_LO, RBBM_PERFCTR_CCU_4_HI),
 141 };
 142
 143 static const struct fd_perfcntr_countable ccu_countables[] = {
 144         COUNTABLE(PERF_CCU_BUSY_CYCLES, UINT64, AVERAGE),
 145         COUNTABLE(PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN, UINT64, AVERAGE),
 146         COUNTABLE(PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN, UINT64, AVERAGE),
 147         COUNTABLE(PERF_CCU_STARVE_CYCLES_FLAG_RETURN, UINT64, AVERAGE),
 148         COUNTABLE(PERF_CCU_DEPTH_BLOCKS, UINT64, AVERAGE),
 149         COUNTABLE(PERF_CCU_COLOR_BLOCKS, UINT64, AVERAGE),
 150         COUNTABLE(PERF_CCU_DEPTH_BLOCK_HIT, UINT64, AVERAGE),
 151         COUNTABLE(PERF_CCU_COLOR_BLOCK_HIT, UINT64, AVERAGE),
 152         COUNTABLE(PERF_CCU_PARTIAL_BLOCK_READ, UINT64, AVERAGE),
 153         COUNTABLE(PERF_CCU_GMEM_READ, UINT64, AVERAGE),
 154         COUNTABLE(PERF_CCU_GMEM_WRITE, UINT64, AVERAGE),
 155         COUNTABLE(PERF_CCU_DEPTH_READ_FLAG0_COUNT, UINT64, AVERAGE),
 156         COUNTABLE(PERF_CCU_DEPTH_READ_FLAG1_COUNT, UINT64, AVERAGE),
 157         COUNTABLE(PERF_CCU_DEPTH_READ_FLAG2_COUNT, UINT64, AVERAGE),
 158         COUNTABLE(PERF_CCU_DEPTH_READ_FLAG3_COUNT, UINT64, AVERAGE),
 159         COUNTABLE(PERF_CCU_DEPTH_READ_FLAG4_COUNT, UINT64, AVERAGE),
 160         COUNTABLE(PERF_CCU_DEPTH_READ_FLAG5_COUNT, UINT64, AVERAGE),
 161         COUNTABLE(PERF_CCU_DEPTH_READ_FLAG6_COUNT, UINT64, AVERAGE),
 162         COUNTABLE(PERF_CCU_DEPTH_READ_FLAG8_COUNT, UINT64, AVERAGE),
 163         COUNTABLE(PERF_CCU_COLOR_READ_FLAG0_COUNT, UINT64, AVERAGE),
 164         COUNTABLE(PERF_CCU_COLOR_READ_FLAG1_COUNT, UINT64, AVERAGE),
 165         COUNTABLE(PERF_CCU_COLOR_READ_FLAG2_COUNT, UINT64, AVERAGE),
 166         COUNTABLE(PERF_CCU_COLOR_READ_FLAG3_COUNT, UINT64, AVERAGE),
 167         COUNTABLE(PERF_CCU_COLOR_READ_FLAG4_COUNT, UINT64, AVERAGE),
 168         COUNTABLE(PERF_CCU_COLOR_READ_FLAG5_COUNT, UINT64, AVERAGE),
 169         COUNTABLE(PERF_CCU_COLOR_READ_FLAG6_COUNT, UINT64, AVERAGE),
 170         COUNTABLE(PERF_CCU_COLOR_READ_FLAG8_COUNT, UINT64, AVERAGE),
 171         COUNTABLE(PERF_CCU_2D_RD_REQ, UINT64, AVERAGE),
 172         COUNTABLE(PERF_CCU_2D_WR_REQ, UINT64, AVERAGE),
 173 };
 174
 175 static const struct fd_perfcntr_counter tse_counters[] = {
 176         COUNTER(GRAS_PERFCTR_TSE_SEL_0, RBBM_PERFCTR_TSE_0_LO, RBBM_PERFCTR_TSE_0_HI),
 177         COUNTER(GRAS_PERFCTR_TSE_SEL_1, RBBM_PERFCTR_TSE_1_LO, RBBM_PERFCTR_TSE_1_HI),
 178         COUNTER(GRAS_PERFCTR_TSE_SEL_2, RBBM_PERFCTR_TSE_2_LO, RBBM_PERFCTR_TSE_2_HI),
 179         COUNTER(GRAS_PERFCTR_TSE_SEL_3, RBBM_PERFCTR_TSE_3_LO, RBBM_PERFCTR_TSE_3_HI),
 180 };
 181
 182 static const struct fd_perfcntr_countable tse_countables[] = {
 183         COUNTABLE(PERF_TSE_BUSY_CYCLES, UINT64, AVERAGE),
 184         COUNTABLE(PERF_TSE_CLIPPING_CYCLES, UINT64, AVERAGE),
 185         COUNTABLE(PERF_TSE_STALL_CYCLES_RAS, UINT64, AVERAGE),
 186         COUNTABLE(PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE, UINT64, AVERAGE),
 187         COUNTABLE(PERF_TSE_STALL_CYCLES_LRZ_ZPLANE, UINT64, AVERAGE),
 188         COUNTABLE(PERF_TSE_STARVE_CYCLES_PC, UINT64, AVERAGE),
 189         COUNTABLE(PERF_TSE_INPUT_PRIM, UINT64, AVERAGE),
 190         COUNTABLE(PERF_TSE_INPUT_NULL_PRIM, UINT64, AVERAGE),
 191         COUNTABLE(PERF_TSE_TRIVAL_REJ_PRIM, UINT64, AVERAGE),
 192         COUNTABLE(PERF_TSE_CLIPPED_PRIM, UINT64, AVERAGE),
 193         COUNTABLE(PERF_TSE_ZERO_AREA_PRIM, UINT64, AVERAGE),
 194         COUNTABLE(PERF_TSE_FACENESS_CULLED_PRIM, UINT64, AVERAGE),
 195         COUNTABLE(PERF_TSE_ZERO_PIXEL_PRIM, UINT64, AVERAGE),
 196         COUNTABLE(PERF_TSE_OUTPUT_NULL_PRIM, UINT64, AVERAGE),
 197         COUNTABLE(PERF_TSE_OUTPUT_VISIBLE_PRIM, UINT64, AVERAGE),
 198         COUNTABLE(PERF_TSE_CINVOCATION, UINT64, AVERAGE),
 199         COUNTABLE(PERF_TSE_CPRIMITIVES, UINT64, AVERAGE),
 200         COUNTABLE(PERF_TSE_2D_INPUT_PRIM, UINT64, AVERAGE),
 201         COUNTABLE(PERF_TSE_2D_ALIVE_CYCLES, UINT64, AVERAGE),
 202         COUNTABLE(PERF_TSE_CLIP_PLANES, UINT64, AVERAGE),
 203 };
 204
 205 static const struct fd_perfcntr_counter ras_counters[] = {
 206         COUNTER(GRAS_PERFCTR_RAS_SEL_0, RBBM_PERFCTR_RAS_0_LO, RBBM_PERFCTR_RAS_0_HI),
 207         COUNTER(GRAS_PERFCTR_RAS_SEL_1, RBBM_PERFCTR_RAS_1_LO, RBBM_PERFCTR_RAS_1_HI),
 208         COUNTER(GRAS_PERFCTR_RAS_SEL_2, RBBM_PERFCTR_RAS_2_LO, RBBM_PERFCTR_RAS_2_HI),
 209         COUNTER(GRAS_PERFCTR_RAS_SEL_3, RBBM_PERFCTR_RAS_3_LO, RBBM_PERFCTR_RAS_3_HI),
 210 };
 211
 212 static const struct fd_perfcntr_countable ras_countables[] = {
 213         COUNTABLE(PERF_RAS_BUSY_CYCLES, UINT64, AVERAGE),
 214         COUNTABLE(PERF_RAS_SUPERTILE_ACTIVE_CYCLES, UINT64, AVERAGE),
 215         COUNTABLE(PERF_RAS_STALL_CYCLES_LRZ, UINT64, AVERAGE),
 216         COUNTABLE(PERF_RAS_STARVE_CYCLES_TSE, UINT64, AVERAGE),
 217         COUNTABLE(PERF_RAS_SUPER_TILES, UINT64, AVERAGE),
 218         COUNTABLE(PERF_RAS_8X4_TILES, UINT64, AVERAGE),
 219         COUNTABLE(PERF_RAS_MASKGEN_ACTIVE, UINT64, AVERAGE),
 220         COUNTABLE(PERF_RAS_FULLY_COVERED_SUPER_TILES, UINT64, AVERAGE),
 221         COUNTABLE(PERF_RAS_FULLY_COVERED_8X4_TILES, UINT64, AVERAGE),
 222         COUNTABLE(PERF_RAS_PRIM_KILLED_INVISILBE, UINT64, AVERAGE),
 223         COUNTABLE(PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES, UINT64, AVERAGE),
 224         COUNTABLE(PERF_RAS_LRZ_INTF_WORKING_CYCLES, UINT64, AVERAGE),
 225         COUNTABLE(PERF_RAS_BLOCKS, UINT64, AVERAGE),
 226 };
 227
 228 static const struct fd_perfcntr_counter lrz_counters[] = {
 229         COUNTER(GRAS_PERFCTR_LRZ_SEL_0, RBBM_PERFCTR_LRZ_0_LO, RBBM_PERFCTR_LRZ_0_HI),
 230         COUNTER(GRAS_PERFCTR_LRZ_SEL_1, RBBM_PERFCTR_LRZ_1_LO, RBBM_PERFCTR_LRZ_1_HI),
 231         COUNTER(GRAS_PERFCTR_LRZ_SEL_2, RBBM_PERFCTR_LRZ_2_LO, RBBM_PERFCTR_LRZ_2_HI),
 232         COUNTER(GRAS_PERFCTR_LRZ_SEL_3, RBBM_PERFCTR_LRZ_3_LO, RBBM_PERFCTR_LRZ_3_HI),
 233 };
 234
 235 static const struct fd_perfcntr_countable lrz_countables[] = {
 236         COUNTABLE(PERF_LRZ_BUSY_CYCLES, UINT64, AVERAGE),
 237         COUNTABLE(PERF_LRZ_STARVE_CYCLES_RAS, UINT64, AVERAGE),
 238         COUNTABLE(PERF_LRZ_STALL_CYCLES_RB, UINT64, AVERAGE),
 239         COUNTABLE(PERF_LRZ_STALL_CYCLES_VSC, UINT64, AVERAGE),
 240         COUNTABLE(PERF_LRZ_STALL_CYCLES_VPC, UINT64, AVERAGE),
 241         COUNTABLE(PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH, UINT64, AVERAGE),
 242         COUNTABLE(PERF_LRZ_STALL_CYCLES_UCHE, UINT64, AVERAGE),
 243         COUNTABLE(PERF_LRZ_LRZ_READ, UINT64, AVERAGE),
 244         COUNTABLE(PERF_LRZ_LRZ_WRITE, UINT64, AVERAGE),
 245         COUNTABLE(PERF_LRZ_READ_LATENCY, UINT64, AVERAGE),
 246         COUNTABLE(PERF_LRZ_MERGE_CACHE_UPDATING, UINT64, AVERAGE),
 247         COUNTABLE(PERF_LRZ_PRIM_KILLED_BY_MASKGEN, UINT64, AVERAGE),
 248         COUNTABLE(PERF_LRZ_PRIM_KILLED_BY_LRZ, UINT64, AVERAGE),
 249         COUNTABLE(PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ, UINT64, AVERAGE),
 250         COUNTABLE(PERF_LRZ_FULL_8X8_TILES, UINT64, AVERAGE),
 251         COUNTABLE(PERF_LRZ_PARTIAL_8X8_TILES, UINT64, AVERAGE),
 252         COUNTABLE(PERF_LRZ_TILE_KILLED, UINT64, AVERAGE),
 253         COUNTABLE(PERF_LRZ_TOTAL_PIXEL, UINT64, AVERAGE),
 254         COUNTABLE(PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ, UINT64, AVERAGE),
 255         COUNTABLE(PERF_LRZ_FULLY_COVERED_TILES, UINT64, AVERAGE),
 256         COUNTABLE(PERF_LRZ_PARTIAL_COVERED_TILES, UINT64, AVERAGE),
 257         COUNTABLE(PERF_LRZ_FEEDBACK_ACCEPT, UINT64, AVERAGE),
 258         COUNTABLE(PERF_LRZ_FEEDBACK_DISCARD, UINT64, AVERAGE),
 259         COUNTABLE(PERF_LRZ_FEEDBACK_STALL, UINT64, AVERAGE),
 260         COUNTABLE(PERF_LRZ_STALL_CYCLES_RB_ZPLANE, UINT64, AVERAGE),
 261         COUNTABLE(PERF_LRZ_STALL_CYCLES_RB_BPLANE, UINT64, AVERAGE),
 262         COUNTABLE(PERF_LRZ_STALL_CYCLES_VC, UINT64, AVERAGE),
 263         COUNTABLE(PERF_LRZ_RAS_MASK_TRANS, UINT64, AVERAGE),
 264 };
 265
 266 static const struct fd_perfcntr_counter hlsq_counters[] = {
 267         COUNTER(HLSQ_PERFCTR_HLSQ_SEL_0, RBBM_PERFCTR_HLSQ_0_LO, RBBM_PERFCTR_HLSQ_0_HI),
 268         COUNTER(HLSQ_PERFCTR_HLSQ_SEL_1, RBBM_PERFCTR_HLSQ_1_LO, RBBM_PERFCTR_HLSQ_1_HI),
 269         COUNTER(HLSQ_PERFCTR_HLSQ_SEL_2, RBBM_PERFCTR_HLSQ_2_LO, RBBM_PERFCTR_HLSQ_2_HI),
 270         COUNTER(HLSQ_PERFCTR_HLSQ_SEL_3, RBBM_PERFCTR_HLSQ_3_LO, RBBM_PERFCTR_HLSQ_3_HI),
 271         COUNTER(HLSQ_PERFCTR_HLSQ_SEL_4, RBBM_PERFCTR_HLSQ_4_LO, RBBM_PERFCTR_HLSQ_4_HI),
 272         COUNTER(HLSQ_PERFCTR_HLSQ_SEL_5, RBBM_PERFCTR_HLSQ_5_LO, RBBM_PERFCTR_HLSQ_5_HI),
 273 // TODO did we loose some HLSQ counters or are they just missing from xml
 274 //      COUNTER(HLSQ_PERFCTR_HLSQ_SEL_6, RBBM_PERFCTR_HLSQ_6_LO, RBBM_PERFCTR_HLSQ_6_HI),
 275 //      COUNTER(HLSQ_PERFCTR_HLSQ_SEL_7, RBBM_PERFCTR_HLSQ_7_LO, RBBM_PERFCTR_HLSQ_7_HI),
 276 };
 277
 278 static const struct fd_perfcntr_countable hlsq_countables[] = {
 279         COUNTABLE(PERF_HLSQ_BUSY_CYCLES, UINT64, AVERAGE),
 280         COUNTABLE(PERF_HLSQ_STALL_CYCLES_UCHE, UINT64, AVERAGE),
 281         COUNTABLE(PERF_HLSQ_STALL_CYCLES_SP_STATE, UINT64, AVERAGE),
 282         COUNTABLE(PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE, UINT64, AVERAGE),
 283         COUNTABLE(PERF_HLSQ_UCHE_LATENCY_CYCLES, UINT64, AVERAGE),
 284         COUNTABLE(PERF_HLSQ_UCHE_LATENCY_COUNT, UINT64, AVERAGE),
 285         COUNTABLE(PERF_HLSQ_FS_STAGE_1X_WAVES, UINT64, AVERAGE),
 286         COUNTABLE(PERF_HLSQ_FS_STAGE_2X_WAVES, UINT64, AVERAGE),
 287         COUNTABLE(PERF_HLSQ_QUADS, UINT64, AVERAGE),
 288         COUNTABLE(PERF_HLSQ_CS_INVOCATIONS, UINT64, AVERAGE),
 289         COUNTABLE(PERF_HLSQ_COMPUTE_DRAWCALLS, UINT64, AVERAGE),
 290         COUNTABLE(PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING, UINT64, AVERAGE),
 291         COUNTABLE(PERF_HLSQ_DUAL_FS_PROG_ACTIVE, UINT64, AVERAGE),
 292         COUNTABLE(PERF_HLSQ_DUAL_VS_PROG_ACTIVE, UINT64, AVERAGE),
 293         COUNTABLE(PERF_HLSQ_FS_BATCH_COUNT_ZERO, UINT64, AVERAGE),
 294         COUNTABLE(PERF_HLSQ_VS_BATCH_COUNT_ZERO, UINT64, AVERAGE),
 295         COUNTABLE(PERF_HLSQ_WAVE_PENDING_NO_QUAD, UINT64, AVERAGE),
 296         COUNTABLE(PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE, UINT64, AVERAGE),
 297         COUNTABLE(PERF_HLSQ_STALL_CYCLES_VPC, UINT64, AVERAGE),
 298         COUNTABLE(PERF_HLSQ_PIXELS, UINT64, AVERAGE),
 299         COUNTABLE(PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC, UINT64, AVERAGE),
 300 };
 301
 302 static const struct fd_perfcntr_counter pc_counters[] = {
 303         COUNTER(PC_PERFCTR_PC_SEL_0, RBBM_PERFCTR_PC_0_LO, RBBM_PERFCTR_PC_0_HI),
 304         COUNTER(PC_PERFCTR_PC_SEL_1, RBBM_PERFCTR_PC_1_LO, RBBM_PERFCTR_PC_1_HI),
 305         COUNTER(PC_PERFCTR_PC_SEL_2, RBBM_PERFCTR_PC_2_LO, RBBM_PERFCTR_PC_2_HI),
 306         COUNTER(PC_PERFCTR_PC_SEL_3, RBBM_PERFCTR_PC_3_LO, RBBM_PERFCTR_PC_3_HI),
 307         COUNTER(PC_PERFCTR_PC_SEL_4, RBBM_PERFCTR_PC_4_LO, RBBM_PERFCTR_PC_4_HI),
 308         COUNTER(PC_PERFCTR_PC_SEL_5, RBBM_PERFCTR_PC_5_LO, RBBM_PERFCTR_PC_5_HI),
 309         COUNTER(PC_PERFCTR_PC_SEL_6, RBBM_PERFCTR_PC_6_LO, RBBM_PERFCTR_PC_6_HI),
 310         COUNTER(PC_PERFCTR_PC_SEL_7, RBBM_PERFCTR_PC_7_LO, RBBM_PERFCTR_PC_7_HI),
 311 };
 312
 313 static const struct fd_perfcntr_countable pc_countables[] = {
 314         COUNTABLE(PERF_PC_BUSY_CYCLES, UINT64, AVERAGE),
 315         COUNTABLE(PERF_PC_WORKING_CYCLES, UINT64, AVERAGE),
 316         COUNTABLE(PERF_PC_STALL_CYCLES_VFD, UINT64, AVERAGE),
 317         COUNTABLE(PERF_PC_STALL_CYCLES_TSE, UINT64, AVERAGE),
 318         COUNTABLE(PERF_PC_STALL_CYCLES_VPC, UINT64, AVERAGE),
 319         COUNTABLE(PERF_PC_STALL_CYCLES_UCHE, UINT64, AVERAGE),
 320         COUNTABLE(PERF_PC_STALL_CYCLES_TESS, UINT64, AVERAGE),
 321         COUNTABLE(PERF_PC_STALL_CYCLES_TSE_ONLY, UINT64, AVERAGE),
 322         COUNTABLE(PERF_PC_STALL_CYCLES_VPC_ONLY, UINT64, AVERAGE),
 323         COUNTABLE(PERF_PC_PASS1_TF_STALL_CYCLES, UINT64, AVERAGE),
 324         COUNTABLE(PERF_PC_STARVE_CYCLES_FOR_INDEX, UINT64, AVERAGE),
 325         COUNTABLE(PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR, UINT64, AVERAGE),
 326         COUNTABLE(PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM, UINT64, AVERAGE),
 327         COUNTABLE(PERF_PC_STARVE_CYCLES_FOR_POSITION, UINT64, AVERAGE),
 328         COUNTABLE(PERF_PC_STARVE_CYCLES_DI, UINT64, AVERAGE),
 329         COUNTABLE(PERF_PC_VIS_STREAMS_LOADED, UINT64, AVERAGE),
 330         COUNTABLE(PERF_PC_INSTANCES, UINT64, AVERAGE),
 331         COUNTABLE(PERF_PC_VPC_PRIMITIVES, UINT64, AVERAGE),
 332         COUNTABLE(PERF_PC_DEAD_PRIM, UINT64, AVERAGE),
 333         COUNTABLE(PERF_PC_LIVE_PRIM, UINT64, AVERAGE),
 334         COUNTABLE(PERF_PC_VERTEX_HITS, UINT64, AVERAGE),
 335         COUNTABLE(PERF_PC_IA_VERTICES, UINT64, AVERAGE),
 336         COUNTABLE(PERF_PC_IA_PRIMITIVES, UINT64, AVERAGE),
 337         COUNTABLE(PERF_PC_GS_PRIMITIVES, UINT64, AVERAGE),
 338         COUNTABLE(PERF_PC_HS_INVOCATIONS, UINT64, AVERAGE),
 339         COUNTABLE(PERF_PC_DS_INVOCATIONS, UINT64, AVERAGE),
 340         COUNTABLE(PERF_PC_VS_INVOCATIONS, UINT64, AVERAGE),
 341         COUNTABLE(PERF_PC_GS_INVOCATIONS, UINT64, AVERAGE),
 342         COUNTABLE(PERF_PC_DS_PRIMITIVES, UINT64, AVERAGE),
 343         COUNTABLE(PERF_PC_VPC_POS_DATA_TRANSACTION, UINT64, AVERAGE),
 344         COUNTABLE(PERF_PC_3D_DRAWCALLS, UINT64, AVERAGE),
 345         COUNTABLE(PERF_PC_2D_DRAWCALLS, UINT64, AVERAGE),
 346         COUNTABLE(PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS, UINT64, AVERAGE),
 347         COUNTABLE(PERF_TESS_BUSY_CYCLES, UINT64, AVERAGE),
 348         COUNTABLE(PERF_TESS_WORKING_CYCLES, UINT64, AVERAGE),
 349         COUNTABLE(PERF_TESS_STALL_CYCLES_PC, UINT64, AVERAGE),
 350         COUNTABLE(PERF_TESS_STARVE_CYCLES_PC, UINT64, AVERAGE),
 351         COUNTABLE(PERF_PC_TSE_TRANSACTION, UINT64, AVERAGE),
 352         COUNTABLE(PERF_PC_TSE_VERTEX, UINT64, AVERAGE),
 353         COUNTABLE(PERF_PC_TESS_PC_UV_TRANS, UINT64, AVERAGE),
 354         COUNTABLE(PERF_PC_TESS_PC_UV_PATCHES, UINT64, AVERAGE),
 355         COUNTABLE(PERF_PC_TESS_FACTOR_TRANS, UINT64, AVERAGE),
 356 };
 357
 358 static const struct fd_perfcntr_counter rb_counters[] = {
 359         COUNTER(RB_PERFCTR_RB_SEL_0, RBBM_PERFCTR_RB_0_LO, RBBM_PERFCTR_RB_0_HI),
 360         COUNTER(RB_PERFCTR_RB_SEL_1, RBBM_PERFCTR_RB_1_LO, RBBM_PERFCTR_RB_1_HI),
 361         COUNTER(RB_PERFCTR_RB_SEL_2, RBBM_PERFCTR_RB_2_LO, RBBM_PERFCTR_RB_2_HI),
 362         COUNTER(RB_PERFCTR_RB_SEL_3, RBBM_PERFCTR_RB_3_LO, RBBM_PERFCTR_RB_3_HI),
 363         COUNTER(RB_PERFCTR_RB_SEL_4, RBBM_PERFCTR_RB_4_LO, RBBM_PERFCTR_RB_4_HI),
 364         COUNTER(RB_PERFCTR_RB_SEL_5, RBBM_PERFCTR_RB_5_LO, RBBM_PERFCTR_RB_5_HI),
 365         COUNTER(RB_PERFCTR_RB_SEL_6, RBBM_PERFCTR_RB_6_LO, RBBM_PERFCTR_RB_6_HI),
 366         COUNTER(RB_PERFCTR_RB_SEL_7, RBBM_PERFCTR_RB_7_LO, RBBM_PERFCTR_RB_7_HI),
 367 };
 368
 369 static const struct fd_perfcntr_countable rb_countables[] = {
 370         COUNTABLE(PERF_RB_BUSY_CYCLES, UINT64, AVERAGE),
 371         COUNTABLE(PERF_RB_STALL_CYCLES_HLSQ, UINT64, AVERAGE),
 372         COUNTABLE(PERF_RB_STALL_CYCLES_FIFO0_FULL, UINT64, AVERAGE),
 373         COUNTABLE(PERF_RB_STALL_CYCLES_FIFO1_FULL, UINT64, AVERAGE),
 374         COUNTABLE(PERF_RB_STALL_CYCLES_FIFO2_FULL, UINT64, AVERAGE),
 375         COUNTABLE(PERF_RB_STARVE_CYCLES_SP, UINT64, AVERAGE),
 376         COUNTABLE(PERF_RB_STARVE_CYCLES_LRZ_TILE, UINT64, AVERAGE),
 377         COUNTABLE(PERF_RB_STARVE_CYCLES_CCU, UINT64, AVERAGE),
 378         COUNTABLE(PERF_RB_STARVE_CYCLES_Z_PLANE, UINT64, AVERAGE),
 379         COUNTABLE(PERF_RB_STARVE_CYCLES_BARY_PLANE, UINT64, AVERAGE),
 380         COUNTABLE(PERF_RB_Z_WORKLOAD, UINT64, AVERAGE),
 381         COUNTABLE(PERF_RB_HLSQ_ACTIVE, UINT64, AVERAGE),
 382         COUNTABLE(PERF_RB_Z_READ, UINT64, AVERAGE),
 383         COUNTABLE(PERF_RB_Z_WRITE, UINT64, AVERAGE),
 384         COUNTABLE(PERF_RB_C_READ, UINT64, AVERAGE),
 385         COUNTABLE(PERF_RB_C_WRITE, UINT64, AVERAGE),
 386         COUNTABLE(PERF_RB_TOTAL_PASS, UINT64, AVERAGE),
 387         COUNTABLE(PERF_RB_Z_PASS, UINT64, AVERAGE),
 388         COUNTABLE(PERF_RB_Z_FAIL, UINT64, AVERAGE),
 389         COUNTABLE(PERF_RB_S_FAIL, UINT64, AVERAGE),
 390         COUNTABLE(PERF_RB_BLENDED_FXP_COMPONENTS, UINT64, AVERAGE),
 391         COUNTABLE(PERF_RB_BLENDED_FP16_COMPONENTS, UINT64, AVERAGE),
 392         COUNTABLE(PERF_RB_PS_INVOCATIONS, UINT64, AVERAGE),
 393         COUNTABLE(PERF_RB_2D_ALIVE_CYCLES, UINT64, AVERAGE),
 394         COUNTABLE(PERF_RB_2D_STALL_CYCLES_A2D, UINT64, AVERAGE),
 395         COUNTABLE(PERF_RB_2D_STARVE_CYCLES_SRC, UINT64, AVERAGE),
 396         COUNTABLE(PERF_RB_2D_STARVE_CYCLES_SP, UINT64, AVERAGE),
 397         COUNTABLE(PERF_RB_2D_STARVE_CYCLES_DST, UINT64, AVERAGE),
 398         COUNTABLE(PERF_RB_2D_VALID_PIXELS, UINT64, AVERAGE),
 399         COUNTABLE(PERF_RB_3D_PIXELS, UINT64, AVERAGE),
 400         COUNTABLE(PERF_RB_BLENDER_WORKING_CYCLES, UINT64, AVERAGE),
 401         COUNTABLE(PERF_RB_ZPROC_WORKING_CYCLES, UINT64, AVERAGE),
 402         COUNTABLE(PERF_RB_CPROC_WORKING_CYCLES, UINT64, AVERAGE),
 403         COUNTABLE(PERF_RB_SAMPLER_WORKING_CYCLES, UINT64, AVERAGE),
 404         COUNTABLE(PERF_RB_STALL_CYCLES_CCU_COLOR_READ, UINT64, AVERAGE),
 405         COUNTABLE(PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE, UINT64, AVERAGE),
 406         COUNTABLE(PERF_RB_STALL_CYCLES_CCU_DEPTH_READ, UINT64, AVERAGE),
 407         COUNTABLE(PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE, UINT64, AVERAGE),
 408         COUNTABLE(PERF_RB_STALL_CYCLES_VPC, UINT64, AVERAGE),
 409         COUNTABLE(PERF_RB_2D_INPUT_TRANS, UINT64, AVERAGE),
 410         COUNTABLE(PERF_RB_2D_OUTPUT_RB_DST_TRANS, UINT64, AVERAGE),
 411         COUNTABLE(PERF_RB_2D_OUTPUT_RB_SRC_TRANS, UINT64, AVERAGE),
 412         COUNTABLE(PERF_RB_BLENDED_FP32_COMPONENTS, UINT64, AVERAGE),
 413         COUNTABLE(PERF_RB_COLOR_PIX_TILES, UINT64, AVERAGE),
 414         COUNTABLE(PERF_RB_STALL_CYCLES_CCU, UINT64, AVERAGE),
 415         COUNTABLE(PERF_RB_EARLY_Z_ARB3_GRANT, UINT64, AVERAGE),
 416         COUNTABLE(PERF_RB_LATE_Z_ARB3_GRANT, UINT64, AVERAGE),
 417         COUNTABLE(PERF_RB_EARLY_Z_SKIP_GRANT, UINT64, AVERAGE),
 418 };
 419
 420 static const struct fd_perfcntr_counter rbbm_counters[] = {
 421 //RESERVED: for kernel
 422 //      COUNTER(RBBM_PERFCTR_RBBM_SEL_0, RBBM_PERFCTR_RBBM_0_LO, RBBM_PERFCTR_RBBM_0_HI),
 423         COUNTER(RBBM_PERFCTR_RBBM_SEL_1, RBBM_PERFCTR_RBBM_1_LO, RBBM_PERFCTR_RBBM_1_HI),
 424         COUNTER(RBBM_PERFCTR_RBBM_SEL_2, RBBM_PERFCTR_RBBM_2_LO, RBBM_PERFCTR_RBBM_2_HI),
 425         COUNTER(RBBM_PERFCTR_RBBM_SEL_3, RBBM_PERFCTR_RBBM_3_LO, RBBM_PERFCTR_RBBM_3_HI),
 426 };
 427
 428 static const struct fd_perfcntr_countable rbbm_countables[] = {
 429         COUNTABLE(PERF_RBBM_ALWAYS_COUNT, UINT64, AVERAGE),
 430         COUNTABLE(PERF_RBBM_ALWAYS_ON, UINT64, AVERAGE),
 431         COUNTABLE(PERF_RBBM_TSE_BUSY, UINT64, AVERAGE),
 432         COUNTABLE(PERF_RBBM_RAS_BUSY, UINT64, AVERAGE),
 433         COUNTABLE(PERF_RBBM_PC_DCALL_BUSY, UINT64, AVERAGE),
 434         COUNTABLE(PERF_RBBM_PC_VSD_BUSY, UINT64, AVERAGE),
 435         COUNTABLE(PERF_RBBM_STATUS_MASKED, UINT64, AVERAGE),
 436         COUNTABLE(PERF_RBBM_COM_BUSY, UINT64, AVERAGE),
 437         COUNTABLE(PERF_RBBM_DCOM_BUSY, UINT64, AVERAGE),
 438         COUNTABLE(PERF_RBBM_VBIF_BUSY, UINT64, AVERAGE),
 439         COUNTABLE(PERF_RBBM_VSC_BUSY, UINT64, AVERAGE),
 440         COUNTABLE(PERF_RBBM_TESS_BUSY, UINT64, AVERAGE),
 441         COUNTABLE(PERF_RBBM_UCHE_BUSY, UINT64, AVERAGE),
 442         COUNTABLE(PERF_RBBM_HLSQ_BUSY, UINT64, AVERAGE),
 443 };
 444
 445 static const struct fd_perfcntr_counter sp_counters[] = {
 446 //RESERVED: for kernel
 447 //      COUNTER(SP_PERFCTR_SP_SEL_0,  RBBM_PERFCTR_SP_0_LO,  RBBM_PERFCTR_SP_0_HI),
 448         COUNTER(SP_PERFCTR_SP_SEL_1,  RBBM_PERFCTR_SP_1_LO,  RBBM_PERFCTR_SP_1_HI),
 449         COUNTER(SP_PERFCTR_SP_SEL_2,  RBBM_PERFCTR_SP_2_LO,  RBBM_PERFCTR_SP_2_HI),
 450         COUNTER(SP_PERFCTR_SP_SEL_3,  RBBM_PERFCTR_SP_3_LO,  RBBM_PERFCTR_SP_3_HI),
 451         COUNTER(SP_PERFCTR_SP_SEL_4,  RBBM_PERFCTR_SP_4_LO,  RBBM_PERFCTR_SP_4_HI),
 452         COUNTER(SP_PERFCTR_SP_SEL_5,  RBBM_PERFCTR_SP_5_LO,  RBBM_PERFCTR_SP_5_HI),
 453         COUNTER(SP_PERFCTR_SP_SEL_6,  RBBM_PERFCTR_SP_6_LO,  RBBM_PERFCTR_SP_6_HI),
 454         COUNTER(SP_PERFCTR_SP_SEL_7,  RBBM_PERFCTR_SP_7_LO,  RBBM_PERFCTR_SP_7_HI),
 455         COUNTER(SP_PERFCTR_SP_SEL_8,  RBBM_PERFCTR_SP_8_LO,  RBBM_PERFCTR_SP_8_HI),
 456         COUNTER(SP_PERFCTR_SP_SEL_9,  RBBM_PERFCTR_SP_9_LO,  RBBM_PERFCTR_SP_9_HI),
 457         COUNTER(SP_PERFCTR_SP_SEL_10, RBBM_PERFCTR_SP_10_LO, RBBM_PERFCTR_SP_10_HI),
 458         COUNTER(SP_PERFCTR_SP_SEL_11, RBBM_PERFCTR_SP_11_LO, RBBM_PERFCTR_SP_11_HI),
 459         COUNTER(SP_PERFCTR_SP_SEL_12, RBBM_PERFCTR_SP_12_LO, RBBM_PERFCTR_SP_12_HI),
 460         COUNTER(SP_PERFCTR_SP_SEL_13, RBBM_PERFCTR_SP_13_LO, RBBM_PERFCTR_SP_13_HI),
 461         COUNTER(SP_PERFCTR_SP_SEL_14, RBBM_PERFCTR_SP_14_LO, RBBM_PERFCTR_SP_14_HI),
 462         COUNTER(SP_PERFCTR_SP_SEL_15, RBBM_PERFCTR_SP_15_LO, RBBM_PERFCTR_SP_15_HI),
 463         COUNTER(SP_PERFCTR_SP_SEL_16, RBBM_PERFCTR_SP_16_LO, RBBM_PERFCTR_SP_16_HI),
 464         COUNTER(SP_PERFCTR_SP_SEL_17, RBBM_PERFCTR_SP_17_LO, RBBM_PERFCTR_SP_17_HI),
 465         COUNTER(SP_PERFCTR_SP_SEL_18, RBBM_PERFCTR_SP_18_LO, RBBM_PERFCTR_SP_18_HI),
 466         COUNTER(SP_PERFCTR_SP_SEL_19, RBBM_PERFCTR_SP_19_LO, RBBM_PERFCTR_SP_19_HI),
 467         COUNTER(SP_PERFCTR_SP_SEL_20, RBBM_PERFCTR_SP_20_LO, RBBM_PERFCTR_SP_20_HI),
 468         COUNTER(SP_PERFCTR_SP_SEL_21, RBBM_PERFCTR_SP_21_LO, RBBM_PERFCTR_SP_21_HI),
 469         COUNTER(SP_PERFCTR_SP_SEL_22, RBBM_PERFCTR_SP_22_LO, RBBM_PERFCTR_SP_22_HI),
 470         COUNTER(SP_PERFCTR_SP_SEL_23, RBBM_PERFCTR_SP_23_LO, RBBM_PERFCTR_SP_23_HI),
 471 };
 472
 473 static const struct fd_perfcntr_countable sp_countables[] = {
 474         COUNTABLE(PERF_SP_BUSY_CYCLES, UINT64, AVERAGE),
 475         COUNTABLE(PERF_SP_ALU_WORKING_CYCLES, UINT64, AVERAGE),
 476         COUNTABLE(PERF_SP_EFU_WORKING_CYCLES, UINT64, AVERAGE),
 477         COUNTABLE(PERF_SP_STALL_CYCLES_VPC, UINT64, AVERAGE),
 478         COUNTABLE(PERF_SP_STALL_CYCLES_TP, UINT64, AVERAGE),
 479         COUNTABLE(PERF_SP_STALL_CYCLES_UCHE, UINT64, AVERAGE),
 480         COUNTABLE(PERF_SP_STALL_CYCLES_RB, UINT64, AVERAGE),
 481         COUNTABLE(PERF_SP_NON_EXECUTION_CYCLES, UINT64, AVERAGE),
 482         COUNTABLE(PERF_SP_WAVE_CONTEXTS, UINT64, AVERAGE),
 483         COUNTABLE(PERF_SP_WAVE_CONTEXT_CYCLES, UINT64, AVERAGE),
 484         COUNTABLE(PERF_SP_FS_STAGE_WAVE_CYCLES, UINT64, AVERAGE),
 485         COUNTABLE(PERF_SP_FS_STAGE_WAVE_SAMPLES, UINT64, AVERAGE),
 486         COUNTABLE(PERF_SP_VS_STAGE_WAVE_CYCLES, UINT64, AVERAGE),
 487         COUNTABLE(PERF_SP_VS_STAGE_WAVE_SAMPLES, UINT64, AVERAGE),
 488         COUNTABLE(PERF_SP_FS_STAGE_DURATION_CYCLES, UINT64, AVERAGE),
 489         COUNTABLE(PERF_SP_VS_STAGE_DURATION_CYCLES, UINT64, AVERAGE),
 490         COUNTABLE(PERF_SP_WAVE_CTRL_CYCLES, UINT64, AVERAGE),
 491         COUNTABLE(PERF_SP_WAVE_LOAD_CYCLES, UINT64, AVERAGE),
 492         COUNTABLE(PERF_SP_WAVE_EMIT_CYCLES, UINT64, AVERAGE),
 493         COUNTABLE(PERF_SP_WAVE_NOP_CYCLES, UINT64, AVERAGE),
 494         COUNTABLE(PERF_SP_WAVE_WAIT_CYCLES, UINT64, AVERAGE),
 495         COUNTABLE(PERF_SP_WAVE_FETCH_CYCLES, UINT64, AVERAGE),
 496         COUNTABLE(PERF_SP_WAVE_IDLE_CYCLES, UINT64, AVERAGE),
 497         COUNTABLE(PERF_SP_WAVE_END_CYCLES, UINT64, AVERAGE),
 498         COUNTABLE(PERF_SP_WAVE_LONG_SYNC_CYCLES, UINT64, AVERAGE),
 499         COUNTABLE(PERF_SP_WAVE_SHORT_SYNC_CYCLES, UINT64, AVERAGE),
 500         COUNTABLE(PERF_SP_WAVE_JOIN_CYCLES, UINT64, AVERAGE),
 501         COUNTABLE(PERF_SP_LM_LOAD_INSTRUCTIONS, UINT64, AVERAGE),
 502         COUNTABLE(PERF_SP_LM_STORE_INSTRUCTIONS, UINT64, AVERAGE),
 503         COUNTABLE(PERF_SP_LM_ATOMICS, UINT64, AVERAGE),
 504         COUNTABLE(PERF_SP_GM_LOAD_INSTRUCTIONS, UINT64, AVERAGE),
 505         COUNTABLE(PERF_SP_GM_STORE_INSTRUCTIONS, UINT64, AVERAGE),
 506         COUNTABLE(PERF_SP_GM_ATOMICS, UINT64, AVERAGE),
 507         COUNTABLE(PERF_SP_VS_STAGE_TEX_INSTRUCTIONS, UINT64, AVERAGE),
 508         COUNTABLE(PERF_SP_VS_STAGE_EFU_INSTRUCTIONS, UINT64, AVERAGE),
 509         COUNTABLE(PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS, UINT64, AVERAGE),
 510         COUNTABLE(PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS, UINT64, AVERAGE),
 511         COUNTABLE(PERF_SP_FS_STAGE_TEX_INSTRUCTIONS, UINT64, AVERAGE),
 512         COUNTABLE(PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS, UINT64, AVERAGE),
 513         COUNTABLE(PERF_SP_FS_STAGE_EFU_INSTRUCTIONS, UINT64, AVERAGE),
 514         COUNTABLE(PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS, UINT64, AVERAGE),
 515         COUNTABLE(PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS, UINT64, AVERAGE),
 516         COUNTABLE(PERF_SP_FS_STAGE_BARY_INSTRUCTIONS, UINT64, AVERAGE),
 517         COUNTABLE(PERF_SP_VS_INSTRUCTIONS, UINT64, AVERAGE),
 518         COUNTABLE(PERF_SP_FS_INSTRUCTIONS, UINT64, AVERAGE),
 519         COUNTABLE(PERF_SP_ADDR_LOCK_COUNT, UINT64, AVERAGE),
 520         COUNTABLE(PERF_SP_UCHE_READ_TRANS, UINT64, AVERAGE),
 521         COUNTABLE(PERF_SP_UCHE_WRITE_TRANS, UINT64, AVERAGE),
 522         COUNTABLE(PERF_SP_EXPORT_VPC_TRANS, UINT64, AVERAGE),
 523         COUNTABLE(PERF_SP_EXPORT_RB_TRANS, UINT64, AVERAGE),
 524         COUNTABLE(PERF_SP_PIXELS_KILLED, UINT64, AVERAGE),
 525         COUNTABLE(PERF_SP_ICL1_REQUESTS, UINT64, AVERAGE),
 526         COUNTABLE(PERF_SP_ICL1_MISSES, UINT64, AVERAGE),
 527         COUNTABLE(PERF_SP_HS_INSTRUCTIONS, UINT64, AVERAGE),
 528         COUNTABLE(PERF_SP_DS_INSTRUCTIONS, UINT64, AVERAGE),
 529         COUNTABLE(PERF_SP_GS_INSTRUCTIONS, UINT64, AVERAGE),
 530         COUNTABLE(PERF_SP_CS_INSTRUCTIONS, UINT64, AVERAGE),
 531         COUNTABLE(PERF_SP_GPR_READ, UINT64, AVERAGE),
 532         COUNTABLE(PERF_SP_GPR_WRITE, UINT64, AVERAGE),
 533         COUNTABLE(PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS, UINT64, AVERAGE),
 534         COUNTABLE(PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS, UINT64, AVERAGE),
 535         COUNTABLE(PERF_SP_LM_BANK_CONFLICTS, UINT64, AVERAGE),
 536         COUNTABLE(PERF_SP_TEX_CONTROL_WORKING_CYCLES, UINT64, AVERAGE),
 537         COUNTABLE(PERF_SP_LOAD_CONTROL_WORKING_CYCLES, UINT64, AVERAGE),
 538         COUNTABLE(PERF_SP_FLOW_CONTROL_WORKING_CYCLES, UINT64, AVERAGE),
 539         COUNTABLE(PERF_SP_LM_WORKING_CYCLES, UINT64, AVERAGE),
 540         COUNTABLE(PERF_SP_DISPATCHER_WORKING_CYCLES, UINT64, AVERAGE),
 541         COUNTABLE(PERF_SP_SEQUENCER_WORKING_CYCLES, UINT64, AVERAGE),
 542         COUNTABLE(PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP, UINT64, AVERAGE),
 543         COUNTABLE(PERF_SP_STARVE_CYCLES_HLSQ, UINT64, AVERAGE),
 544         COUNTABLE(PERF_SP_NON_EXECUTION_LS_CYCLES, UINT64, AVERAGE),
 545         COUNTABLE(PERF_SP_WORKING_EU, UINT64, AVERAGE),
 546         COUNTABLE(PERF_SP_ANY_EU_WORKING, UINT64, AVERAGE),
 547         COUNTABLE(PERF_SP_WORKING_EU_FS_STAGE, UINT64, AVERAGE),
 548         COUNTABLE(PERF_SP_ANY_EU_WORKING_FS_STAGE, UINT64, AVERAGE),
 549         COUNTABLE(PERF_SP_WORKING_EU_VS_STAGE, UINT64, AVERAGE),
 550         COUNTABLE(PERF_SP_ANY_EU_WORKING_VS_STAGE, UINT64, AVERAGE),
 551         COUNTABLE(PERF_SP_WORKING_EU_CS_STAGE, UINT64, AVERAGE),
 552         COUNTABLE(PERF_SP_ANY_EU_WORKING_CS_STAGE, UINT64, AVERAGE),
 553         COUNTABLE(PERF_SP_GPR_READ_PREFETCH, UINT64, AVERAGE),
 554         COUNTABLE(PERF_SP_GPR_READ_CONFLICT, UINT64, AVERAGE),
 555         COUNTABLE(PERF_SP_GPR_WRITE_CONFLICT, UINT64, AVERAGE),
 556         COUNTABLE(PERF_SP_GM_LOAD_LATENCY_CYCLES, UINT64, AVERAGE),
 557         COUNTABLE(PERF_SP_GM_LOAD_LATENCY_SAMPLES, UINT64, AVERAGE),
 558         COUNTABLE(PERF_SP_EXECUTABLE_WAVES, UINT64, AVERAGE),
 559 };
 560
 561 static const struct fd_perfcntr_counter tp_counters[] = {
 562         COUNTER(TPL1_PERFCTR_TP_SEL_0,  RBBM_PERFCTR_TP_0_LO,  RBBM_PERFCTR_TP_0_HI),
 563         COUNTER(TPL1_PERFCTR_TP_SEL_1,  RBBM_PERFCTR_TP_1_LO,  RBBM_PERFCTR_TP_1_HI),
 564         COUNTER(TPL1_PERFCTR_TP_SEL_2,  RBBM_PERFCTR_TP_2_LO,  RBBM_PERFCTR_TP_2_HI),
 565         COUNTER(TPL1_PERFCTR_TP_SEL_3,  RBBM_PERFCTR_TP_3_LO,  RBBM_PERFCTR_TP_3_HI),
 566         COUNTER(TPL1_PERFCTR_TP_SEL_4,  RBBM_PERFCTR_TP_4_LO,  RBBM_PERFCTR_TP_4_HI),
 567         COUNTER(TPL1_PERFCTR_TP_SEL_5,  RBBM_PERFCTR_TP_5_LO,  RBBM_PERFCTR_TP_5_HI),
 568         COUNTER(TPL1_PERFCTR_TP_SEL_6,  RBBM_PERFCTR_TP_6_LO,  RBBM_PERFCTR_TP_6_HI),
 569         COUNTER(TPL1_PERFCTR_TP_SEL_7,  RBBM_PERFCTR_TP_7_LO,  RBBM_PERFCTR_TP_7_HI),
 570         COUNTER(TPL1_PERFCTR_TP_SEL_8,  RBBM_PERFCTR_TP_8_LO,  RBBM_PERFCTR_TP_8_HI),
 571         COUNTER(TPL1_PERFCTR_TP_SEL_9,  RBBM_PERFCTR_TP_9_LO,  RBBM_PERFCTR_TP_9_HI),
 572         COUNTER(TPL1_PERFCTR_TP_SEL_10, RBBM_PERFCTR_TP_10_LO, RBBM_PERFCTR_TP_10_HI),
 573         COUNTER(TPL1_PERFCTR_TP_SEL_11, RBBM_PERFCTR_TP_11_LO, RBBM_PERFCTR_TP_11_HI),
 574 };
 575
 576 static const struct fd_perfcntr_countable tp_countables[] = {
 577         COUNTABLE(PERF_TP_BUSY_CYCLES, UINT64, AVERAGE),
 578         COUNTABLE(PERF_TP_STALL_CYCLES_UCHE, UINT64, AVERAGE),
 579         COUNTABLE(PERF_TP_LATENCY_CYCLES, UINT64, AVERAGE),
 580         COUNTABLE(PERF_TP_LATENCY_TRANS, UINT64, AVERAGE),
 581         COUNTABLE(PERF_TP_FLAG_CACHE_REQUEST_SAMPLES, UINT64, AVERAGE),
 582         COUNTABLE(PERF_TP_FLAG_CACHE_REQUEST_LATENCY, UINT64, AVERAGE),
 583         COUNTABLE(PERF_TP_L1_CACHELINE_REQUESTS, UINT64, AVERAGE),
 584         COUNTABLE(PERF_TP_L1_CACHELINE_MISSES, UINT64, AVERAGE),
 585         COUNTABLE(PERF_TP_SP_TP_TRANS, UINT64, AVERAGE),
 586         COUNTABLE(PERF_TP_TP_SP_TRANS, UINT64, AVERAGE),
 587         COUNTABLE(PERF_TP_OUTPUT_PIXELS, UINT64, AVERAGE),
 588         COUNTABLE(PERF_TP_FILTER_WORKLOAD_16BIT, UINT64, AVERAGE),
 589         COUNTABLE(PERF_TP_FILTER_WORKLOAD_32BIT, UINT64, AVERAGE),
 590         COUNTABLE(PERF_TP_QUADS_RECEIVED, UINT64, AVERAGE),
 591         COUNTABLE(PERF_TP_QUADS_OFFSET, UINT64, AVERAGE),
 592         COUNTABLE(PERF_TP_QUADS_SHADOW, UINT64, AVERAGE),
 593         COUNTABLE(PERF_TP_QUADS_ARRAY, UINT64, AVERAGE),
 594         COUNTABLE(PERF_TP_QUADS_GRADIENT, UINT64, AVERAGE),
 595         COUNTABLE(PERF_TP_QUADS_1D, UINT64, AVERAGE),
 596         COUNTABLE(PERF_TP_QUADS_2D, UINT64, AVERAGE),
 597         COUNTABLE(PERF_TP_QUADS_BUFFER, UINT64, AVERAGE),
 598         COUNTABLE(PERF_TP_QUADS_3D, UINT64, AVERAGE),
 599         COUNTABLE(PERF_TP_QUADS_CUBE, UINT64, AVERAGE),
 600         COUNTABLE(PERF_TP_DIVERGENT_QUADS_RECEIVED, UINT64, AVERAGE),
 601         COUNTABLE(PERF_TP_PRT_NON_RESIDENT_EVENTS, UINT64, AVERAGE),
 602         COUNTABLE(PERF_TP_OUTPUT_PIXELS_POINT, UINT64, AVERAGE),
 603         COUNTABLE(PERF_TP_OUTPUT_PIXELS_BILINEAR, UINT64, AVERAGE),
 604         COUNTABLE(PERF_TP_OUTPUT_PIXELS_MIP, UINT64, AVERAGE),
 605         COUNTABLE(PERF_TP_OUTPUT_PIXELS_ANISO, UINT64, AVERAGE),
 606         COUNTABLE(PERF_TP_OUTPUT_PIXELS_ZERO_LOD, UINT64, AVERAGE),
 607         COUNTABLE(PERF_TP_FLAG_CACHE_REQUESTS, UINT64, AVERAGE),
 608         COUNTABLE(PERF_TP_FLAG_CACHE_MISSES, UINT64, AVERAGE),
 609         COUNTABLE(PERF_TP_L1_5_L2_REQUESTS, UINT64, AVERAGE),
 610         COUNTABLE(PERF_TP_2D_OUTPUT_PIXELS, UINT64, AVERAGE),
 611         COUNTABLE(PERF_TP_2D_OUTPUT_PIXELS_POINT, UINT64, AVERAGE),
 612         COUNTABLE(PERF_TP_2D_OUTPUT_PIXELS_BILINEAR, UINT64, AVERAGE),
 613         COUNTABLE(PERF_TP_2D_FILTER_WORKLOAD_16BIT, UINT64, AVERAGE),
 614         COUNTABLE(PERF_TP_2D_FILTER_WORKLOAD_32BIT, UINT64, AVERAGE),
 615         COUNTABLE(PERF_TP_TPA2TPC_TRANS, UINT64, AVERAGE),
 616         COUNTABLE(PERF_TP_L1_MISSES_ASTC_1TILE, UINT64, AVERAGE),
 617         COUNTABLE(PERF_TP_L1_MISSES_ASTC_2TILE, UINT64, AVERAGE),
 618         COUNTABLE(PERF_TP_L1_MISSES_ASTC_4TILE, UINT64, AVERAGE),
 619         COUNTABLE(PERF_TP_L1_5_L2_COMPRESS_REQS, UINT64, AVERAGE),
 620         COUNTABLE(PERF_TP_L1_5_L2_COMPRESS_MISS, UINT64, AVERAGE),
 621         COUNTABLE(PERF_TP_L1_BANK_CONFLICT, UINT64, AVERAGE),
 622         COUNTABLE(PERF_TP_L1_5_MISS_LATENCY_CYCLES, UINT64, AVERAGE),
 623         COUNTABLE(PERF_TP_L1_5_MISS_LATENCY_TRANS, UINT64, AVERAGE),
 624         COUNTABLE(PERF_TP_QUADS_CONSTANT_MULTIPLIED, UINT64, AVERAGE),
 625         COUNTABLE(PERF_TP_FRONTEND_WORKING_CYCLES, UINT64, AVERAGE),
 626         COUNTABLE(PERF_TP_L1_TAG_WORKING_CYCLES, UINT64, AVERAGE),
 627         COUNTABLE(PERF_TP_L1_DATA_WRITE_WORKING_CYCLES, UINT64, AVERAGE),
 628         COUNTABLE(PERF_TP_PRE_L1_DECOM_WORKING_CYCLES, UINT64, AVERAGE),
 629         COUNTABLE(PERF_TP_BACKEND_WORKING_CYCLES, UINT64, AVERAGE),
 630         COUNTABLE(PERF_TP_FLAG_CACHE_WORKING_CYCLES, UINT64, AVERAGE),
 631         COUNTABLE(PERF_TP_L1_5_CACHE_WORKING_CYCLES, UINT64, AVERAGE),
 632         COUNTABLE(PERF_TP_STARVE_CYCLES_SP, UINT64, AVERAGE),
 633         COUNTABLE(PERF_TP_STARVE_CYCLES_UCHE, UINT64, AVERAGE),
 634 };
 635
 636 static const struct fd_perfcntr_counter uche_counters[] = {
 637         COUNTER(UCHE_PERFCTR_UCHE_SEL_0,  RBBM_PERFCTR_UCHE_0_LO,  RBBM_PERFCTR_UCHE_0_HI),
 638         COUNTER(UCHE_PERFCTR_UCHE_SEL_1,  RBBM_PERFCTR_UCHE_1_LO,  RBBM_PERFCTR_UCHE_1_HI),
 639         COUNTER(UCHE_PERFCTR_UCHE_SEL_2,  RBBM_PERFCTR_UCHE_2_LO,  RBBM_PERFCTR_UCHE_2_HI),
 640         COUNTER(UCHE_PERFCTR_UCHE_SEL_3,  RBBM_PERFCTR_UCHE_3_LO,  RBBM_PERFCTR_UCHE_3_HI),
 641         COUNTER(UCHE_PERFCTR_UCHE_SEL_4,  RBBM_PERFCTR_UCHE_4_LO,  RBBM_PERFCTR_UCHE_4_HI),
 642         COUNTER(UCHE_PERFCTR_UCHE_SEL_5,  RBBM_PERFCTR_UCHE_5_LO,  RBBM_PERFCTR_UCHE_5_HI),
 643         COUNTER(UCHE_PERFCTR_UCHE_SEL_6,  RBBM_PERFCTR_UCHE_6_LO,  RBBM_PERFCTR_UCHE_6_HI),
 644         COUNTER(UCHE_PERFCTR_UCHE_SEL_7,  RBBM_PERFCTR_UCHE_7_LO,  RBBM_PERFCTR_UCHE_7_HI),
 645         COUNTER(UCHE_PERFCTR_UCHE_SEL_8,  RBBM_PERFCTR_UCHE_8_LO,  RBBM_PERFCTR_UCHE_8_HI),
 646         COUNTER(UCHE_PERFCTR_UCHE_SEL_9,  RBBM_PERFCTR_UCHE_9_LO,  RBBM_PERFCTR_UCHE_9_HI),
 647         COUNTER(UCHE_PERFCTR_UCHE_SEL_10, RBBM_PERFCTR_UCHE_10_LO, RBBM_PERFCTR_UCHE_10_HI),
 648         COUNTER(UCHE_PERFCTR_UCHE_SEL_11, RBBM_PERFCTR_UCHE_11_LO, RBBM_PERFCTR_UCHE_11_HI),
 649 };
 650
 651 static const struct fd_perfcntr_countable uche_countables[] = {
 652         COUNTABLE(PERF_UCHE_BUSY_CYCLES, UINT64, AVERAGE),
 653         COUNTABLE(PERF_UCHE_STALL_CYCLES_ARBITER, UINT64, AVERAGE),
 654         COUNTABLE(PERF_UCHE_VBIF_LATENCY_CYCLES, UINT64, AVERAGE),
 655         COUNTABLE(PERF_UCHE_VBIF_LATENCY_SAMPLES, UINT64, AVERAGE),
 656         COUNTABLE(PERF_UCHE_VBIF_READ_BEATS_TP, UINT64, AVERAGE),
 657         COUNTABLE(PERF_UCHE_VBIF_READ_BEATS_VFD, UINT64, AVERAGE),
 658         COUNTABLE(PERF_UCHE_VBIF_READ_BEATS_HLSQ, UINT64, AVERAGE),
 659         COUNTABLE(PERF_UCHE_VBIF_READ_BEATS_LRZ, UINT64, AVERAGE),
 660         COUNTABLE(PERF_UCHE_VBIF_READ_BEATS_SP, UINT64, AVERAGE),
 661         COUNTABLE(PERF_UCHE_READ_REQUESTS_TP, UINT64, AVERAGE),
 662         COUNTABLE(PERF_UCHE_READ_REQUESTS_VFD, UINT64, AVERAGE),
 663         COUNTABLE(PERF_UCHE_READ_REQUESTS_HLSQ, UINT64, AVERAGE),
 664         COUNTABLE(PERF_UCHE_READ_REQUESTS_LRZ, UINT64, AVERAGE),
 665         COUNTABLE(PERF_UCHE_READ_REQUESTS_SP, UINT64, AVERAGE),
 666         COUNTABLE(PERF_UCHE_WRITE_REQUESTS_LRZ, UINT64, AVERAGE),
 667         COUNTABLE(PERF_UCHE_WRITE_REQUESTS_SP, UINT64, AVERAGE),
 668         COUNTABLE(PERF_UCHE_WRITE_REQUESTS_VPC, UINT64, AVERAGE),
 669         COUNTABLE(PERF_UCHE_WRITE_REQUESTS_VSC, UINT64, AVERAGE),
 670         COUNTABLE(PERF_UCHE_EVICTS, UINT64, AVERAGE),
 671         COUNTABLE(PERF_UCHE_BANK_REQ0, UINT64, AVERAGE),
 672         COUNTABLE(PERF_UCHE_BANK_REQ1, UINT64, AVERAGE),
 673         COUNTABLE(PERF_UCHE_BANK_REQ2, UINT64, AVERAGE),
 674         COUNTABLE(PERF_UCHE_BANK_REQ3, UINT64, AVERAGE),
 675         COUNTABLE(PERF_UCHE_BANK_REQ4, UINT64, AVERAGE),
 676         COUNTABLE(PERF_UCHE_BANK_REQ5, UINT64, AVERAGE),
 677         COUNTABLE(PERF_UCHE_BANK_REQ6, UINT64, AVERAGE),
 678         COUNTABLE(PERF_UCHE_BANK_REQ7, UINT64, AVERAGE),
 679         COUNTABLE(PERF_UCHE_VBIF_READ_BEATS_CH0, UINT64, AVERAGE),
 680         COUNTABLE(PERF_UCHE_VBIF_READ_BEATS_CH1, UINT64, AVERAGE),
 681         COUNTABLE(PERF_UCHE_GMEM_READ_BEATS, UINT64, AVERAGE),
 682         COUNTABLE(PERF_UCHE_TPH_REF_FULL, UINT64, AVERAGE),
 683         COUNTABLE(PERF_UCHE_TPH_VICTIM_FULL, UINT64, AVERAGE),
 684         COUNTABLE(PERF_UCHE_TPH_EXT_FULL, UINT64, AVERAGE),
 685         COUNTABLE(PERF_UCHE_VBIF_STALL_WRITE_DATA, UINT64, AVERAGE),
 686         COUNTABLE(PERF_UCHE_DCMP_LATENCY_SAMPLES, UINT64, AVERAGE),
 687         COUNTABLE(PERF_UCHE_DCMP_LATENCY_CYCLES, UINT64, AVERAGE),
 688         COUNTABLE(PERF_UCHE_VBIF_READ_BEATS_PC, UINT64, AVERAGE),
 689         COUNTABLE(PERF_UCHE_READ_REQUESTS_PC, UINT64, AVERAGE),
 690         COUNTABLE(PERF_UCHE_RAM_READ_REQ, UINT64, AVERAGE),
 691         COUNTABLE(PERF_UCHE_RAM_WRITE_REQ, UINT64, AVERAGE),
 692 };
 693
 694 static const struct fd_perfcntr_counter vfd_counters[] = {
 695         COUNTER(VFD_PERFCTR_VFD_SEL_0, RBBM_PERFCTR_VFD_0_LO, RBBM_PERFCTR_VFD_0_HI),
 696         COUNTER(VFD_PERFCTR_VFD_SEL_1, RBBM_PERFCTR_VFD_1_LO, RBBM_PERFCTR_VFD_1_HI),
 697         COUNTER(VFD_PERFCTR_VFD_SEL_2, RBBM_PERFCTR_VFD_2_LO, RBBM_PERFCTR_VFD_2_HI),
 698         COUNTER(VFD_PERFCTR_VFD_SEL_3, RBBM_PERFCTR_VFD_3_LO, RBBM_PERFCTR_VFD_3_HI),
 699         COUNTER(VFD_PERFCTR_VFD_SEL_4, RBBM_PERFCTR_VFD_4_LO, RBBM_PERFCTR_VFD_4_HI),
 700         COUNTER(VFD_PERFCTR_VFD_SEL_5, RBBM_PERFCTR_VFD_5_LO, RBBM_PERFCTR_VFD_5_HI),
 701         COUNTER(VFD_PERFCTR_VFD_SEL_6, RBBM_PERFCTR_VFD_6_LO, RBBM_PERFCTR_VFD_6_HI),
 702         COUNTER(VFD_PERFCTR_VFD_SEL_7, RBBM_PERFCTR_VFD_7_LO, RBBM_PERFCTR_VFD_7_HI),
 703 };
 704
 705 static const struct fd_perfcntr_countable vfd_countables[] = {
 706         COUNTABLE(PERF_VFD_BUSY_CYCLES, UINT64, AVERAGE),
 707         COUNTABLE(PERF_VFD_STALL_CYCLES_UCHE, UINT64, AVERAGE),
 708         COUNTABLE(PERF_VFD_STALL_CYCLES_VPC_ALLOC, UINT64, AVERAGE),
 709         COUNTABLE(PERF_VFD_STALL_CYCLES_SP_INFO, UINT64, AVERAGE),
 710         COUNTABLE(PERF_VFD_STALL_CYCLES_SP_ATTR, UINT64, AVERAGE),
 711         COUNTABLE(PERF_VFD_STARVE_CYCLES_UCHE, UINT64, AVERAGE),
 712         COUNTABLE(PERF_VFD_RBUFFER_FULL, UINT64, AVERAGE),
 713         COUNTABLE(PERF_VFD_ATTR_INFO_FIFO_FULL, UINT64, AVERAGE),
 714         COUNTABLE(PERF_VFD_DECODED_ATTRIBUTE_BYTES, UINT64, AVERAGE),
 715         COUNTABLE(PERF_VFD_NUM_ATTRIBUTES, UINT64, AVERAGE),
 716         COUNTABLE(PERF_VFD_UPPER_SHADER_FIBERS, UINT64, AVERAGE),
 717         COUNTABLE(PERF_VFD_LOWER_SHADER_FIBERS, UINT64, AVERAGE),
 718         COUNTABLE(PERF_VFD_MODE_0_FIBERS, UINT64, AVERAGE),
 719         COUNTABLE(PERF_VFD_MODE_1_FIBERS, UINT64, AVERAGE),
 720         COUNTABLE(PERF_VFD_MODE_2_FIBERS, UINT64, AVERAGE),
 721         COUNTABLE(PERF_VFD_MODE_3_FIBERS, UINT64, AVERAGE),
 722         COUNTABLE(PERF_VFD_MODE_4_FIBERS, UINT64, AVERAGE),
 723         COUNTABLE(PERF_VFD_TOTAL_VERTICES, UINT64, AVERAGE),
 724         COUNTABLE(PERF_VFDP_STALL_CYCLES_VFD, UINT64, AVERAGE),
 725         COUNTABLE(PERF_VFDP_STALL_CYCLES_VFD_INDEX, UINT64, AVERAGE),
 726         COUNTABLE(PERF_VFDP_STALL_CYCLES_VFD_PROG, UINT64, AVERAGE),
 727         COUNTABLE(PERF_VFDP_STARVE_CYCLES_PC, UINT64, AVERAGE),
 728         COUNTABLE(PERF_VFDP_VS_STAGE_WAVES, UINT64, AVERAGE),
 729 };
 730
 731 static const struct fd_perfcntr_counter vpc_counters[] = {
 732         COUNTER(VPC_PERFCTR_VPC_SEL_0, RBBM_PERFCTR_VPC_0_LO, RBBM_PERFCTR_VPC_0_HI),
 733         COUNTER(VPC_PERFCTR_VPC_SEL_1, RBBM_PERFCTR_VPC_1_LO, RBBM_PERFCTR_VPC_1_HI),
 734         COUNTER(VPC_PERFCTR_VPC_SEL_2, RBBM_PERFCTR_VPC_2_LO, RBBM_PERFCTR_VPC_2_HI),
 735         COUNTER(VPC_PERFCTR_VPC_SEL_3, RBBM_PERFCTR_VPC_3_LO, RBBM_PERFCTR_VPC_3_HI),
 736         COUNTER(VPC_PERFCTR_VPC_SEL_4, RBBM_PERFCTR_VPC_4_LO, RBBM_PERFCTR_VPC_4_HI),
 737         COUNTER(VPC_PERFCTR_VPC_SEL_5, RBBM_PERFCTR_VPC_5_LO, RBBM_PERFCTR_VPC_5_HI),
 738 };
 739
 740 static const struct fd_perfcntr_countable vpc_countables[] = {
 741         COUNTABLE(PERF_VPC_BUSY_CYCLES, UINT64, AVERAGE),
 742         COUNTABLE(PERF_VPC_WORKING_CYCLES, UINT64, AVERAGE),
 743         COUNTABLE(PERF_VPC_STALL_CYCLES_UCHE, UINT64, AVERAGE),
 744         COUNTABLE(PERF_VPC_STALL_CYCLES_VFD_WACK, UINT64, AVERAGE),
 745         COUNTABLE(PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC, UINT64, AVERAGE),
 746         COUNTABLE(PERF_VPC_STALL_CYCLES_PC, UINT64, AVERAGE),
 747         COUNTABLE(PERF_VPC_STALL_CYCLES_SP_LM, UINT64, AVERAGE),
 748         COUNTABLE(PERF_VPC_STARVE_CYCLES_SP, UINT64, AVERAGE),
 749         COUNTABLE(PERF_VPC_STARVE_CYCLES_LRZ, UINT64, AVERAGE),
 750         COUNTABLE(PERF_VPC_PC_PRIMITIVES, UINT64, AVERAGE),
 751         COUNTABLE(PERF_VPC_SP_COMPONENTS, UINT64, AVERAGE),
 752         COUNTABLE(PERF_VPC_STALL_CYCLES_VPCRAM_POS, UINT64, AVERAGE),
 753         COUNTABLE(PERF_VPC_LRZ_ASSIGN_PRIMITIVES, UINT64, AVERAGE),
 754         COUNTABLE(PERF_VPC_RB_VISIBLE_PRIMITIVES, UINT64, AVERAGE),
 755         COUNTABLE(PERF_VPC_LM_TRANSACTION, UINT64, AVERAGE),
 756         COUNTABLE(PERF_VPC_STREAMOUT_TRANSACTION, UINT64, AVERAGE),
 757         COUNTABLE(PERF_VPC_VS_BUSY_CYCLES, UINT64, AVERAGE),
 758         COUNTABLE(PERF_VPC_PS_BUSY_CYCLES, UINT64, AVERAGE),
 759         COUNTABLE(PERF_VPC_VS_WORKING_CYCLES, UINT64, AVERAGE),
 760         COUNTABLE(PERF_VPC_PS_WORKING_CYCLES, UINT64, AVERAGE),
 761         COUNTABLE(PERF_VPC_STARVE_CYCLES_RB, UINT64, AVERAGE),
 762         COUNTABLE(PERF_VPC_NUM_VPCRAM_READ_POS, UINT64, AVERAGE),
 763         COUNTABLE(PERF_VPC_WIT_FULL_CYCLES, UINT64, AVERAGE),
 764         COUNTABLE(PERF_VPC_VPCRAM_FULL_CYCLES, UINT64, AVERAGE),
 765         COUNTABLE(PERF_VPC_LM_FULL_WAIT_FOR_INTP_END, UINT64, AVERAGE),
 766         COUNTABLE(PERF_VPC_NUM_VPCRAM_WRITE, UINT64, AVERAGE),
 767         COUNTABLE(PERF_VPC_NUM_VPCRAM_READ_SO, UINT64, AVERAGE),
 768         COUNTABLE(PERF_VPC_NUM_ATTR_REQ_LM, UINT64, AVERAGE),
 769 };
 770
 771 static const struct fd_perfcntr_counter vsc_counters[] = {
 772         COUNTER(VSC_PERFCTR_VSC_SEL_0, RBBM_PERFCTR_VSC_0_LO, RBBM_PERFCTR_VSC_0_HI),
 773         COUNTER(VSC_PERFCTR_VSC_SEL_1, RBBM_PERFCTR_VSC_1_LO, RBBM_PERFCTR_VSC_1_HI),
 774 };
 775
 776 static const struct fd_perfcntr_countable vsc_countables[] = {
 777         COUNTABLE(PERF_VSC_BUSY_CYCLES, UINT64, AVERAGE),
 778         COUNTABLE(PERF_VSC_WORKING_CYCLES, UINT64, AVERAGE),
 779         COUNTABLE(PERF_VSC_STALL_CYCLES_UCHE, UINT64, AVERAGE),
 780         COUNTABLE(PERF_VSC_EOT_NUM, UINT64, AVERAGE),
 781         COUNTABLE(PERF_VSC_INPUT_TILES, UINT64, AVERAGE),
 782 };
 783
 784 const struct fd_perfcntr_group a6xx_perfcntr_groups[] = {
 785         GROUP("CP", cp_counters, cp_countables),
 786         GROUP("CCU", ccu_counters, ccu_countables),
 787         GROUP("TSE", tse_counters, tse_countables),
 788         GROUP("RAS", ras_counters, ras_countables),
 789         GROUP("LRZ", lrz_counters, lrz_countables),
 790         GROUP("HLSQ", hlsq_counters, hlsq_countables),
 791         GROUP("PC", pc_counters, pc_countables),
 792         GROUP("RB", rb_counters, rb_countables),
 793         GROUP("RBBM", rbbm_counters, rbbm_countables),
 794         GROUP("SP", sp_counters, sp_countables),
 795         GROUP("TP", tp_counters, tp_countables),
 796         GROUP("UCHE", uche_counters, uche_countables),
 797         GROUP("VFD", vfd_counters, vfd_countables),
 798         GROUP("VPC", vpc_counters, vpc_countables),
 799         GROUP("VSC", vsc_counters, vsc_countables),
 800 //      GROUP("VBIF", vbif_counters, vbif_countables),
 801 };
 802
 803 const unsigned a6xx_num_perfcntr_groups = ARRAY_SIZE(a6xx_perfcntr_groups);
 804
 805 #endif /* FD5_PERFCNTR_H_ */