2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25 * Rob Clark <robclark@freedesktop.org>
28 #include "pipe/p_state.h"
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_inlines.h"
32 #include "util/u_format.h"
33 #include "util/bitset.h"
35 #include "freedreno_program.h"
37 #include "fd6_program.h"
39 #include "fd6_texture.h"
40 #include "fd6_format.h"
43 delete_shader_stateobj(struct fd6_shader_stateobj
*so
)
45 ir3_shader_destroy(so
->shader
);
49 static struct fd6_shader_stateobj
*
50 create_shader_stateobj(struct pipe_context
*pctx
, const struct pipe_shader_state
*cso
,
53 struct fd_context
*ctx
= fd_context(pctx
);
54 struct ir3_compiler
*compiler
= ctx
->screen
->compiler
;
55 struct fd6_shader_stateobj
*so
= CALLOC_STRUCT(fd6_shader_stateobj
);
56 so
->shader
= ir3_shader_create(compiler
, cso
, type
, &ctx
->debug
);
61 fd6_fp_state_create(struct pipe_context
*pctx
,
62 const struct pipe_shader_state
*cso
)
64 return create_shader_stateobj(pctx
, cso
, SHADER_FRAGMENT
);
68 fd6_fp_state_delete(struct pipe_context
*pctx
, void *hwcso
)
70 struct fd6_shader_stateobj
*so
= hwcso
;
71 delete_shader_stateobj(so
);
75 fd6_vp_state_create(struct pipe_context
*pctx
,
76 const struct pipe_shader_state
*cso
)
78 return create_shader_stateobj(pctx
, cso
, SHADER_VERTEX
);
82 fd6_vp_state_delete(struct pipe_context
*pctx
, void *hwcso
)
84 struct fd6_shader_stateobj
*so
= hwcso
;
85 delete_shader_stateobj(so
);
89 fd6_emit_shader(struct fd_ringbuffer
*ring
, const struct ir3_shader_variant
*so
)
91 const struct ir3_info
*si
= &so
->info
;
92 enum a6xx_state_block sb
= fd6_stage2shadersb(so
->type
);
93 enum a6xx_state_src src
;
97 if (fd_mesa_debug
& FD_DBG_DIRECT
) {
100 bin
= fd_bo_map(so
->bo
);
109 opcode
= CP_LOAD_STATE6_GEOM
;
111 case SHADER_FRAGMENT
:
113 opcode
= CP_LOAD_STATE6_FRAG
;
116 unreachable("bad shader type");
119 OUT_PKT7(ring
, opcode
, 3 + sz
);
120 OUT_RING(ring
, CP_LOAD_STATE6_0_DST_OFF(0) |
121 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER
) |
122 CP_LOAD_STATE6_0_STATE_SRC(src
) |
123 CP_LOAD_STATE6_0_STATE_BLOCK(sb
) |
124 CP_LOAD_STATE6_0_NUM_UNIT(so
->instrlen
));
126 OUT_RING(ring
, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
127 OUT_RING(ring
, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
129 OUT_RELOC(ring
, so
->bo
, 0, 0, 0);
132 /* for how clever coverity is, it is sometimes rather dull, and
133 * doesn't realize that the only case where bin==NULL, sz==0:
135 assume(bin
|| (sz
== 0));
137 for (i
= 0; i
< sz
; i
++) {
138 OUT_RING(ring
, bin
[i
]);
142 /* Add any missing varyings needed for stream-out. Otherwise varyings not
143 * used by fragment shader will be stripped out.
146 link_stream_out(struct ir3_shader_linkage
*l
, const struct ir3_shader_variant
*v
)
148 const struct pipe_stream_output_info
*strmout
= &v
->shader
->stream_output
;
151 * First, any stream-out varyings not already in linkage map (ie. also
152 * consumed by frag shader) need to be added:
154 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
155 const struct pipe_stream_output
*out
= &strmout
->output
[i
];
156 unsigned k
= out
->register_index
;
158 (1 << (out
->num_components
+ out
->start_component
)) - 1;
159 unsigned idx
, nextloc
= 0;
161 /* psize/pos need to be the last entries in linkage map, and will
162 * get added link_stream_out, so skip over them:
164 if ((v
->outputs
[k
].slot
== VARYING_SLOT_PSIZ
) ||
165 (v
->outputs
[k
].slot
== VARYING_SLOT_POS
))
168 for (idx
= 0; idx
< l
->cnt
; idx
++) {
169 if (l
->var
[idx
].regid
== v
->outputs
[k
].regid
)
171 nextloc
= MAX2(nextloc
, l
->var
[idx
].loc
+ 4);
174 /* add if not already in linkage map: */
176 ir3_link_add(l
, v
->outputs
[k
].regid
, compmask
, nextloc
);
178 /* expand component-mask if needed, ie streaming out all components
179 * but frag shader doesn't consume all components:
181 if (compmask
& ~l
->var
[idx
].compmask
) {
182 l
->var
[idx
].compmask
|= compmask
;
183 l
->max_loc
= MAX2(l
->max_loc
,
184 l
->var
[idx
].loc
+ util_last_bit(l
->var
[idx
].compmask
));
190 setup_stream_out(struct fd_context
*ctx
, const struct ir3_shader_variant
*v
,
191 struct ir3_shader_linkage
*l
)
193 const struct pipe_stream_output_info
*strmout
= &v
->shader
->stream_output
;
194 struct fd6_streamout_state
*tf
= &fd6_context(ctx
)->tf
;
196 memset(tf
, 0, sizeof(*tf
));
198 tf
->prog_count
= align(l
->max_loc
, 2) / 2;
200 debug_assert(tf
->prog_count
< ARRAY_SIZE(tf
->prog
));
202 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
203 const struct pipe_stream_output
*out
= &strmout
->output
[i
];
204 unsigned k
= out
->register_index
;
207 tf
->ncomp
[out
->output_buffer
] += out
->num_components
;
209 /* linkage map sorted by order frag shader wants things, so
210 * a bit less ideal here..
212 for (idx
= 0; idx
< l
->cnt
; idx
++)
213 if (l
->var
[idx
].regid
== v
->outputs
[k
].regid
)
216 debug_assert(idx
< l
->cnt
);
218 for (unsigned j
= 0; j
< out
->num_components
; j
++) {
219 unsigned c
= j
+ out
->start_component
;
220 unsigned loc
= l
->var
[idx
].loc
+ c
;
221 unsigned off
= j
+ out
->dst_offset
; /* in dwords */
224 tf
->prog
[loc
/2] |= A6XX_VPC_SO_PROG_B_EN
|
225 A6XX_VPC_SO_PROG_B_BUF(out
->output_buffer
) |
226 A6XX_VPC_SO_PROG_B_OFF(off
* 4);
228 tf
->prog
[loc
/2] |= A6XX_VPC_SO_PROG_A_EN
|
229 A6XX_VPC_SO_PROG_A_BUF(out
->output_buffer
) |
230 A6XX_VPC_SO_PROG_A_OFF(off
* 4);
235 tf
->vpc_so_buf_cntl
= A6XX_VPC_SO_BUF_CNTL_ENABLE
|
236 COND(tf
->ncomp
[0] > 0, A6XX_VPC_SO_BUF_CNTL_BUF0
) |
237 COND(tf
->ncomp
[1] > 0, A6XX_VPC_SO_BUF_CNTL_BUF1
) |
238 COND(tf
->ncomp
[2] > 0, A6XX_VPC_SO_BUF_CNTL_BUF2
) |
239 COND(tf
->ncomp
[3] > 0, A6XX_VPC_SO_BUF_CNTL_BUF3
);
243 const struct ir3_shader_variant
*v
;
244 const struct ir3_info
*i
;
245 /* const sizes are in units of 4 * vec4 */
248 /* instr sizes are in units of 16 instructions */
263 setup_stages(struct fd6_emit
*emit
, struct stage
*s
)
267 s
[VS
].v
= fd6_emit_get_vp(emit
);
268 s
[FS
].v
= fd6_emit_get_fp(emit
);
270 s
[HS
].v
= s
[DS
].v
= s
[GS
].v
= NULL
; /* for now */
272 for (i
= 0; i
< MAX_STAGES
; i
++) {
274 s
[i
].i
= &s
[i
].v
->info
;
275 s
[i
].constlen
= align(s
[i
].v
->constlen
, 4);
276 /* instrlen is already in units of 16 instr.. although
277 * probably we should ditch that and not make the compiler
278 * care about instruction group size of a3xx vs a5xx
280 s
[i
].instrlen
= s
[i
].v
->instrlen
;
288 unsigned constoff
= 0;
289 for (i
= 0; i
< MAX_STAGES
; i
++) {
290 s
[i
].constoff
= constoff
;
291 constoff
+= s
[i
].constlen
;
295 s
[FS
].instroff
= 64 - s
[FS
].instrlen
;
296 s
[HS
].instroff
= s
[DS
].instroff
= s
[GS
].instroff
= s
[FS
].instroff
;
300 fd6_program_emit(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
301 struct fd6_emit
*emit
)
303 struct stage s
[MAX_STAGES
];
304 uint32_t pos_regid
, psize_regid
, color_regid
[8];
305 uint32_t face_regid
, coord_regid
, zwcoord_regid
, samp_id_regid
, samp_mask_regid
;
306 uint32_t vcoord_regid
, vertex_regid
, instance_regid
;
307 enum a3xx_threadsize fssz
;
308 uint8_t psize_loc
= ~0;
311 setup_stages(emit
, s
);
315 pos_regid
= ir3_find_output_regid(s
[VS
].v
, VARYING_SLOT_POS
);
316 psize_regid
= ir3_find_output_regid(s
[VS
].v
, VARYING_SLOT_PSIZ
);
317 vertex_regid
= ir3_find_sysval_regid(s
[VS
].v
, SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
);
318 instance_regid
= ir3_find_sysval_regid(s
[VS
].v
, SYSTEM_VALUE_INSTANCE_ID
);
320 if (s
[FS
].v
->color0_mrt
) {
321 color_regid
[0] = color_regid
[1] = color_regid
[2] = color_regid
[3] =
322 color_regid
[4] = color_regid
[5] = color_regid
[6] = color_regid
[7] =
323 ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_COLOR
);
325 color_regid
[0] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA0
);
326 color_regid
[1] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA1
);
327 color_regid
[2] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA2
);
328 color_regid
[3] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA3
);
329 color_regid
[4] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA4
);
330 color_regid
[5] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA5
);
331 color_regid
[6] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA6
);
332 color_regid
[7] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA7
);
335 samp_id_regid
= ir3_find_sysval_regid(s
[FS
].v
, SYSTEM_VALUE_SAMPLE_ID
);
336 samp_mask_regid
= ir3_find_sysval_regid(s
[FS
].v
, SYSTEM_VALUE_SAMPLE_MASK_IN
);
337 face_regid
= ir3_find_sysval_regid(s
[FS
].v
, SYSTEM_VALUE_FRONT_FACE
);
338 coord_regid
= ir3_find_sysval_regid(s
[FS
].v
, SYSTEM_VALUE_FRAG_COORD
);
339 zwcoord_regid
= (coord_regid
== regid(63,0)) ? regid(63,0) : (coord_regid
+ 2);
340 vcoord_regid
= ir3_find_sysval_regid(s
[FS
].v
, SYSTEM_VALUE_VARYING_COORD
);
342 /* we could probably divide this up into things that need to be
343 * emitted if frag-prog is dirty vs if vert-prog is dirty..
346 OUT_PKT4(ring
, REG_A6XX_SP_VS_TEX_COUNT
, 1);
349 struct fd_texture_stateobj
*tex
= &ctx
->tex
[PIPE_SHADER_VERTEX
];
350 OUT_PKT4(ring
, REG_A6XX_SP_VS_CONFIG
, 2);
351 OUT_RING(ring
, COND(s
[VS
].v
, A6XX_SP_VS_CONFIG_ENABLED
) |
352 A6XX_SP_VS_CONFIG_NTEX(tex
->num_textures
) |
353 A6XX_SP_VS_CONFIG_NSAMP(tex
->num_samplers
)); /* SP_VS_CONFIG */
354 OUT_RING(ring
, s
[VS
].instrlen
); /* SP_VS_INSTRLEN */
356 OUT_PKT4(ring
, REG_A6XX_SP_HS_UNKNOWN_A831
, 1);
359 OUT_PKT4(ring
, REG_A6XX_SP_HS_CONFIG
, 2);
360 OUT_RING(ring
, COND(s
[HS
].v
, A6XX_SP_HS_CONFIG_ENABLED
)); /* SP_HS_CONFIG */
361 OUT_RING(ring
, s
[HS
].instrlen
); /* SP_HS_INSTRLEN */
363 OUT_PKT4(ring
, REG_A6XX_SP_DS_CONFIG
, 2);
364 OUT_RING(ring
, COND(s
[DS
].v
, A6XX_SP_DS_CONFIG_ENABLED
)); /* SP_DS_CONFIG */
365 OUT_RING(ring
, s
[DS
].instrlen
); /* SP_DS_INSTRLEN */
367 OUT_PKT4(ring
, REG_A6XX_SP_GS_UNKNOWN_A871
, 1);
370 OUT_PKT4(ring
, REG_A6XX_SP_GS_CONFIG
, 2);
371 OUT_RING(ring
, COND(s
[GS
].v
, A6XX_SP_GS_CONFIG_ENABLED
)); /* SP_GS_CONFIG */
372 OUT_RING(ring
, s
[GS
].instrlen
); /* SP_GS_INSTRLEN */
374 OUT_PKT4(ring
, REG_A6XX_SP_UNKNOWN_A99E
, 1);
375 OUT_RING(ring
, 0x7fc0);
377 OUT_PKT4(ring
, REG_A6XX_SP_UNKNOWN_A9A8
, 1);
380 OUT_PKT4(ring
, REG_A6XX_SP_UNKNOWN_AB00
, 1);
383 tex
= &ctx
->tex
[PIPE_SHADER_FRAGMENT
];
384 OUT_PKT4(ring
, REG_A6XX_SP_FS_CONFIG
, 2);
385 OUT_RING(ring
, COND(s
[FS
].v
, A6XX_SP_FS_CONFIG_ENABLED
) |
386 A6XX_SP_FS_CONFIG_NTEX(tex
->num_textures
) |
387 A6XX_SP_FS_CONFIG_NSAMP(tex
->num_samplers
));
389 OUT_RING(ring
, s
[FS
].instrlen
); /* SP_FS_INSTRLEN */
391 OUT_PKT4(ring
, REG_A6XX_HLSQ_VS_CNTL
, 4);
392 OUT_RING(ring
, A6XX_HLSQ_VS_CNTL_CONSTLEN(s
[VS
].constlen
) | 0x100); /* HLSQ_VS_CONSTLEN */
393 OUT_RING(ring
, A6XX_HLSQ_HS_CNTL_CONSTLEN(s
[HS
].constlen
)); /* HLSQ_HS_CONSTLEN */
394 OUT_RING(ring
, A6XX_HLSQ_DS_CNTL_CONSTLEN(s
[DS
].constlen
)); /* HLSQ_DS_CONSTLEN */
395 OUT_RING(ring
, A6XX_HLSQ_GS_CNTL_CONSTLEN(s
[GS
].constlen
)); /* HLSQ_GS_CONSTLEN */
397 OUT_PKT4(ring
, REG_A6XX_HLSQ_FS_CNTL
, 1);
398 OUT_RING(ring
, A6XX_HLSQ_VS_CNTL_CONSTLEN(s
[FS
].constlen
) | 0x100); /* HLSQ_FS_CONSTLEN */
400 OUT_PKT4(ring
, REG_A6XX_SP_VS_CTRL_REG0
, 1);
401 OUT_RING(ring
, A6XX_SP_VS_CTRL_REG0_THREADSIZE(fssz
) |
402 A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(s
[VS
].i
->max_reg
+ 1) |
403 A6XX_SP_VS_CTRL_REG0_MERGEDREGS
|
404 A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(0x3) | // XXX need to figure this out somehow..
405 COND(s
[VS
].v
->has_samp
, A6XX_SP_VS_CTRL_REG0_PIXLODENABLE
));
407 struct ir3_shader_linkage l
= {0};
408 ir3_link_shaders(&l
, s
[VS
].v
, s
[FS
].v
);
410 if ((s
[VS
].v
->shader
->stream_output
.num_outputs
> 0) &&
411 !emit
->key
.binning_pass
)
412 link_stream_out(&l
, s
[VS
].v
);
414 BITSET_DECLARE(varbs
, 128) = {0};
415 uint32_t *varmask
= (uint32_t *)varbs
;
417 for (i
= 0; i
< l
.cnt
; i
++)
418 for (j
= 0; j
< util_last_bit(l
.var
[i
].compmask
); j
++)
419 BITSET_SET(varbs
, l
.var
[i
].loc
+ j
);
421 OUT_PKT4(ring
, REG_A6XX_VPC_VAR_DISABLE(0), 4);
422 OUT_RING(ring
, ~varmask
[0]); /* VPC_VAR[0].DISABLE */
423 OUT_RING(ring
, ~varmask
[1]); /* VPC_VAR[1].DISABLE */
424 OUT_RING(ring
, ~varmask
[2]); /* VPC_VAR[2].DISABLE */
425 OUT_RING(ring
, ~varmask
[3]); /* VPC_VAR[3].DISABLE */
427 /* a6xx appends pos/psize to end of the linkage map: */
428 if (pos_regid
!= regid(63,0))
429 ir3_link_add(&l
, pos_regid
, 0xf, l
.max_loc
);
431 if (psize_regid
!= regid(63,0)) {
432 psize_loc
= l
.max_loc
;
433 ir3_link_add(&l
, psize_regid
, 0x1, l
.max_loc
);
436 if ((s
[VS
].v
->shader
->stream_output
.num_outputs
> 0) &&
437 !emit
->key
.binning_pass
) {
438 setup_stream_out(ctx
, s
[VS
].v
, &l
);
441 for (i
= 0, j
= 0; (i
< 16) && (j
< l
.cnt
); i
++) {
444 OUT_PKT4(ring
, REG_A6XX_SP_VS_OUT_REG(i
), 1);
446 reg
|= A6XX_SP_VS_OUT_REG_A_REGID(l
.var
[j
].regid
);
447 reg
|= A6XX_SP_VS_OUT_REG_A_COMPMASK(l
.var
[j
].compmask
);
450 reg
|= A6XX_SP_VS_OUT_REG_B_REGID(l
.var
[j
].regid
);
451 reg
|= A6XX_SP_VS_OUT_REG_B_COMPMASK(l
.var
[j
].compmask
);
457 for (i
= 0, j
= 0; (i
< 8) && (j
< l
.cnt
); i
++) {
460 OUT_PKT4(ring
, REG_A6XX_SP_VS_VPC_DST_REG(i
), 1);
462 reg
|= A6XX_SP_VS_VPC_DST_REG_OUTLOC0(l
.var
[j
++].loc
);
463 reg
|= A6XX_SP_VS_VPC_DST_REG_OUTLOC1(l
.var
[j
++].loc
);
464 reg
|= A6XX_SP_VS_VPC_DST_REG_OUTLOC2(l
.var
[j
++].loc
);
465 reg
|= A6XX_SP_VS_VPC_DST_REG_OUTLOC3(l
.var
[j
++].loc
);
470 OUT_PKT4(ring
, REG_A6XX_SP_VS_OBJ_START_LO
, 2);
471 OUT_RELOC(ring
, s
[VS
].v
->bo
, 0, 0, 0); /* SP_VS_OBJ_START_LO/HI */
474 fd6_emit_shader(ring
, s
[VS
].v
);
476 // TODO depending on other bits in this reg (if any) set somewhere else?
478 OUT_PKT4(ring
, REG_A6XX_PC_PRIM_VTX_CNTL
, 1);
479 OUT_RING(ring
, COND(s
[VS
].v
->writes_psize
, A6XX_PC_PRIM_VTX_CNTL_PSIZE
));
482 OUT_PKT4(ring
, REG_A6XX_SP_PRIMITIVE_CNTL
, 1);
483 OUT_RING(ring
, A6XX_SP_PRIMITIVE_CNTL_VSOUT(l
.cnt
));
485 bool enable_varyings
= s
[FS
].v
->total_in
> 0;
487 OUT_PKT4(ring
, REG_A6XX_VPC_CNTL_0
, 1);
488 OUT_RING(ring
, A6XX_VPC_CNTL_0_NUMNONPOSVAR(s
[FS
].v
->total_in
) |
489 COND(enable_varyings
, A6XX_VPC_CNTL_0_VARYING
) |
492 OUT_PKT4(ring
, REG_A6XX_PC_PRIMITIVE_CNTL_1
, 1);
493 OUT_RING(ring
, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(l
.max_loc
) |
494 COND(psize_regid
!= regid(63,0), 0x100));
496 if (emit
->key
.binning_pass
) {
497 OUT_PKT4(ring
, REG_A6XX_SP_FS_OBJ_START_LO
, 2);
498 OUT_RING(ring
, 0x00000000); /* SP_FS_OBJ_START_LO */
499 OUT_RING(ring
, 0x00000000); /* SP_FS_OBJ_START_HI */
501 OUT_PKT4(ring
, REG_A6XX_SP_FS_OBJ_START_LO
, 2);
502 OUT_RELOC(ring
, s
[FS
].v
->bo
, 0, 0, 0); /* SP_FS_OBJ_START_LO/HI */
505 OUT_PKT4(ring
, REG_A6XX_HLSQ_CONTROL_1_REG
, 5);
506 OUT_RING(ring
, 0x7); /* XXX */
507 OUT_RING(ring
, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid
) |
508 A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid
) |
509 A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(samp_mask_regid
) |
510 0xfc000000); /* XXX */
511 OUT_RING(ring
, A6XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID(vcoord_regid
) |
512 0xfcfcfc00); /* XXX */
513 OUT_RING(ring
, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid
) |
514 A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid
) |
515 0x0000fcfc); /* XXX */
516 OUT_RING(ring
, 0xfc); /* XXX */
518 OUT_PKT4(ring
, REG_A6XX_HLSQ_UNKNOWN_B980
, 1);
519 OUT_RING(ring
, s
[FS
].v
->total_in
> 0 ? 3 : 1);
521 OUT_PKT4(ring
, REG_A6XX_SP_FS_CTRL_REG0
, 1);
522 OUT_RING(ring
, A6XX_SP_FS_CTRL_REG0_THREADSIZE(fssz
) |
523 COND(s
[FS
].v
->total_in
> 0, A6XX_SP_FS_CTRL_REG0_VARYING
) |
524 COND(s
[FS
].v
->frag_coord
, A6XX_SP_FS_CTRL_REG0_VARYING
) |
526 A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(s
[FS
].i
->max_reg
+ 1) |
527 A6XX_SP_FS_CTRL_REG0_MERGEDREGS
|
528 A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(0x3) | // XXX need to figure this out somehow..
529 COND(s
[FS
].v
->has_samp
, A6XX_SP_FS_CTRL_REG0_PIXLODENABLE
));
531 OUT_PKT4(ring
, REG_A6XX_SP_UNKNOWN_A982
, 1);
532 OUT_RING(ring
, 0); /* XXX */
534 OUT_PKT4(ring
, REG_A6XX_HLSQ_UPDATE_CNTL
, 1);
535 OUT_RING(ring
, 0xff); /* XXX */
537 OUT_PKT4(ring
, REG_A6XX_VPC_GS_SIV_CNTL
, 1);
538 OUT_RING(ring
, 0x0000ffff); /* XXX */
541 OUT_PKT4(ring
, REG_A6XX_SP_SP_CNTL
, 1);
542 OUT_RING(ring
, 0x00000010); /* XXX */
545 OUT_PKT4(ring
, REG_A6XX_GRAS_CNTL
, 1);
546 OUT_RING(ring
, COND(enable_varyings
, A6XX_GRAS_CNTL_VARYING
) |
547 COND(s
[FS
].v
->frag_coord
,
548 A6XX_GRAS_CNTL_UNK3
|
549 A6XX_GRAS_CNTL_XCOORD
|
550 A6XX_GRAS_CNTL_YCOORD
|
551 A6XX_GRAS_CNTL_ZCOORD
|
552 A6XX_GRAS_CNTL_WCOORD
));
554 OUT_PKT4(ring
, REG_A6XX_RB_RENDER_CONTROL0
, 2);
555 OUT_RING(ring
, COND(enable_varyings
, A6XX_RB_RENDER_CONTROL0_VARYING
|
556 A6XX_RB_RENDER_CONTROL0_UNK10
) |
557 COND(s
[FS
].v
->frag_coord
,
558 A6XX_RB_RENDER_CONTROL0_UNK3
|
559 A6XX_RB_RENDER_CONTROL0_XCOORD
|
560 A6XX_RB_RENDER_CONTROL0_YCOORD
|
561 A6XX_RB_RENDER_CONTROL0_ZCOORD
|
562 A6XX_RB_RENDER_CONTROL0_WCOORD
));
563 OUT_RING(ring
, COND(s
[FS
].v
->frag_face
, A6XX_RB_RENDER_CONTROL1_FACENESS
));
565 OUT_PKT4(ring
, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
566 for (i
= 0; i
< 8; i
++) {
567 OUT_RING(ring
, A6XX_SP_FS_OUTPUT_REG_REGID(color_regid
[i
]) |
568 COND(emit
->key
.half_precision
,
569 A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION
));
572 OUT_PKT4(ring
, REG_A6XX_VPC_PACK
, 1);
573 OUT_RING(ring
, A6XX_VPC_PACK_NUMNONPOSVAR(s
[FS
].v
->total_in
) |
574 A6XX_VPC_PACK_PSIZELOC(psize_loc
) |
575 A6XX_VPC_PACK_STRIDE_IN_VPC(l
.max_loc
));
577 if (!emit
->key
.binning_pass
) {
578 uint32_t vinterp
[8], vpsrepl
[8];
580 memset(vinterp
, 0, sizeof(vinterp
));
581 memset(vpsrepl
, 0, sizeof(vpsrepl
));
583 /* looks like we need to do int varyings in the frag
584 * shader on a5xx (no flatshad reg? or a420.0 bug?):
587 * (sy)ldlv.u32 r0.x,l[r0.x], 1
588 * ldlv.u32 r0.y,l[r0.x+1], 1
589 * (ss)bary.f (ei)r63.x, 0, r0.x
590 * (ss)(rpt1)cov.s32f16 hr0.x, (r)r0.x
592 * sam (f16)(xyzw)hr0.x, hr0.x, s#0, t#0
594 * Possibly on later a5xx variants we'll be able to use
595 * something like the code below instead of workaround
598 /* figure out VARYING_INTERP / VARYING_PS_REPL register values: */
599 for (j
= -1; (j
= ir3_next_varying(s
[FS
].v
, j
)) < (int)s
[FS
].v
->inputs_count
; ) {
600 /* NOTE: varyings are packed, so if compmask is 0xb
601 * then first, third, and fourth component occupy
602 * three consecutive varying slots:
604 unsigned compmask
= s
[FS
].v
->inputs
[j
].compmask
;
606 uint32_t inloc
= s
[FS
].v
->inputs
[j
].inloc
;
608 if ((s
[FS
].v
->inputs
[j
].interpolate
== INTERP_MODE_FLAT
) ||
609 (s
[FS
].v
->inputs
[j
].rasterflat
&& emit
->rasterflat
)) {
610 uint32_t loc
= inloc
;
612 for (i
= 0; i
< 4; i
++) {
613 if (compmask
& (1 << i
)) {
614 vinterp
[loc
/ 16] |= 1 << ((loc
% 16) * 2);
615 //flatshade[loc / 32] |= 1 << (loc % 32);
621 gl_varying_slot slot
= s
[FS
].v
->inputs
[j
].slot
;
623 /* since we don't enable PIPE_CAP_TGSI_TEXCOORD: */
624 if (slot
>= VARYING_SLOT_VAR0
) {
625 unsigned texmask
= 1 << (slot
- VARYING_SLOT_VAR0
);
626 /* Replace the .xy coordinates with S/T from the point sprite. Set
627 * interpolation bits for .zw such that they become .01
629 if (emit
->sprite_coord_enable
& texmask
) {
630 /* mask is two 2-bit fields, where:
633 * '11' -> 1 - T (flip mode)
635 unsigned mask
= emit
->sprite_coord_mode
? 0b1101 : 0b1001;
636 uint32_t loc
= inloc
;
637 if (compmask
& 0x1) {
638 vpsrepl
[loc
/ 16] |= ((mask
>> 0) & 0x3) << ((loc
% 16) * 2);
641 if (compmask
& 0x2) {
642 vpsrepl
[loc
/ 16] |= ((mask
>> 2) & 0x3) << ((loc
% 16) * 2);
645 if (compmask
& 0x4) {
647 vinterp
[loc
/ 16] |= 0b10 << ((loc
% 16) * 2);
650 if (compmask
& 0x8) {
652 vinterp
[loc
/ 16] |= 0b11 << ((loc
% 16) * 2);
659 OUT_PKT4(ring
, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
660 for (i
= 0; i
< 8; i
++)
661 OUT_RING(ring
, vinterp
[i
]); /* VPC_VARYING_INTERP[i].MODE */
663 OUT_PKT4(ring
, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
664 for (i
= 0; i
< 8; i
++)
665 OUT_RING(ring
, vpsrepl
[i
]); /* VPC_VARYING_PS_REPL[i] */
668 if (!emit
->key
.binning_pass
)
670 fd6_emit_shader(ring
, s
[FS
].v
);
672 OUT_PKT4(ring
, REG_A6XX_VFD_CONTROL_1
, 6);
673 OUT_RING(ring
, A6XX_VFD_CONTROL_1_REGID4VTX(vertex_regid
) |
674 A6XX_VFD_CONTROL_1_REGID4INST(instance_regid
) |
676 OUT_RING(ring
, 0x0000fcfc); /* VFD_CONTROL_2 */
677 OUT_RING(ring
, 0xfcfcfcfc); /* VFD_CONTROL_3 */
678 OUT_RING(ring
, 0x000000fc); /* VFD_CONTROL_4 */
679 OUT_RING(ring
, 0x0000fcfc); /* VFD_CONTROL_5 */
680 OUT_RING(ring
, 0x00000000); /* VFD_CONTROL_6 */
684 fd6_prog_init(struct pipe_context
*pctx
)
686 pctx
->create_fs_state
= fd6_fp_state_create
;
687 pctx
->delete_fs_state
= fd6_fp_state_delete
;
689 pctx
->create_vs_state
= fd6_vp_state_create
;
690 pctx
->delete_vs_state
= fd6_vp_state_delete
;