projects / mesa.git / blob
? search:


9e12cb246c9314937fd896ec8ec40031f31fff51
[mesa.git] / src / gallium / drivers / freedreno / a6xx / fd6_program.c
1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 * Authors:
25 * Rob Clark <robclark@freedesktop.org>
26 */
27
28 #include "pipe/p_state.h"
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_inlines.h"
32 #include "util/format/u_format.h"
33 #include "util/bitset.h"
34
35 #include "freedreno_program.h"
36
37 #include "fd6_program.h"
38 #include "fd6_emit.h"
39 #include "fd6_texture.h"
40 #include "fd6_format.h"
41
42 void
43 fd6_emit_shader(struct fd_ringbuffer *ring, const struct ir3_shader_variant *so)
44 {
45 enum a6xx_state_block sb = fd6_stage2shadersb(so->type);
46
47 uint32_t obj_start;
48 uint32_t instrlen;
49
50 switch (so->type) {
51 case MESA_SHADER_VERTEX:
52 obj_start = REG_A6XX_SP_VS_OBJ_START_LO;
53 instrlen = REG_A6XX_SP_VS_INSTRLEN;
54 break;
55 case MESA_SHADER_TESS_CTRL:
56 obj_start = REG_A6XX_SP_HS_OBJ_START_LO;
57 instrlen = REG_A6XX_SP_HS_INSTRLEN;
58 break;
59 case MESA_SHADER_TESS_EVAL:
60 obj_start = REG_A6XX_SP_DS_OBJ_START_LO;
61 instrlen = REG_A6XX_SP_DS_INSTRLEN;
62 break;
63 case MESA_SHADER_GEOMETRY:
64 obj_start = REG_A6XX_SP_GS_OBJ_START_LO;
65 instrlen = REG_A6XX_SP_GS_INSTRLEN;
66 break;
67 case MESA_SHADER_FRAGMENT:
68 obj_start = REG_A6XX_SP_FS_OBJ_START_LO;
69 instrlen = REG_A6XX_SP_FS_INSTRLEN;
70 break;
71 case MESA_SHADER_COMPUTE:
72 case MESA_SHADER_KERNEL:
73 obj_start = REG_A6XX_SP_CS_OBJ_START_LO;
74 instrlen = REG_A6XX_SP_CS_INSTRLEN;
75 break;
76 case MESA_SHADER_NONE:
77 unreachable("");
78 }
79
80 OUT_PKT4(ring, instrlen, 1);
81 OUT_RING(ring, so->instrlen);
82
83 OUT_PKT4(ring, obj_start, 2);
84 OUT_RELOC(ring, so->bo, 0, 0, 0);
85
86 OUT_PKT7(ring, fd6_stage2opcode(so->type), 3);
87 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
88 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
89 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
90 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
91 CP_LOAD_STATE6_0_NUM_UNIT(so->instrlen));
92 OUT_RELOCD(ring, so->bo, 0, 0, 0);
93 }
94
95 /* Add any missing varyings needed for stream-out. Otherwise varyings not
96 * used by fragment shader will be stripped out.
97 */
98 static void
99 link_stream_out(struct ir3_shader_linkage *l, const struct ir3_shader_variant *v)
100 {
101 const struct ir3_stream_output_info *strmout = &v->shader->stream_output;
102
103 /*
104 * First, any stream-out varyings not already in linkage map (ie. also
105 * consumed by frag shader) need to be added:
106 */
107 for (unsigned i = 0; i < strmout->num_outputs; i++) {
108 const struct ir3_stream_output *out = &strmout->output[i];
109 unsigned k = out->register_index;
110 unsigned compmask =
111 (1 << (out->num_components + out->start_component)) - 1;
112 unsigned idx, nextloc = 0;
113
114 /* psize/pos need to be the last entries in linkage map, and will
115 * get added link_stream_out, so skip over them:
116 */
117 if ((v->outputs[k].slot == VARYING_SLOT_PSIZ) ||
118 (v->outputs[k].slot == VARYING_SLOT_POS))
119 continue;
120
121 for (idx = 0; idx < l->cnt; idx++) {
122 if (l->var[idx].regid == v->outputs[k].regid)
123 break;
124 nextloc = MAX2(nextloc, l->var[idx].loc + 4);
125 }
126
127 /* add if not already in linkage map: */
128 if (idx == l->cnt)
129 ir3_link_add(l, v->outputs[k].regid, compmask, nextloc);
130
131 /* expand component-mask if needed, ie streaming out all components
132 * but frag shader doesn't consume all components:
133 */
134 if (compmask & ~l->var[idx].compmask) {
135 l->var[idx].compmask |= compmask;
136 l->max_loc = MAX2(l->max_loc,
137 l->var[idx].loc + util_last_bit(l->var[idx].compmask));
138 }
139 }
140 }
141
142 static void
143 setup_stream_out(struct fd6_program_state *state, const struct ir3_shader_variant *v,
144 struct ir3_shader_linkage *l)
145 {
146 const struct ir3_stream_output_info *strmout = &v->shader->stream_output;
147 struct fd6_streamout_state *tf = &state->tf;
148
149 memset(tf, 0, sizeof(*tf));
150
151 tf->prog_count = align(l->max_loc, 2) / 2;
152
153 debug_assert(tf->prog_count < ARRAY_SIZE(tf->prog));
154
155 for (unsigned i = 0; i < strmout->num_outputs; i++) {
156 const struct ir3_stream_output *out = &strmout->output[i];
157 unsigned k = out->register_index;
158 unsigned idx;
159
160 tf->ncomp[out->output_buffer] += out->num_components;
161
162 /* linkage map sorted by order frag shader wants things, so
163 * a bit less ideal here..
164 */
165 for (idx = 0; idx < l->cnt; idx++)
166 if (l->var[idx].regid == v->outputs[k].regid)
167 break;
168
169 debug_assert(idx < l->cnt);
170
171 for (unsigned j = 0; j < out->num_components; j++) {
172 unsigned c = j + out->start_component;
173 unsigned loc = l->var[idx].loc + c;
174 unsigned off = j + out->dst_offset; /* in dwords */
175
176 if (loc & 1) {
177 tf->prog[loc/2] |= A6XX_VPC_SO_PROG_B_EN |
178 A6XX_VPC_SO_PROG_B_BUF(out->output_buffer) |
179 A6XX_VPC_SO_PROG_B_OFF(off * 4);
180 } else {
181 tf->prog[loc/2] |= A6XX_VPC_SO_PROG_A_EN |
182 A6XX_VPC_SO_PROG_A_BUF(out->output_buffer) |
183 A6XX_VPC_SO_PROG_A_OFF(off * 4);
184 }
185 }
186 }
187
188 tf->vpc_so_buf_cntl = A6XX_VPC_SO_BUF_CNTL_ENABLE |
189 COND(tf->ncomp[0] > 0, A6XX_VPC_SO_BUF_CNTL_BUF0) |
190 COND(tf->ncomp[1] > 0, A6XX_VPC_SO_BUF_CNTL_BUF1) |
191 COND(tf->ncomp[2] > 0, A6XX_VPC_SO_BUF_CNTL_BUF2) |
192 COND(tf->ncomp[3] > 0, A6XX_VPC_SO_BUF_CNTL_BUF3);
193 }
194
195 static void
196 setup_config_stateobj(struct fd_ringbuffer *ring, struct fd6_program_state *state)
197 {
198 OUT_PKT4(ring, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
199 OUT_RING(ring, 0xff); /* XXX */
200
201 if (state->ds)
202 debug_assert(state->ds->constlen >= state->bs->constlen);
203 else
204 debug_assert(state->vs->constlen >= state->bs->constlen);
205
206 OUT_PKT4(ring, REG_A6XX_HLSQ_VS_CNTL, 4);
207 OUT_RING(ring, A6XX_HLSQ_VS_CNTL_CONSTLEN(align(state->vs->constlen, 4)) |
208 A6XX_HLSQ_VS_CNTL_ENABLED);
209 OUT_RING(ring, COND(state->hs,
210 A6XX_HLSQ_HS_CNTL_ENABLED |
211 A6XX_HLSQ_HS_CNTL_CONSTLEN(align(state->hs->constlen, 4))));
212 OUT_RING(ring, COND(state->ds,
213 A6XX_HLSQ_DS_CNTL_ENABLED |
214 A6XX_HLSQ_DS_CNTL_CONSTLEN(align(state->ds->constlen, 4))));
215 OUT_RING(ring, COND(state->gs,
216 A6XX_HLSQ_GS_CNTL_ENABLED |
217 A6XX_HLSQ_GS_CNTL_CONSTLEN(align(state->gs->constlen, 4))));
218 OUT_PKT4(ring, REG_A6XX_HLSQ_FS_CNTL, 1);
219 OUT_RING(ring, A6XX_HLSQ_FS_CNTL_CONSTLEN(align(state->fs->constlen, 4)) |
220 A6XX_HLSQ_FS_CNTL_ENABLED);
221
222 OUT_PKT4(ring, REG_A6XX_SP_VS_CONFIG, 1);
223 OUT_RING(ring, COND(state->vs, A6XX_SP_VS_CONFIG_ENABLED) |
224 A6XX_SP_VS_CONFIG_NIBO(ir3_shader_nibo(state->vs)) |
225 A6XX_SP_VS_CONFIG_NTEX(state->vs->num_samp) |
226 A6XX_SP_VS_CONFIG_NSAMP(state->vs->num_samp));
227
228 OUT_PKT4(ring, REG_A6XX_SP_HS_CONFIG, 1);
229 OUT_RING(ring, COND(state->hs,
230 A6XX_SP_HS_CONFIG_ENABLED |
231 A6XX_SP_HS_CONFIG_NIBO(ir3_shader_nibo(state->hs)) |
232 A6XX_SP_HS_CONFIG_NTEX(state->hs->num_samp) |
233 A6XX_SP_HS_CONFIG_NSAMP(state->hs->num_samp)));
234
235 OUT_PKT4(ring, REG_A6XX_SP_DS_CONFIG, 1);
236 OUT_RING(ring, COND(state->ds,
237 A6XX_SP_DS_CONFIG_ENABLED |
238 A6XX_SP_DS_CONFIG_NIBO(ir3_shader_nibo(state->ds)) |
239 A6XX_SP_DS_CONFIG_NTEX(state->ds->num_samp) |
240 A6XX_SP_DS_CONFIG_NSAMP(state->ds->num_samp)));
241
242 OUT_PKT4(ring, REG_A6XX_SP_GS_CONFIG, 1);
243 OUT_RING(ring, COND(state->gs,
244 A6XX_SP_GS_CONFIG_ENABLED |
245 A6XX_SP_GS_CONFIG_NIBO(ir3_shader_nibo(state->gs)) |
246 A6XX_SP_GS_CONFIG_NTEX(state->gs->num_samp) |
247 A6XX_SP_GS_CONFIG_NSAMP(state->gs->num_samp)));
248
249 OUT_PKT4(ring, REG_A6XX_SP_FS_CONFIG, 1);
250 OUT_RING(ring, COND(state->fs, A6XX_SP_FS_CONFIG_ENABLED) |
251 A6XX_SP_FS_CONFIG_NIBO(ir3_shader_nibo(state->fs)) |
252 A6XX_SP_FS_CONFIG_NTEX(state->fs->num_samp) |
253 A6XX_SP_FS_CONFIG_NSAMP(state->fs->num_samp));
254
255 OUT_PKT4(ring, REG_A6XX_SP_IBO_COUNT, 1);
256 OUT_RING(ring, ir3_shader_nibo(state->fs));
257 }
258
259 static inline uint32_t
260 next_regid(uint32_t reg, uint32_t increment)
261 {
262 if (VALIDREG(reg))
263 return reg + increment;
264 else
265 return regid(63,0);
266 }
267
268 static void
269 setup_stateobj(struct fd_ringbuffer *ring, struct fd_screen *screen,
270 struct fd6_program_state *state, const struct ir3_shader_key *key,
271 bool binning_pass)
272 {
273 uint32_t pos_regid, psize_regid, color_regid[8], posz_regid;
274 uint32_t face_regid, coord_regid, zwcoord_regid, samp_id_regid;
275 uint32_t smask_in_regid, smask_regid;
276 uint32_t vertex_regid, instance_regid, layer_regid, primitive_regid;
277 uint32_t hs_invocation_regid;
278 uint32_t tess_coord_x_regid, tess_coord_y_regid, hs_patch_regid, ds_patch_regid;
279 uint32_t ij_pix_regid, ij_samp_regid, ij_cent_regid, ij_size_regid;
280 uint32_t gs_header_regid;
281 enum a3xx_threadsize fssz;
282 uint8_t psize_loc = ~0, pos_loc = ~0, layer_loc = ~0;
283 int i, j;
284
285 static const struct ir3_shader_variant dummy_fs = {0};
286 const struct ir3_shader_variant *vs = binning_pass ? state->bs : state->vs;
287 const struct ir3_shader_variant *hs = state->hs;
288 const struct ir3_shader_variant *ds = state->ds;
289 const struct ir3_shader_variant *gs = state->gs;
290 const struct ir3_shader_variant *fs = binning_pass ? &dummy_fs : state->fs;
291
292 if (binning_pass && state->ds)
293 ds = state->bs;
294 else if (binning_pass)
295 vs = state->bs;
296
297 bool sample_shading = fs->per_samp | key->sample_shading;
298
299 fssz = FOUR_QUADS;
300
301 pos_regid = ir3_find_output_regid(vs, VARYING_SLOT_POS);
302 psize_regid = ir3_find_output_regid(vs, VARYING_SLOT_PSIZ);
303 vertex_regid = ir3_find_sysval_regid(vs, SYSTEM_VALUE_VERTEX_ID);
304 instance_regid = ir3_find_sysval_regid(vs, SYSTEM_VALUE_INSTANCE_ID);
305
306 if (hs) {
307 tess_coord_x_regid = ir3_find_sysval_regid(ds, SYSTEM_VALUE_TESS_COORD);
308 tess_coord_y_regid = next_regid(tess_coord_x_regid, 1);
309 hs_patch_regid = ir3_find_sysval_regid(hs, SYSTEM_VALUE_PRIMITIVE_ID);
310 ds_patch_regid = ir3_find_sysval_regid(ds, SYSTEM_VALUE_PRIMITIVE_ID);
311 hs_invocation_regid = ir3_find_sysval_regid(hs, SYSTEM_VALUE_TCS_HEADER_IR3);
312
313 pos_regid = ir3_find_output_regid(ds, VARYING_SLOT_POS);
314 psize_regid = ir3_find_output_regid(ds, VARYING_SLOT_PSIZ);
315 } else {
316 tess_coord_x_regid = regid(63, 0);
317 tess_coord_y_regid = regid(63, 0);
318 hs_patch_regid = regid(63, 0);
319 ds_patch_regid = regid(63, 0);
320 hs_invocation_regid = regid(63, 0);
321 }
322
323 if (gs) {
324 gs_header_regid = ir3_find_sysval_regid(gs, SYSTEM_VALUE_GS_HEADER_IR3);
325 primitive_regid = ir3_find_sysval_regid(gs, SYSTEM_VALUE_PRIMITIVE_ID);
326 pos_regid = ir3_find_output_regid(gs, VARYING_SLOT_POS);
327 psize_regid = ir3_find_output_regid(gs, VARYING_SLOT_PSIZ);
328 layer_regid = ir3_find_output_regid(gs, VARYING_SLOT_LAYER);
329 } else {
330 gs_header_regid = regid(63, 0);
331 primitive_regid = regid(63, 0);
332 layer_regid = regid(63, 0);
333 }
334
335 if (fs->color0_mrt) {
336 color_regid[0] = color_regid[1] = color_regid[2] = color_regid[3] =
337 color_regid[4] = color_regid[5] = color_regid[6] = color_regid[7] =
338 ir3_find_output_regid(fs, FRAG_RESULT_COLOR);
339 } else {
340 color_regid[0] = ir3_find_output_regid(fs, FRAG_RESULT_DATA0);
341 color_regid[1] = ir3_find_output_regid(fs, FRAG_RESULT_DATA1);
342 color_regid[2] = ir3_find_output_regid(fs, FRAG_RESULT_DATA2);
343 color_regid[3] = ir3_find_output_regid(fs, FRAG_RESULT_DATA3);
344 color_regid[4] = ir3_find_output_regid(fs, FRAG_RESULT_DATA4);
345 color_regid[5] = ir3_find_output_regid(fs, FRAG_RESULT_DATA5);
346 color_regid[6] = ir3_find_output_regid(fs, FRAG_RESULT_DATA6);
347 color_regid[7] = ir3_find_output_regid(fs, FRAG_RESULT_DATA7);
348 }
349
350 samp_id_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_ID);
351 smask_in_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_MASK_IN);
352 face_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRONT_FACE);
353 coord_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRAG_COORD);
354 zwcoord_regid = next_regid(coord_regid, 2);
355 ij_pix_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL);
356 ij_samp_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE);
357 ij_cent_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID);
358 ij_size_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE);
359 posz_regid = ir3_find_output_regid(fs, FRAG_RESULT_DEPTH);
360 smask_regid = ir3_find_output_regid(fs, FRAG_RESULT_SAMPLE_MASK);
361
362 /* If we have pre-dispatch texture fetches, then ij_pix should not
363 * be DCE'd, even if not actually used in the shader itself:
364 */
365 if (fs->num_sampler_prefetch > 0) {
366 assert(VALIDREG(ij_pix_regid));
367 /* also, it seems like ij_pix is *required* to be r0.x */
368 assert(ij_pix_regid == regid(0, 0));
369 }
370
371 /* we can't write gl_SampleMask for !msaa.. if b0 is zero then we
372 * end up masking the single sample!!
373 */
374 if (!key->msaa)
375 smask_regid = regid(63, 0);
376
377 /* we could probably divide this up into things that need to be
378 * emitted if frag-prog is dirty vs if vert-prog is dirty..
379 */
380
381 OUT_PKT4(ring, REG_A6XX_SP_HS_UNKNOWN_A833, 1);
382 OUT_RING(ring, 0x0);
383
384 OUT_PKT4(ring, REG_A6XX_SP_FS_PREFETCH_CNTL, 1 + fs->num_sampler_prefetch);
385 OUT_RING(ring, A6XX_SP_FS_PREFETCH_CNTL_COUNT(fs->num_sampler_prefetch) |
386 A6XX_SP_FS_PREFETCH_CNTL_UNK4(regid(63, 0)) |
387 0x7000); // XXX
388 for (int i = 0; i < fs->num_sampler_prefetch; i++) {
389 const struct ir3_sampler_prefetch *prefetch = &fs->sampler_prefetch[i];
390 OUT_RING(ring, A6XX_SP_FS_PREFETCH_CMD_SRC(prefetch->src) |
391 A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(prefetch->samp_id) |
392 A6XX_SP_FS_PREFETCH_CMD_TEX_ID(prefetch->tex_id) |
393 A6XX_SP_FS_PREFETCH_CMD_DST(prefetch->dst) |
394 A6XX_SP_FS_PREFETCH_CMD_WRMASK(prefetch->wrmask) |
395 COND(prefetch->half_precision, A6XX_SP_FS_PREFETCH_CMD_HALF) |
396 A6XX_SP_FS_PREFETCH_CMD_CMD(prefetch->cmd));
397 }
398
399 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A9A8, 1);
400 OUT_RING(ring, 0);
401
402 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_AB00, 1);
403 OUT_RING(ring, 0x5);
404
405 OUT_PKT4(ring, REG_A6XX_SP_FS_OUTPUT_CNTL0, 1);
406 OUT_RING(ring, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid) |
407 A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid) |
408 0xfc000000);
409
410 enum a3xx_threadsize vssz;
411 uint32_t vsregs;
412 if (ds || hs) {
413 vssz = TWO_QUADS;
414 vsregs = 0;
415 } else {
416 vssz = FOUR_QUADS;
417 vsregs = A6XX_SP_VS_CTRL_REG0_MERGEDREGS;
418 }
419
420 OUT_PKT4(ring, REG_A6XX_SP_VS_CTRL_REG0, 1);
421 OUT_RING(ring, A6XX_SP_VS_CTRL_REG0_THREADSIZE(vssz) |
422 A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vs->info.max_reg + 1) |
423 vsregs |
424 A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(vs->branchstack) |
425 COND(vs->need_pixlod, A6XX_SP_VS_CTRL_REG0_PIXLODENABLE));
426
427 fd6_emit_shader(ring, vs);
428 ir3_emit_immediates(screen, vs, ring);
429
430 struct ir3_shader_linkage l = {0};
431 const struct ir3_shader_variant *last_shader = fd6_last_shader(state);
432 ir3_link_shaders(&l, last_shader, fs, true);
433
434 OUT_PKT4(ring, REG_A6XX_VPC_VAR_DISABLE(0), 4);
435 OUT_RING(ring, ~l.varmask[0]); /* VPC_VAR[0].DISABLE */
436 OUT_RING(ring, ~l.varmask[1]); /* VPC_VAR[1].DISABLE */
437 OUT_RING(ring, ~l.varmask[2]); /* VPC_VAR[2].DISABLE */
438 OUT_RING(ring, ~l.varmask[3]); /* VPC_VAR[3].DISABLE */
439
440 /* Add stream out outputs after computing the VPC_VAR_DISABLE bitmask. */
441 if (last_shader->shader->stream_output.num_outputs > 0)
442 link_stream_out(&l, last_shader);
443
444 if (VALIDREG(layer_regid)) {
445 layer_loc = l.max_loc;
446 ir3_link_add(&l, layer_regid, 0x1, l.max_loc);
447 }
448
449 if (VALIDREG(pos_regid)) {
450 pos_loc = l.max_loc;
451 ir3_link_add(&l, pos_regid, 0xf, l.max_loc);
452 }
453
454 if (VALIDREG(psize_regid)) {
455 psize_loc = l.max_loc;
456 ir3_link_add(&l, psize_regid, 0x1, l.max_loc);
457 }
458
459 if (last_shader->shader->stream_output.num_outputs > 0) {
460 setup_stream_out(state, last_shader, &l);
461 }
462
463 debug_assert(l.cnt < 32);
464 if (gs)
465 OUT_PKT4(ring, REG_A6XX_SP_GS_OUT_REG(0), DIV_ROUND_UP(l.cnt, 2));
466 else if (ds)
467 OUT_PKT4(ring, REG_A6XX_SP_DS_OUT_REG(0), DIV_ROUND_UP(l.cnt, 2));
468 else
469 OUT_PKT4(ring, REG_A6XX_SP_VS_OUT_REG(0), DIV_ROUND_UP(l.cnt, 2));
470
471 for (j = 0; j < l.cnt; ) {
472 uint32_t reg = 0;
473
474 reg |= A6XX_SP_VS_OUT_REG_A_REGID(l.var[j].regid);
475 reg |= A6XX_SP_VS_OUT_REG_A_COMPMASK(l.var[j].compmask);
476 j++;
477
478 reg |= A6XX_SP_VS_OUT_REG_B_REGID(l.var[j].regid);
479 reg |= A6XX_SP_VS_OUT_REG_B_COMPMASK(l.var[j].compmask);
480 j++;
481
482 OUT_RING(ring, reg);
483 }
484
485 if (gs)
486 OUT_PKT4(ring, REG_A6XX_SP_GS_VPC_DST_REG(0), DIV_ROUND_UP(l.cnt, 4));
487 else if (ds)
488 OUT_PKT4(ring, REG_A6XX_SP_DS_VPC_DST_REG(0), DIV_ROUND_UP(l.cnt, 4));
489 else
490 OUT_PKT4(ring, REG_A6XX_SP_VS_VPC_DST_REG(0), DIV_ROUND_UP(l.cnt, 4));
491
492 for (j = 0; j < l.cnt; ) {
493 uint32_t reg = 0;
494
495 reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC0(l.var[j++].loc);
496 reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC1(l.var[j++].loc);
497 reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC2(l.var[j++].loc);
498 reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC3(l.var[j++].loc);
499
500 OUT_RING(ring, reg);
501 }
502
503 if (hs) {
504 OUT_PKT4(ring, REG_A6XX_SP_HS_CTRL_REG0, 1);
505 OUT_RING(ring, A6XX_SP_HS_CTRL_REG0_THREADSIZE(TWO_QUADS) |
506 A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(hs->info.max_reg + 1) |
507 A6XX_SP_HS_CTRL_REG0_BRANCHSTACK(hs->branchstack) |
508 COND(hs->need_pixlod, A6XX_SP_HS_CTRL_REG0_PIXLODENABLE));
509
510 fd6_emit_shader(ring, hs);
511 ir3_emit_immediates(screen, hs, ring);
512 ir3_emit_link_map(screen, vs, hs, ring);
513
514 OUT_PKT4(ring, REG_A6XX_SP_DS_CTRL_REG0, 1);
515 OUT_RING(ring, A6XX_SP_DS_CTRL_REG0_THREADSIZE(TWO_QUADS) |
516 A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(ds->info.max_reg + 1) |
517 A6XX_SP_DS_CTRL_REG0_BRANCHSTACK(ds->branchstack) |
518 COND(ds->need_pixlod, A6XX_SP_DS_CTRL_REG0_PIXLODENABLE));
519
520 fd6_emit_shader(ring, ds);
521 ir3_emit_immediates(screen, ds, ring);
522 ir3_emit_link_map(screen, hs, ds, ring);
523
524 shader_info *hs_info = &hs->shader->nir->info;
525 OUT_PKT4(ring, REG_A6XX_PC_TESS_NUM_VERTEX, 1);
526 OUT_RING(ring, hs_info->tess.tcs_vertices_out);
527
528 /* Total attribute slots in HS incoming patch. */
529 OUT_PKT4(ring, REG_A6XX_PC_UNKNOWN_9801, 1);
530 OUT_RING(ring, hs_info->tess.tcs_vertices_out * vs->shader->output_size / 4);
531
532 OUT_PKT4(ring, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
533 OUT_RING(ring, vs->shader->output_size);
534
535 shader_info *ds_info = &ds->shader->nir->info;
536 OUT_PKT4(ring, REG_A6XX_PC_TESS_CNTL, 1);
537 uint32_t output;
538 if (ds_info->tess.point_mode)
539 output = TESS_POINTS;
540 else if (ds_info->tess.primitive_mode == GL_ISOLINES)
541 output = TESS_LINES;
542 else if (ds_info->tess.ccw)
543 output = TESS_CCW_TRIS;
544 else
545 output = TESS_CW_TRIS;
546
547 OUT_RING(ring, A6XX_PC_TESS_CNTL_SPACING(fd6_gl2spacing(ds_info->tess.spacing)) |
548 A6XX_PC_TESS_CNTL_OUTPUT(output));
549
550 /* xxx: Misc tess unknowns: */
551 OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9103, 1);
552 OUT_RING(ring, 0x00ffff00);
553
554 OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9106, 1);
555 OUT_RING(ring, 0x0000ffff);
556
557 OUT_PKT4(ring, REG_A6XX_GRAS_UNKNOWN_809D, 1);
558 OUT_RING(ring, 0x0);
559
560 OUT_PKT4(ring, REG_A6XX_GRAS_UNKNOWN_8002, 1);
561 OUT_RING(ring, 0x0);
562
563 OUT_PKT4(ring, REG_A6XX_VPC_PACK, 1);
564 OUT_RING(ring, A6XX_VPC_PACK_POSITIONLOC(pos_loc) |
565 A6XX_VPC_PACK_PSIZELOC(255) |
566 A6XX_VPC_PACK_STRIDE_IN_VPC(l.max_loc));
567
568 OUT_PKT4(ring, REG_A6XX_VPC_PACK_3, 1);
569 OUT_RING(ring, A6XX_VPC_PACK_3_POSITIONLOC(pos_loc) |
570 A6XX_VPC_PACK_3_PSIZELOC(psize_loc) |
571 A6XX_VPC_PACK_3_STRIDE_IN_VPC(l.max_loc));
572
573 OUT_PKT4(ring, REG_A6XX_SP_DS_PRIMITIVE_CNTL, 1);
574 OUT_RING(ring, A6XX_SP_DS_PRIMITIVE_CNTL_DSOUT(l.cnt));
575
576 OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_4, 1);
577 OUT_RING(ring, A6XX_PC_PRIMITIVE_CNTL_4_STRIDE_IN_VPC(l.max_loc) |
578 CONDREG(psize_regid, 0x100));
579
580 } else {
581 OUT_PKT4(ring, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
582 OUT_RING(ring, 0);
583 }
584
585 OUT_PKT4(ring, REG_A6XX_SP_PRIMITIVE_CNTL, 1);
586 OUT_RING(ring, A6XX_SP_PRIMITIVE_CNTL_VSOUT(l.cnt));
587
588 bool enable_varyings = fs->total_in > 0;
589
590 OUT_PKT4(ring, REG_A6XX_VPC_CNTL_0, 1);
591 OUT_RING(ring, A6XX_VPC_CNTL_0_NUMNONPOSVAR(fs->total_in) |
592 COND(enable_varyings, A6XX_VPC_CNTL_0_VARYING) |
593 0xff00ff00);
594
595 OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_1, 1);
596 OUT_RING(ring, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(l.max_loc) |
597 CONDREG(psize_regid, A6XX_PC_PRIMITIVE_CNTL_1_PSIZE));
598
599 OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_3, 1);
600 OUT_RING(ring, 0);
601
602 OUT_PKT4(ring, REG_A6XX_HLSQ_CONTROL_1_REG, 5);
603 OUT_RING(ring, 0x7); /* XXX */
604 OUT_RING(ring, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid) |
605 A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid) |
606 A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(smask_in_regid) |
607 A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_size_regid));
608 OUT_RING(ring, A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL(ij_pix_regid) |
609 A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID(ij_cent_regid) |
610 0xfc00fc00); /* XXX */
611 OUT_RING(ring, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid) |
612 A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid) |
613 A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP(ij_samp_regid) |
614 0x0000fc00); /* XXX */
615 OUT_RING(ring, 0xfc); /* XXX */
616
617 OUT_PKT4(ring, REG_A6XX_HLSQ_UNKNOWN_B980, 1);
618 OUT_RING(ring, enable_varyings ? 3 : 1);
619
620 OUT_PKT4(ring, REG_A6XX_SP_FS_CTRL_REG0, 1);
621 OUT_RING(ring, A6XX_SP_FS_CTRL_REG0_THREADSIZE(fssz) |
622 COND(enable_varyings, A6XX_SP_FS_CTRL_REG0_VARYING) |
623 COND(fs->frag_coord, A6XX_SP_FS_CTRL_REG0_VARYING) |
624 0x1000000 |
625 A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fs->info.max_reg + 1) |
626 A6XX_SP_FS_CTRL_REG0_MERGEDREGS |
627 A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(fs->branchstack) |
628 COND(fs->need_pixlod, A6XX_SP_FS_CTRL_REG0_PIXLODENABLE));
629
630 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A982, 1);
631 OUT_RING(ring, 0); /* XXX */
632
633 OUT_PKT4(ring, REG_A6XX_VPC_GS_SIV_CNTL, 1);
634 OUT_RING(ring, 0x0000ffff); /* XXX */
635
636 OUT_PKT4(ring, REG_A6XX_GRAS_CNTL, 1);
637 OUT_RING(ring,
638 CONDREG(ij_pix_regid, A6XX_GRAS_CNTL_VARYING) |
639 CONDREG(ij_cent_regid, A6XX_GRAS_CNTL_CENTROID) |
640 CONDREG(ij_samp_regid, A6XX_GRAS_CNTL_PERSAMP_VARYING) |
641 COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_GRAS_CNTL_SIZE) |
642 COND(VALIDREG(ij_size_regid) && sample_shading, A6XX_GRAS_CNTL_SIZE_PERSAMP) |
643 COND(fs->frag_coord,
644 A6XX_GRAS_CNTL_SIZE |
645 A6XX_GRAS_CNTL_XCOORD |
646 A6XX_GRAS_CNTL_YCOORD |
647 A6XX_GRAS_CNTL_ZCOORD |
648 A6XX_GRAS_CNTL_WCOORD) |
649 COND(fs->frag_face, A6XX_GRAS_CNTL_SIZE));
650
651 OUT_PKT4(ring, REG_A6XX_RB_RENDER_CONTROL0, 2);
652 OUT_RING(ring,
653 CONDREG(ij_pix_regid, A6XX_RB_RENDER_CONTROL0_VARYING) |
654 CONDREG(ij_cent_regid, A6XX_RB_RENDER_CONTROL0_CENTROID) |
655 CONDREG(ij_samp_regid, A6XX_RB_RENDER_CONTROL0_PERSAMP_VARYING) |
656 COND(enable_varyings, A6XX_RB_RENDER_CONTROL0_UNK10) |
657 COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE) |
658 COND(VALIDREG(ij_size_regid) && sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP) |
659 COND(fs->frag_coord,
660 A6XX_RB_RENDER_CONTROL0_SIZE |
661 A6XX_RB_RENDER_CONTROL0_XCOORD |
662 A6XX_RB_RENDER_CONTROL0_YCOORD |
663 A6XX_RB_RENDER_CONTROL0_ZCOORD |
664 A6XX_RB_RENDER_CONTROL0_WCOORD) |
665 COND(fs->frag_face, A6XX_RB_RENDER_CONTROL0_SIZE));
666
667 OUT_RING(ring,
668 CONDREG(smask_in_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK) |
669 CONDREG(samp_id_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEID) |
670 CONDREG(ij_size_regid, A6XX_RB_RENDER_CONTROL1_SIZE) |
671 COND(fs->frag_face, A6XX_RB_RENDER_CONTROL1_FACENESS));
672
673 OUT_PKT4(ring, REG_A6XX_RB_SAMPLE_CNTL, 1);
674 OUT_RING(ring, COND(sample_shading, A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE));
675
676 OUT_PKT4(ring, REG_A6XX_GRAS_UNKNOWN_8101, 1);
677 OUT_RING(ring, COND(sample_shading, 0x6)); // XXX
678
679 OUT_PKT4(ring, REG_A6XX_GRAS_SAMPLE_CNTL, 1);
680 OUT_RING(ring, COND(sample_shading, A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE));
681
682 OUT_PKT4(ring, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
683 for (i = 0; i < 8; i++) {
684 OUT_RING(ring, A6XX_SP_FS_OUTPUT_REG_REGID(color_regid[i]) |
685 COND(color_regid[i] & HALF_REG_ID, A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION));
686 }
687
688 OUT_PKT4(ring, REG_A6XX_VPC_PACK, 1);
689 OUT_RING(ring, A6XX_VPC_PACK_POSITIONLOC(pos_loc) |
690 A6XX_VPC_PACK_PSIZELOC(psize_loc) |
691 A6XX_VPC_PACK_STRIDE_IN_VPC(l.max_loc));
692
693 if (gs) {
694 OUT_PKT4(ring, REG_A6XX_SP_GS_CTRL_REG0, 1);
695 OUT_RING(ring, A6XX_SP_GS_CTRL_REG0_THREADSIZE(TWO_QUADS) |
696 A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(gs->info.max_reg + 1) |
697 A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(gs->branchstack) |
698 COND(gs->need_pixlod, A6XX_SP_GS_CTRL_REG0_PIXLODENABLE));
699
700 fd6_emit_shader(ring, gs);
701 ir3_emit_immediates(screen, gs, ring);
702 if (ds)
703 ir3_emit_link_map(screen, ds, gs, ring);
704 else
705 ir3_emit_link_map(screen, vs, gs, ring);
706
707 OUT_PKT4(ring, REG_A6XX_VPC_PACK_GS, 1);
708 OUT_RING(ring, A6XX_VPC_PACK_GS_POSITIONLOC(pos_loc) |
709 A6XX_VPC_PACK_GS_PSIZELOC(psize_loc) |
710 A6XX_VPC_PACK_GS_STRIDE_IN_VPC(l.max_loc));
711
712 OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9105, 1);
713 OUT_RING(ring, A6XX_VPC_UNKNOWN_9105_LAYERLOC(layer_loc) | 0xff00);
714
715 OUT_PKT4(ring, REG_A6XX_GRAS_UNKNOWN_809C, 1);
716 OUT_RING(ring, CONDREG(layer_regid, A6XX_GRAS_UNKNOWN_809C_GS_WRITES_LAYER));
717
718 uint32_t flags_regid = ir3_find_output_regid(gs, VARYING_SLOT_GS_VERTEX_FLAGS_IR3);
719
720 OUT_PKT4(ring, REG_A6XX_SP_PRIMITIVE_CNTL_GS, 1);
721 OUT_RING(ring, A6XX_SP_PRIMITIVE_CNTL_GS_GSOUT(l.cnt) |
722 A6XX_SP_PRIMITIVE_CNTL_GS_FLAGS_REGID(flags_regid));
723
724 OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_2, 1);
725 OUT_RING(ring, A6XX_PC_PRIMITIVE_CNTL_2_STRIDE_IN_VPC(l.max_loc) |
726 CONDREG(psize_regid, A6XX_PC_PRIMITIVE_CNTL_2_PSIZE) |
727 CONDREG(layer_regid, A6XX_PC_PRIMITIVE_CNTL_2_LAYER) |
728 CONDREG(primitive_regid, A6XX_PC_PRIMITIVE_CNTL_2_PRIMITIVE_ID));
729
730 uint32_t output;
731 switch (gs->shader->nir->info.gs.output_primitive) {
732 case GL_POINTS:
733 output = TESS_POINTS;
734 break;
735 case GL_LINE_STRIP:
736 output = TESS_LINES;
737 break;
738 case GL_TRIANGLE_STRIP:
739 output = TESS_CW_TRIS;
740 break;
741 default:
742 unreachable("");
743 }
744 OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_5, 1);
745 OUT_RING(ring,
746 A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(gs->shader->nir->info.gs.vertices_out - 1) |
747 A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(output) |
748 A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(gs->shader->nir->info.gs.invocations - 1));
749
750 OUT_PKT4(ring, REG_A6XX_GRAS_UNKNOWN_8003, 1);
751 OUT_RING(ring, 0);
752
753 OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9100, 1);
754 OUT_RING(ring, 0xff);
755
756 OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9102, 1);
757 OUT_RING(ring, 0xffff00);
758
759 const struct ir3_shader_variant *prev = state->ds ? state->ds : state->vs;
760
761 /* Size of per-primitive alloction in ldlw memory in vec4s. */
762 uint32_t vec4_size =
763 gs->shader->nir->info.gs.vertices_in *
764 DIV_ROUND_UP(prev->shader->output_size, 4);
765 OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_6, 1);
766 OUT_RING(ring, A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(vec4_size));
767
768 OUT_PKT4(ring, REG_A6XX_PC_UNKNOWN_9B07, 1);
769 OUT_RING(ring, 0);
770
771 OUT_PKT4(ring, REG_A6XX_SP_GS_UNKNOWN_A871, 1);
772 OUT_RING(ring, prev->shader->output_size);
773 } else {
774 OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_6, 1);
775 OUT_RING(ring, 0);
776 OUT_PKT4(ring, REG_A6XX_SP_GS_UNKNOWN_A871, 1);
777 OUT_RING(ring, 0);
778 }
779
780 OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9101, 1);
781 OUT_RING(ring, 0xffff00);
782
783 OUT_PKT4(ring, REG_A6XX_VPC_UNKNOWN_9107, 1);
784 OUT_RING(ring, 0);
785
786 if (fs->instrlen)
787 fd6_emit_shader(ring, fs);
788
789 OUT_PKT4(ring, REG_A6XX_VFD_CONTROL_1, 6);
790 OUT_RING(ring, A6XX_VFD_CONTROL_1_REGID4VTX(vertex_regid) |
791 A6XX_VFD_CONTROL_1_REGID4INST(instance_regid) |
792 A6XX_VFD_CONTROL_1_REGID4PRIMID(primitive_regid) |
793 0xfc000000);
794 OUT_RING(ring, A6XX_VFD_CONTROL_2_REGID_HSPATCHID(hs_patch_regid) |
795 A6XX_VFD_CONTROL_2_REGID_INVOCATIONID(hs_invocation_regid));
796 OUT_RING(ring, A6XX_VFD_CONTROL_3_REGID_DSPATCHID(ds_patch_regid) |
797 A6XX_VFD_CONTROL_3_REGID_TESSX(tess_coord_x_regid) |
798 A6XX_VFD_CONTROL_3_REGID_TESSY(tess_coord_y_regid) |
799 0xfc);
800 OUT_RING(ring, 0x000000fc); /* VFD_CONTROL_4 */
801 OUT_RING(ring, A6XX_VFD_CONTROL_5_REGID_GSHEADER(gs_header_regid) |
802 0xfc00); /* VFD_CONTROL_5 */
803 OUT_RING(ring, 0x00000000); /* VFD_CONTROL_6 */
804
805 bool fragz = fs->no_earlyz | fs->writes_pos;
806
807 OUT_PKT4(ring, REG_A6XX_RB_DEPTH_PLANE_CNTL, 1);
808 OUT_RING(ring, COND(fragz, A6XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z));
809
810 OUT_PKT4(ring, REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL, 1);
811 OUT_RING(ring, COND(fragz, A6XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z));
812
813 if (!binning_pass)
814 ir3_emit_immediates(screen, fs, ring);
815 }
816
817 static struct fd_ringbuffer *
818 create_interp_stateobj(struct fd_context *ctx, struct fd6_program_state *state)
819 {
820 const struct ir3_shader_variant *fs = state->fs;
821 struct fd_ringbuffer *ring = fd_ringbuffer_new_object(ctx->pipe, 18 * 4);
822 uint32_t vinterp[8] = {0};
823
824 /* figure out VARYING_INTERP / VARYING_PS_REPL register values: */
825 for (int j = -1; (j = ir3_next_varying(fs, j)) < (int)fs->inputs_count; ) {
826 /* NOTE: varyings are packed, so if compmask is 0xb
827 * then first, third, and fourth component occupy
828 * three consecutive varying slots:
829 */
830 unsigned compmask = fs->inputs[j].compmask;
831
832 uint32_t inloc = fs->inputs[j].inloc;
833
834 if (fs->inputs[j].interpolate == INTERP_MODE_FLAT) {
835 uint32_t loc = inloc;
836
837 for (int i = 0; i < 4; i++) {
838 if (compmask & (1 << i)) {
839 vinterp[loc / 16] |= 1 << ((loc % 16) * 2);
840 loc++;
841 }
842 }
843 }
844 }
845
846 OUT_PKT4(ring, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
847 for (int i = 0; i < 8; i++)
848 OUT_RING(ring, vinterp[i]); /* VPC_VARYING_INTERP[i].MODE */
849
850 OUT_PKT4(ring, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
851 for (int i = 0; i < 8; i++)
852 OUT_RING(ring, 0x00000000); /* VPC_VARYING_PS_REPL[i] */
853
854 return ring;
855 }
856
857 /* build the program streaming state which is not part of the pre-
858 * baked stateobj because of dependency on other gl state (rasterflat
859 * or sprite-coord-replacement)
860 */
861 struct fd_ringbuffer *
862 fd6_program_interp_state(struct fd6_emit *emit)
863 {
864 const struct fd6_program_state *state = fd6_emit_get_prog(emit);
865
866 if (!unlikely(emit->rasterflat || emit->sprite_coord_enable)) {
867 /* fastpath: */
868 return fd_ringbuffer_ref(state->interp_stateobj);
869 } else {
870 struct fd_ringbuffer *ring = fd_submit_new_ringbuffer(
871 emit->ctx->batch->submit, 18 * 4, FD_RINGBUFFER_STREAMING);
872
873 /* slow-path: */
874 struct ir3_shader_variant *fs = state->fs;
875 uint32_t vinterp[8], vpsrepl[8];
876
877 memset(vinterp, 0, sizeof(vinterp));
878 memset(vpsrepl, 0, sizeof(vpsrepl));
879
880 for (int j = -1; (j = ir3_next_varying(fs, j)) < (int)fs->inputs_count; ) {
881
882 /* NOTE: varyings are packed, so if compmask is 0xb
883 * then first, third, and fourth component occupy
884 * three consecutive varying slots:
885 */
886 unsigned compmask = fs->inputs[j].compmask;
887
888 uint32_t inloc = fs->inputs[j].inloc;
889
890 if ((fs->inputs[j].interpolate == INTERP_MODE_FLAT) ||
891 (fs->inputs[j].rasterflat && emit->rasterflat)) {
892 uint32_t loc = inloc;
893
894 for (int i = 0; i < 4; i++) {
895 if (compmask & (1 << i)) {
896 vinterp[loc / 16] |= 1 << ((loc % 16) * 2);
897 loc++;
898 }
899 }
900 }
901
902 gl_varying_slot slot = fs->inputs[j].slot;
903
904 /* since we don't enable PIPE_CAP_TGSI_TEXCOORD: */
905 if (slot >= VARYING_SLOT_VAR0) {
906 unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
907 /* Replace the .xy coordinates with S/T from the point sprite. Set
908 * interpolation bits for .zw such that they become .01
909 */
910 if (emit->sprite_coord_enable & texmask) {
911 /* mask is two 2-bit fields, where:
912 * '01' -> S
913 * '10' -> T
914 * '11' -> 1 - T (flip mode)
915 */
916 unsigned mask = emit->sprite_coord_mode ? 0b1101 : 0b1001;
917 uint32_t loc = inloc;
918 if (compmask & 0x1) {
919 vpsrepl[loc / 16] |= ((mask >> 0) & 0x3) << ((loc % 16) * 2);
920 loc++;
921 }
922 if (compmask & 0x2) {
923 vpsrepl[loc / 16] |= ((mask >> 2) & 0x3) << ((loc % 16) * 2);
924 loc++;
925 }
926 if (compmask & 0x4) {
927 /* .z <- 0.0f */
928 vinterp[loc / 16] |= 0b10 << ((loc % 16) * 2);
929 loc++;
930 }
931 if (compmask & 0x8) {
932 /* .w <- 1.0f */
933 vinterp[loc / 16] |= 0b11 << ((loc % 16) * 2);
934 loc++;
935 }
936 }
937 }
938 }
939
940 OUT_PKT4(ring, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
941 for (int i = 0; i < 8; i++)
942 OUT_RING(ring, vinterp[i]); /* VPC_VARYING_INTERP[i].MODE */
943
944 OUT_PKT4(ring, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
945 for (int i = 0; i < 8; i++)
946 OUT_RING(ring, vpsrepl[i]); /* VPC_VARYING_PS_REPL[i] */
947
948 return ring;
949 }
950 }
951
952 static struct ir3_program_state *
953 fd6_program_create(void *data, struct ir3_shader_variant *bs,
954 struct ir3_shader_variant *vs,
955 struct ir3_shader_variant *hs,
956 struct ir3_shader_variant *ds,
957 struct ir3_shader_variant *gs,
958 struct ir3_shader_variant *fs,
959 const struct ir3_shader_key *key)
960 {
961 struct fd_context *ctx = data;
962 struct fd6_program_state *state = CALLOC_STRUCT(fd6_program_state);
963
964 /* if we have streamout, use full VS in binning pass, as the
965 * binning pass VS will have outputs on other than position/psize
966 * stripped out:
967 */
968 state->bs = vs->shader->stream_output.num_outputs ? vs : bs;
969 state->vs = vs;
970 state->hs = hs;
971 state->ds = ds;
972 state->gs = gs;
973 state->fs = fs;
974 state->config_stateobj = fd_ringbuffer_new_object(ctx->pipe, 0x1000);
975 state->binning_stateobj = fd_ringbuffer_new_object(ctx->pipe, 0x1000);
976 state->stateobj = fd_ringbuffer_new_object(ctx->pipe, 0x1000);
977
978 #ifdef DEBUG
979 if (!ds) {
980 for (unsigned i = 0; i < bs->inputs_count; i++) {
981 if (vs->inputs[i].sysval)
982 continue;
983 debug_assert(bs->inputs[i].regid == vs->inputs[i].regid);
984 }
985 }
986 #endif
987
988 setup_config_stateobj(state->config_stateobj, state);
989 setup_stateobj(state->binning_stateobj, ctx->screen, state, key, true);
990 setup_stateobj(state->stateobj, ctx->screen, state, key, false);
991 state->interp_stateobj = create_interp_stateobj(ctx, state);
992
993 return &state->base;
994 }
995
996 static void
997 fd6_program_destroy(void *data, struct ir3_program_state *state)
998 {
999 struct fd6_program_state *so = fd6_program_state(state);
1000 fd_ringbuffer_del(so->stateobj);
1001 fd_ringbuffer_del(so->binning_stateobj);
1002 fd_ringbuffer_del(so->config_stateobj);
1003 fd_ringbuffer_del(so->interp_stateobj);
1004 free(so);
1005 }
1006
1007 static const struct ir3_cache_funcs cache_funcs = {
1008 .create_state = fd6_program_create,
1009 .destroy_state = fd6_program_destroy,
1010 };
1011
1012 static void *
1013 fd6_shader_state_create(struct pipe_context *pctx, const struct pipe_shader_state *cso)
1014 {
1015 struct fd_context *ctx = fd_context(pctx);
1016 struct ir3_compiler *compiler = ctx->screen->compiler;
1017 struct ir3_shader *shader =
1018 ir3_shader_create(compiler, cso, &ctx->debug, pctx->screen);
1019 unsigned packets, size;
1020
1021 /* pre-calculate size required for userconst stateobj: */
1022 ir3_user_consts_size(&shader->ubo_state, &packets, &size);
1023
1024 /* also account for UBO addresses: */
1025 packets += 1;
1026 size += 2 * shader->const_state.num_ubos;
1027
1028 unsigned sizedwords = (4 * packets) + size;
1029 shader->ubo_state.cmdstream_size = sizedwords * 4;
1030
1031 return shader;
1032 }
1033
1034 static void
1035 fd6_shader_state_delete(struct pipe_context *pctx, void *hwcso)
1036 {
1037 struct ir3_shader *so = hwcso;
1038 struct fd_context *ctx = fd_context(pctx);
1039 ir3_cache_invalidate(fd6_context(ctx)->shader_cache, hwcso);
1040 ir3_shader_destroy(so);
1041 }
1042
1043 void
1044 fd6_prog_init(struct pipe_context *pctx)
1045 {
1046 struct fd_context *ctx = fd_context(pctx);
1047
1048 fd6_context(ctx)->shader_cache = ir3_cache_create(&cache_funcs, ctx);
1049
1050 pctx->create_vs_state = fd6_shader_state_create;
1051 pctx->delete_vs_state = fd6_shader_state_delete;
1052
1053 pctx->create_tcs_state = fd6_shader_state_create;
1054 pctx->delete_tcs_state = fd6_shader_state_delete;
1055
1056 pctx->create_tes_state = fd6_shader_state_create;
1057 pctx->delete_tes_state = fd6_shader_state_delete;
1058
1059 pctx->create_gs_state = fd6_shader_state_create;
1060 pctx->delete_gs_state = fd6_shader_state_delete;
1061
1062 pctx->create_gs_state = fd6_shader_state_create;
1063 pctx->delete_gs_state = fd6_shader_state_delete;
1064
1065 pctx->create_fs_state = fd6_shader_state_create;
1066 pctx->delete_fs_state = fd6_shader_state_delete;
1067
1068 fd_prog_init(pctx);
1069 }