2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25 * Rob Clark <robclark@freedesktop.org>
28 #include "pipe/p_state.h"
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_inlines.h"
32 #include "util/format/u_format.h"
33 #include "util/bitset.h"
35 #include "freedreno_program.h"
37 #include "fd6_program.h"
38 #include "fd6_const.h"
40 #include "fd6_texture.h"
41 #include "fd6_format.h"
44 fd6_emit_shader(struct fd_ringbuffer
*ring
, const struct ir3_shader_variant
*so
)
46 enum a6xx_state_block sb
= fd6_stage2shadersb(so
->type
);
52 case MESA_SHADER_VERTEX
:
53 obj_start
= REG_A6XX_SP_VS_OBJ_START_LO
;
54 instrlen
= REG_A6XX_SP_VS_INSTRLEN
;
56 case MESA_SHADER_TESS_CTRL
:
57 obj_start
= REG_A6XX_SP_HS_OBJ_START_LO
;
58 instrlen
= REG_A6XX_SP_HS_INSTRLEN
;
60 case MESA_SHADER_TESS_EVAL
:
61 obj_start
= REG_A6XX_SP_DS_OBJ_START_LO
;
62 instrlen
= REG_A6XX_SP_DS_INSTRLEN
;
64 case MESA_SHADER_GEOMETRY
:
65 obj_start
= REG_A6XX_SP_GS_OBJ_START_LO
;
66 instrlen
= REG_A6XX_SP_GS_INSTRLEN
;
68 case MESA_SHADER_FRAGMENT
:
69 obj_start
= REG_A6XX_SP_FS_OBJ_START_LO
;
70 instrlen
= REG_A6XX_SP_FS_INSTRLEN
;
72 case MESA_SHADER_COMPUTE
:
73 case MESA_SHADER_KERNEL
:
74 obj_start
= REG_A6XX_SP_CS_OBJ_START_LO
;
75 instrlen
= REG_A6XX_SP_CS_INSTRLEN
;
77 case MESA_SHADER_NONE
:
82 /* Name should generally match what you get with MESA_SHADER_CAPTURE_PATH: */
83 const char *name
= so
->shader
->nir
->info
.name
;
85 fd_emit_string5(ring
, name
, strlen(name
));
88 OUT_PKT4(ring
, instrlen
, 1);
89 OUT_RING(ring
, so
->instrlen
);
91 OUT_PKT4(ring
, obj_start
, 2);
92 OUT_RELOC(ring
, so
->bo
, 0, 0, 0);
94 OUT_PKT7(ring
, fd6_stage2opcode(so
->type
), 3);
95 OUT_RING(ring
, CP_LOAD_STATE6_0_DST_OFF(0) |
96 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER
) |
97 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT
) |
98 CP_LOAD_STATE6_0_STATE_BLOCK(sb
) |
99 CP_LOAD_STATE6_0_NUM_UNIT(so
->instrlen
));
100 OUT_RELOC(ring
, so
->bo
, 0, 0, 0);
103 /* Add any missing varyings needed for stream-out. Otherwise varyings not
104 * used by fragment shader will be stripped out.
107 link_stream_out(struct ir3_shader_linkage
*l
, const struct ir3_shader_variant
*v
)
109 const struct ir3_stream_output_info
*strmout
= &v
->shader
->stream_output
;
112 * First, any stream-out varyings not already in linkage map (ie. also
113 * consumed by frag shader) need to be added:
115 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
116 const struct ir3_stream_output
*out
= &strmout
->output
[i
];
117 unsigned k
= out
->register_index
;
119 (1 << (out
->num_components
+ out
->start_component
)) - 1;
120 unsigned idx
, nextloc
= 0;
122 /* psize/pos need to be the last entries in linkage map, and will
123 * get added link_stream_out, so skip over them:
125 if ((v
->outputs
[k
].slot
== VARYING_SLOT_PSIZ
) ||
126 (v
->outputs
[k
].slot
== VARYING_SLOT_POS
))
129 for (idx
= 0; idx
< l
->cnt
; idx
++) {
130 if (l
->var
[idx
].regid
== v
->outputs
[k
].regid
)
132 nextloc
= MAX2(nextloc
, l
->var
[idx
].loc
+ 4);
135 /* add if not already in linkage map: */
137 ir3_link_add(l
, v
->outputs
[k
].regid
, compmask
, nextloc
);
139 /* expand component-mask if needed, ie streaming out all components
140 * but frag shader doesn't consume all components:
142 if (compmask
& ~l
->var
[idx
].compmask
) {
143 l
->var
[idx
].compmask
|= compmask
;
144 l
->max_loc
= MAX2(l
->max_loc
,
145 l
->var
[idx
].loc
+ util_last_bit(l
->var
[idx
].compmask
));
151 setup_stream_out(struct fd6_program_state
*state
, const struct ir3_shader_variant
*v
,
152 struct ir3_shader_linkage
*l
)
154 const struct ir3_stream_output_info
*strmout
= &v
->shader
->stream_output
;
156 uint32_t ncomp
[PIPE_MAX_SO_BUFFERS
];
157 uint32_t prog
[256/2];
160 memset(ncomp
, 0, sizeof(ncomp
));
161 memset(prog
, 0, sizeof(prog
));
163 prog_count
= align(l
->max_loc
, 2) / 2;
165 debug_assert(prog_count
< ARRAY_SIZE(prog
));
167 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
168 const struct ir3_stream_output
*out
= &strmout
->output
[i
];
169 unsigned k
= out
->register_index
;
172 ncomp
[out
->output_buffer
] += out
->num_components
;
174 /* linkage map sorted by order frag shader wants things, so
175 * a bit less ideal here..
177 for (idx
= 0; idx
< l
->cnt
; idx
++)
178 if (l
->var
[idx
].regid
== v
->outputs
[k
].regid
)
181 debug_assert(idx
< l
->cnt
);
183 for (unsigned j
= 0; j
< out
->num_components
; j
++) {
184 unsigned c
= j
+ out
->start_component
;
185 unsigned loc
= l
->var
[idx
].loc
+ c
;
186 unsigned off
= j
+ out
->dst_offset
; /* in dwords */
189 prog
[loc
/2] |= A6XX_VPC_SO_PROG_B_EN
|
190 A6XX_VPC_SO_PROG_B_BUF(out
->output_buffer
) |
191 A6XX_VPC_SO_PROG_B_OFF(off
* 4);
193 prog
[loc
/2] |= A6XX_VPC_SO_PROG_A_EN
|
194 A6XX_VPC_SO_PROG_A_BUF(out
->output_buffer
) |
195 A6XX_VPC_SO_PROG_A_OFF(off
* 4);
200 struct fd_ringbuffer
*ring
= state
->streamout_stateobj
;
202 OUT_PKT7(ring
, CP_CONTEXT_REG_BUNCH
, 12 + (2 * prog_count
));
203 OUT_RING(ring
, REG_A6XX_VPC_SO_BUF_CNTL
);
204 OUT_RING(ring
, A6XX_VPC_SO_BUF_CNTL_ENABLE
|
205 COND(ncomp
[0] > 0, A6XX_VPC_SO_BUF_CNTL_BUF0
) |
206 COND(ncomp
[1] > 0, A6XX_VPC_SO_BUF_CNTL_BUF1
) |
207 COND(ncomp
[2] > 0, A6XX_VPC_SO_BUF_CNTL_BUF2
) |
208 COND(ncomp
[3] > 0, A6XX_VPC_SO_BUF_CNTL_BUF3
));
209 OUT_RING(ring
, REG_A6XX_VPC_SO_NCOMP(0));
210 OUT_RING(ring
, ncomp
[0]);
211 OUT_RING(ring
, REG_A6XX_VPC_SO_NCOMP(1));
212 OUT_RING(ring
, ncomp
[1]);
213 OUT_RING(ring
, REG_A6XX_VPC_SO_NCOMP(2));
214 OUT_RING(ring
, ncomp
[2]);
215 OUT_RING(ring
, REG_A6XX_VPC_SO_NCOMP(3));
216 OUT_RING(ring
, ncomp
[3]);
217 OUT_RING(ring
, REG_A6XX_VPC_SO_CNTL
);
218 OUT_RING(ring
, A6XX_VPC_SO_CNTL_ENABLE
);
219 for (unsigned i
= 0; i
< prog_count
; i
++) {
220 OUT_RING(ring
, REG_A6XX_VPC_SO_PROG
);
221 OUT_RING(ring
, prog
[i
]);
226 setup_config_stateobj(struct fd_ringbuffer
*ring
, struct fd6_program_state
*state
)
228 OUT_PKT4(ring
, REG_A6XX_HLSQ_UPDATE_CNTL
, 1);
229 OUT_RING(ring
, 0xff); /* XXX */
232 debug_assert(state
->ds
->constlen
>= state
->bs
->constlen
);
234 debug_assert(state
->vs
->constlen
>= state
->bs
->constlen
);
236 OUT_PKT4(ring
, REG_A6XX_HLSQ_VS_CNTL
, 4);
237 OUT_RING(ring
, A6XX_HLSQ_VS_CNTL_CONSTLEN(state
->vs
->constlen
) |
238 A6XX_HLSQ_VS_CNTL_ENABLED
);
239 OUT_RING(ring
, COND(state
->hs
,
240 A6XX_HLSQ_HS_CNTL_ENABLED
|
241 A6XX_HLSQ_HS_CNTL_CONSTLEN(state
->hs
->constlen
)));
242 OUT_RING(ring
, COND(state
->ds
,
243 A6XX_HLSQ_DS_CNTL_ENABLED
|
244 A6XX_HLSQ_DS_CNTL_CONSTLEN(state
->ds
->constlen
)));
245 OUT_RING(ring
, COND(state
->gs
,
246 A6XX_HLSQ_GS_CNTL_ENABLED
|
247 A6XX_HLSQ_GS_CNTL_CONSTLEN(state
->gs
->constlen
)));
248 OUT_PKT4(ring
, REG_A6XX_HLSQ_FS_CNTL
, 1);
249 OUT_RING(ring
, A6XX_HLSQ_FS_CNTL_CONSTLEN(state
->fs
->constlen
) |
250 A6XX_HLSQ_FS_CNTL_ENABLED
);
252 OUT_PKT4(ring
, REG_A6XX_SP_VS_CONFIG
, 1);
253 OUT_RING(ring
, COND(state
->vs
, A6XX_SP_VS_CONFIG_ENABLED
) |
254 A6XX_SP_VS_CONFIG_NIBO(ir3_shader_nibo(state
->vs
)) |
255 A6XX_SP_VS_CONFIG_NTEX(state
->vs
->num_samp
) |
256 A6XX_SP_VS_CONFIG_NSAMP(state
->vs
->num_samp
));
258 OUT_PKT4(ring
, REG_A6XX_SP_HS_CONFIG
, 1);
259 OUT_RING(ring
, COND(state
->hs
,
260 A6XX_SP_HS_CONFIG_ENABLED
|
261 A6XX_SP_HS_CONFIG_NIBO(ir3_shader_nibo(state
->hs
)) |
262 A6XX_SP_HS_CONFIG_NTEX(state
->hs
->num_samp
) |
263 A6XX_SP_HS_CONFIG_NSAMP(state
->hs
->num_samp
)));
265 OUT_PKT4(ring
, REG_A6XX_SP_DS_CONFIG
, 1);
266 OUT_RING(ring
, COND(state
->ds
,
267 A6XX_SP_DS_CONFIG_ENABLED
|
268 A6XX_SP_DS_CONFIG_NIBO(ir3_shader_nibo(state
->ds
)) |
269 A6XX_SP_DS_CONFIG_NTEX(state
->ds
->num_samp
) |
270 A6XX_SP_DS_CONFIG_NSAMP(state
->ds
->num_samp
)));
272 OUT_PKT4(ring
, REG_A6XX_SP_GS_CONFIG
, 1);
273 OUT_RING(ring
, COND(state
->gs
,
274 A6XX_SP_GS_CONFIG_ENABLED
|
275 A6XX_SP_GS_CONFIG_NIBO(ir3_shader_nibo(state
->gs
)) |
276 A6XX_SP_GS_CONFIG_NTEX(state
->gs
->num_samp
) |
277 A6XX_SP_GS_CONFIG_NSAMP(state
->gs
->num_samp
)));
279 OUT_PKT4(ring
, REG_A6XX_SP_FS_CONFIG
, 1);
280 OUT_RING(ring
, COND(state
->fs
, A6XX_SP_FS_CONFIG_ENABLED
) |
281 A6XX_SP_FS_CONFIG_NIBO(ir3_shader_nibo(state
->fs
)) |
282 A6XX_SP_FS_CONFIG_NTEX(state
->fs
->num_samp
) |
283 A6XX_SP_FS_CONFIG_NSAMP(state
->fs
->num_samp
));
285 OUT_PKT4(ring
, REG_A6XX_SP_IBO_COUNT
, 1);
286 OUT_RING(ring
, ir3_shader_nibo(state
->fs
));
289 static inline uint32_t
290 next_regid(uint32_t reg
, uint32_t increment
)
293 return reg
+ increment
;
299 setup_stateobj(struct fd_ringbuffer
*ring
, struct fd_screen
*screen
,
300 struct fd6_program_state
*state
, const struct ir3_shader_key
*key
,
303 uint32_t pos_regid
, psize_regid
, color_regid
[8], posz_regid
;
304 uint32_t face_regid
, coord_regid
, zwcoord_regid
, samp_id_regid
;
305 uint32_t smask_in_regid
, smask_regid
;
306 uint32_t vertex_regid
, instance_regid
, layer_regid
, primitive_regid
;
307 uint32_t hs_invocation_regid
;
308 uint32_t tess_coord_x_regid
, tess_coord_y_regid
, hs_patch_regid
, ds_patch_regid
;
309 uint32_t ij_pix_regid
, ij_samp_regid
, ij_cent_regid
, ij_size_regid
;
310 uint32_t gs_header_regid
;
311 enum a3xx_threadsize fssz
;
312 uint8_t psize_loc
= ~0, pos_loc
= ~0, layer_loc
= ~0;
315 static const struct ir3_shader_variant dummy_fs
= {0};
316 const struct ir3_shader_variant
*vs
= binning_pass
? state
->bs
: state
->vs
;
317 const struct ir3_shader_variant
*hs
= state
->hs
;
318 const struct ir3_shader_variant
*ds
= state
->ds
;
319 const struct ir3_shader_variant
*gs
= state
->gs
;
320 const struct ir3_shader_variant
*fs
= binning_pass
? &dummy_fs
: state
->fs
;
322 /* binning VS is wrong when GS is present, so use nonbinning VS
323 * TODO: compile both binning VS/GS variants correctly
325 if (binning_pass
&& state
->gs
)
328 bool sample_shading
= fs
->per_samp
| key
->sample_shading
;
332 pos_regid
= ir3_find_output_regid(vs
, VARYING_SLOT_POS
);
333 psize_regid
= ir3_find_output_regid(vs
, VARYING_SLOT_PSIZ
);
334 vertex_regid
= ir3_find_sysval_regid(vs
, SYSTEM_VALUE_VERTEX_ID
);
335 instance_regid
= ir3_find_sysval_regid(vs
, SYSTEM_VALUE_INSTANCE_ID
);
338 tess_coord_x_regid
= ir3_find_sysval_regid(ds
, SYSTEM_VALUE_TESS_COORD
);
339 tess_coord_y_regid
= next_regid(tess_coord_x_regid
, 1);
340 hs_patch_regid
= ir3_find_sysval_regid(hs
, SYSTEM_VALUE_PRIMITIVE_ID
);
341 ds_patch_regid
= ir3_find_sysval_regid(ds
, SYSTEM_VALUE_PRIMITIVE_ID
);
342 hs_invocation_regid
= ir3_find_sysval_regid(hs
, SYSTEM_VALUE_TCS_HEADER_IR3
);
344 pos_regid
= ir3_find_output_regid(ds
, VARYING_SLOT_POS
);
345 psize_regid
= ir3_find_output_regid(ds
, VARYING_SLOT_PSIZ
);
347 tess_coord_x_regid
= regid(63, 0);
348 tess_coord_y_regid
= regid(63, 0);
349 hs_patch_regid
= regid(63, 0);
350 ds_patch_regid
= regid(63, 0);
351 hs_invocation_regid
= regid(63, 0);
355 gs_header_regid
= ir3_find_sysval_regid(gs
, SYSTEM_VALUE_GS_HEADER_IR3
);
356 primitive_regid
= ir3_find_sysval_regid(gs
, SYSTEM_VALUE_PRIMITIVE_ID
);
357 pos_regid
= ir3_find_output_regid(gs
, VARYING_SLOT_POS
);
358 psize_regid
= ir3_find_output_regid(gs
, VARYING_SLOT_PSIZ
);
359 layer_regid
= ir3_find_output_regid(gs
, VARYING_SLOT_LAYER
);
361 gs_header_regid
= regid(63, 0);
362 primitive_regid
= regid(63, 0);
363 layer_regid
= regid(63, 0);
366 if (fs
->color0_mrt
) {
367 color_regid
[0] = color_regid
[1] = color_regid
[2] = color_regid
[3] =
368 color_regid
[4] = color_regid
[5] = color_regid
[6] = color_regid
[7] =
369 ir3_find_output_regid(fs
, FRAG_RESULT_COLOR
);
371 color_regid
[0] = ir3_find_output_regid(fs
, FRAG_RESULT_DATA0
);
372 color_regid
[1] = ir3_find_output_regid(fs
, FRAG_RESULT_DATA1
);
373 color_regid
[2] = ir3_find_output_regid(fs
, FRAG_RESULT_DATA2
);
374 color_regid
[3] = ir3_find_output_regid(fs
, FRAG_RESULT_DATA3
);
375 color_regid
[4] = ir3_find_output_regid(fs
, FRAG_RESULT_DATA4
);
376 color_regid
[5] = ir3_find_output_regid(fs
, FRAG_RESULT_DATA5
);
377 color_regid
[6] = ir3_find_output_regid(fs
, FRAG_RESULT_DATA6
);
378 color_regid
[7] = ir3_find_output_regid(fs
, FRAG_RESULT_DATA7
);
381 samp_id_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_SAMPLE_ID
);
382 smask_in_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_SAMPLE_MASK_IN
);
383 face_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_FRONT_FACE
);
384 coord_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_FRAG_COORD
);
385 zwcoord_regid
= next_regid(coord_regid
, 2);
386 ij_pix_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL
);
387 ij_samp_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE
);
388 ij_cent_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID
);
389 ij_size_regid
= ir3_find_sysval_regid(fs
, SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE
);
390 posz_regid
= ir3_find_output_regid(fs
, FRAG_RESULT_DEPTH
);
391 smask_regid
= ir3_find_output_regid(fs
, FRAG_RESULT_SAMPLE_MASK
);
393 /* If we have pre-dispatch texture fetches, then ij_pix should not
394 * be DCE'd, even if not actually used in the shader itself:
396 if (fs
->num_sampler_prefetch
> 0) {
397 assert(VALIDREG(ij_pix_regid
));
398 /* also, it seems like ij_pix is *required* to be r0.x */
399 assert(ij_pix_regid
== regid(0, 0));
402 /* we can't write gl_SampleMask for !msaa.. if b0 is zero then we
403 * end up masking the single sample!!
406 smask_regid
= regid(63, 0);
408 /* we could probably divide this up into things that need to be
409 * emitted if frag-prog is dirty vs if vert-prog is dirty..
412 OUT_PKT4(ring
, REG_A6XX_SP_HS_UNKNOWN_A833
, 1);
415 OUT_PKT4(ring
, REG_A6XX_SP_FS_PREFETCH_CNTL
, 1 + fs
->num_sampler_prefetch
);
416 OUT_RING(ring
, A6XX_SP_FS_PREFETCH_CNTL_COUNT(fs
->num_sampler_prefetch
) |
417 A6XX_SP_FS_PREFETCH_CNTL_UNK4(regid(63, 0)) |
419 for (int i
= 0; i
< fs
->num_sampler_prefetch
; i
++) {
420 const struct ir3_sampler_prefetch
*prefetch
= &fs
->sampler_prefetch
[i
];
421 OUT_RING(ring
, A6XX_SP_FS_PREFETCH_CMD_SRC(prefetch
->src
) |
422 A6XX_SP_FS_PREFETCH_CMD_SAMP_ID(prefetch
->samp_id
) |
423 A6XX_SP_FS_PREFETCH_CMD_TEX_ID(prefetch
->tex_id
) |
424 A6XX_SP_FS_PREFETCH_CMD_DST(prefetch
->dst
) |
425 A6XX_SP_FS_PREFETCH_CMD_WRMASK(prefetch
->wrmask
) |
426 COND(prefetch
->half_precision
, A6XX_SP_FS_PREFETCH_CMD_HALF
) |
427 A6XX_SP_FS_PREFETCH_CMD_CMD(prefetch
->cmd
));
430 OUT_PKT4(ring
, REG_A6XX_SP_UNKNOWN_A9A8
, 1);
433 OUT_PKT4(ring
, REG_A6XX_SP_UNKNOWN_AB00
, 1);
436 OUT_PKT4(ring
, REG_A6XX_SP_FS_OUTPUT_CNTL0
, 1);
437 OUT_RING(ring
, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid
) |
438 A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid
) |
441 enum a3xx_threadsize vssz
;
448 OUT_PKT4(ring
, REG_A6XX_SP_VS_CTRL_REG0
, 1);
449 OUT_RING(ring
, A6XX_SP_VS_CTRL_REG0_THREADSIZE(vssz
) |
450 A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vs
->info
.max_reg
+ 1) |
451 A6XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(vs
->info
.max_half_reg
+ 1) |
452 COND(vs
->mergedregs
, A6XX_SP_VS_CTRL_REG0_MERGEDREGS
) |
453 A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(vs
->branchstack
) |
454 COND(vs
->need_pixlod
, A6XX_SP_VS_CTRL_REG0_PIXLODENABLE
));
456 fd6_emit_shader(ring
, vs
);
457 fd6_emit_immediates(screen
, vs
, ring
);
459 struct ir3_shader_linkage l
= {0};
460 const struct ir3_shader_variant
*last_shader
= fd6_last_shader(state
);
461 ir3_link_shaders(&l
, last_shader
, fs
, true);
463 bool primid_passthru
= l
.primid_loc
!= 0xff;
465 OUT_PKT4(ring
, REG_A6XX_VPC_VAR_DISABLE(0), 4);
466 OUT_RING(ring
, ~l
.varmask
[0]); /* VPC_VAR[0].DISABLE */
467 OUT_RING(ring
, ~l
.varmask
[1]); /* VPC_VAR[1].DISABLE */
468 OUT_RING(ring
, ~l
.varmask
[2]); /* VPC_VAR[2].DISABLE */
469 OUT_RING(ring
, ~l
.varmask
[3]); /* VPC_VAR[3].DISABLE */
471 /* Add stream out outputs after computing the VPC_VAR_DISABLE bitmask. */
472 if (last_shader
->shader
->stream_output
.num_outputs
> 0)
473 link_stream_out(&l
, last_shader
);
475 if (VALIDREG(layer_regid
)) {
476 layer_loc
= l
.max_loc
;
477 ir3_link_add(&l
, layer_regid
, 0x1, l
.max_loc
);
480 if (VALIDREG(pos_regid
)) {
482 ir3_link_add(&l
, pos_regid
, 0xf, l
.max_loc
);
485 if (VALIDREG(psize_regid
)) {
486 psize_loc
= l
.max_loc
;
487 ir3_link_add(&l
, psize_regid
, 0x1, l
.max_loc
);
490 if (last_shader
->shader
->stream_output
.num_outputs
> 0) {
491 setup_stream_out(state
, last_shader
, &l
);
494 debug_assert(l
.cnt
< 32);
496 OUT_PKT4(ring
, REG_A6XX_SP_GS_OUT_REG(0), DIV_ROUND_UP(l
.cnt
, 2));
498 OUT_PKT4(ring
, REG_A6XX_SP_DS_OUT_REG(0), DIV_ROUND_UP(l
.cnt
, 2));
500 OUT_PKT4(ring
, REG_A6XX_SP_VS_OUT_REG(0), DIV_ROUND_UP(l
.cnt
, 2));
502 for (j
= 0; j
< l
.cnt
; ) {
505 reg
|= A6XX_SP_VS_OUT_REG_A_REGID(l
.var
[j
].regid
);
506 reg
|= A6XX_SP_VS_OUT_REG_A_COMPMASK(l
.var
[j
].compmask
);
509 reg
|= A6XX_SP_VS_OUT_REG_B_REGID(l
.var
[j
].regid
);
510 reg
|= A6XX_SP_VS_OUT_REG_B_COMPMASK(l
.var
[j
].compmask
);
517 OUT_PKT4(ring
, REG_A6XX_SP_GS_VPC_DST_REG(0), DIV_ROUND_UP(l
.cnt
, 4));
519 OUT_PKT4(ring
, REG_A6XX_SP_DS_VPC_DST_REG(0), DIV_ROUND_UP(l
.cnt
, 4));
521 OUT_PKT4(ring
, REG_A6XX_SP_VS_VPC_DST_REG(0), DIV_ROUND_UP(l
.cnt
, 4));
523 for (j
= 0; j
< l
.cnt
; ) {
526 reg
|= A6XX_SP_VS_VPC_DST_REG_OUTLOC0(l
.var
[j
++].loc
);
527 reg
|= A6XX_SP_VS_VPC_DST_REG_OUTLOC1(l
.var
[j
++].loc
);
528 reg
|= A6XX_SP_VS_VPC_DST_REG_OUTLOC2(l
.var
[j
++].loc
);
529 reg
|= A6XX_SP_VS_VPC_DST_REG_OUTLOC3(l
.var
[j
++].loc
);
535 OUT_PKT4(ring
, REG_A6XX_SP_HS_CTRL_REG0
, 1);
536 OUT_RING(ring
, A6XX_SP_HS_CTRL_REG0_THREADSIZE(TWO_QUADS
) |
537 A6XX_SP_HS_CTRL_REG0_FULLREGFOOTPRINT(hs
->info
.max_reg
+ 1) |
538 A6XX_SP_HS_CTRL_REG0_HALFREGFOOTPRINT(hs
->info
.max_half_reg
+ 1) |
539 COND(hs
->mergedregs
, A6XX_SP_HS_CTRL_REG0_MERGEDREGS
) |
540 A6XX_SP_HS_CTRL_REG0_BRANCHSTACK(hs
->branchstack
) |
541 COND(hs
->need_pixlod
, A6XX_SP_HS_CTRL_REG0_PIXLODENABLE
));
543 fd6_emit_shader(ring
, hs
);
544 fd6_emit_immediates(screen
, hs
, ring
);
545 fd6_emit_link_map(screen
, vs
, hs
, ring
);
547 OUT_PKT4(ring
, REG_A6XX_SP_DS_CTRL_REG0
, 1);
548 OUT_RING(ring
, A6XX_SP_DS_CTRL_REG0_THREADSIZE(TWO_QUADS
) |
549 A6XX_SP_DS_CTRL_REG0_FULLREGFOOTPRINT(ds
->info
.max_reg
+ 1) |
550 A6XX_SP_DS_CTRL_REG0_HALFREGFOOTPRINT(ds
->info
.max_half_reg
+ 1) |
551 COND(ds
->mergedregs
, A6XX_SP_DS_CTRL_REG0_MERGEDREGS
) |
552 A6XX_SP_DS_CTRL_REG0_BRANCHSTACK(ds
->branchstack
) |
553 COND(ds
->need_pixlod
, A6XX_SP_DS_CTRL_REG0_PIXLODENABLE
));
555 fd6_emit_shader(ring
, ds
);
556 fd6_emit_immediates(screen
, ds
, ring
);
557 fd6_emit_link_map(screen
, hs
, ds
, ring
);
559 shader_info
*hs_info
= &hs
->shader
->nir
->info
;
560 OUT_PKT4(ring
, REG_A6XX_PC_TESS_NUM_VERTEX
, 1);
561 OUT_RING(ring
, hs_info
->tess
.tcs_vertices_out
);
563 /* Total attribute slots in HS incoming patch. */
564 OUT_PKT4(ring
, REG_A6XX_PC_UNKNOWN_9801
, 1);
565 OUT_RING(ring
, hs_info
->tess
.tcs_vertices_out
* vs
->output_size
/ 4);
567 OUT_PKT4(ring
, REG_A6XX_SP_HS_UNKNOWN_A831
, 1);
568 OUT_RING(ring
, vs
->output_size
);
570 shader_info
*ds_info
= &ds
->shader
->nir
->info
;
571 OUT_PKT4(ring
, REG_A6XX_PC_TESS_CNTL
, 1);
573 if (ds_info
->tess
.point_mode
)
574 output
= TESS_POINTS
;
575 else if (ds_info
->tess
.primitive_mode
== GL_ISOLINES
)
577 else if (ds_info
->tess
.ccw
)
578 output
= TESS_CCW_TRIS
;
580 output
= TESS_CW_TRIS
;
582 OUT_RING(ring
, A6XX_PC_TESS_CNTL_SPACING(fd6_gl2spacing(ds_info
->tess
.spacing
)) |
583 A6XX_PC_TESS_CNTL_OUTPUT(output
));
585 /* xxx: Misc tess unknowns: */
586 OUT_PKT4(ring
, REG_A6XX_VPC_UNKNOWN_9103
, 1);
587 OUT_RING(ring
, 0x00ffff00);
589 OUT_PKT4(ring
, REG_A6XX_VPC_UNKNOWN_9106
, 1);
590 OUT_RING(ring
, 0x0000ffff);
592 OUT_PKT4(ring
, REG_A6XX_GRAS_UNKNOWN_809D
, 1);
595 OUT_PKT4(ring
, REG_A6XX_GRAS_UNKNOWN_8002
, 1);
598 OUT_PKT4(ring
, REG_A6XX_VPC_PACK
, 1);
599 OUT_RING(ring
, A6XX_VPC_PACK_POSITIONLOC(pos_loc
) |
600 A6XX_VPC_PACK_PSIZELOC(255) |
601 A6XX_VPC_PACK_STRIDE_IN_VPC(l
.max_loc
));
603 OUT_PKT4(ring
, REG_A6XX_VPC_PACK_3
, 1);
604 OUT_RING(ring
, A6XX_VPC_PACK_3_POSITIONLOC(pos_loc
) |
605 A6XX_VPC_PACK_3_PSIZELOC(psize_loc
) |
606 A6XX_VPC_PACK_3_STRIDE_IN_VPC(l
.max_loc
));
608 OUT_PKT4(ring
, REG_A6XX_SP_DS_PRIMITIVE_CNTL
, 1);
609 OUT_RING(ring
, A6XX_SP_DS_PRIMITIVE_CNTL_DSOUT(l
.cnt
));
611 OUT_PKT4(ring
, REG_A6XX_PC_PRIMITIVE_CNTL_4
, 1);
612 OUT_RING(ring
, A6XX_PC_PRIMITIVE_CNTL_4_STRIDE_IN_VPC(l
.max_loc
) |
613 CONDREG(psize_regid
, 0x100));
616 OUT_PKT4(ring
, REG_A6XX_SP_HS_UNKNOWN_A831
, 1);
620 OUT_PKT4(ring
, REG_A6XX_SP_PRIMITIVE_CNTL
, 1);
621 OUT_RING(ring
, A6XX_SP_PRIMITIVE_CNTL_VSOUT(l
.cnt
));
623 bool enable_varyings
= fs
->total_in
> 0;
625 OUT_PKT4(ring
, REG_A6XX_VPC_CNTL_0
, 1);
626 OUT_RING(ring
, A6XX_VPC_CNTL_0_NUMNONPOSVAR(fs
->total_in
) |
627 COND(enable_varyings
, A6XX_VPC_CNTL_0_VARYING
) |
628 A6XX_VPC_CNTL_0_PRIMIDLOC(l
.primid_loc
) |
629 A6XX_VPC_CNTL_0_UNKLOC(0xff));
631 OUT_PKT4(ring
, REG_A6XX_PC_PRIMITIVE_CNTL_1
, 1);
632 OUT_RING(ring
, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(l
.max_loc
) |
633 CONDREG(psize_regid
, A6XX_PC_PRIMITIVE_CNTL_1_PSIZE
));
635 OUT_PKT4(ring
, REG_A6XX_PC_PRIMITIVE_CNTL_3
, 1);
638 OUT_PKT4(ring
, REG_A6XX_HLSQ_CONTROL_1_REG
, 5);
639 OUT_RING(ring
, 0x7); /* XXX */
640 OUT_RING(ring
, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid
) |
641 A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid
) |
642 A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(smask_in_regid
) |
643 A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_size_regid
));
644 OUT_RING(ring
, A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL(ij_pix_regid
) |
645 A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID(ij_cent_regid
) |
646 0xfc00fc00); /* XXX */
647 OUT_RING(ring
, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid
) |
648 A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid
) |
649 A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP(ij_samp_regid
) |
650 0x0000fc00); /* XXX */
651 OUT_RING(ring
, 0xfc); /* XXX */
653 OUT_PKT4(ring
, REG_A6XX_HLSQ_UNKNOWN_B980
, 1);
654 OUT_RING(ring
, enable_varyings
? 3 : 1);
656 OUT_PKT4(ring
, REG_A6XX_SP_FS_CTRL_REG0
, 1);
657 OUT_RING(ring
, A6XX_SP_FS_CTRL_REG0_THREADSIZE(fssz
) |
658 COND(enable_varyings
, A6XX_SP_FS_CTRL_REG0_VARYING
) |
660 A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fs
->info
.max_reg
+ 1) |
661 A6XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(fs
->info
.max_half_reg
+ 1) |
662 COND(fs
->mergedregs
, A6XX_SP_FS_CTRL_REG0_MERGEDREGS
) |
663 A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(fs
->branchstack
) |
664 COND(fs
->need_pixlod
, A6XX_SP_FS_CTRL_REG0_PIXLODENABLE
));
666 OUT_PKT4(ring
, REG_A6XX_SP_UNKNOWN_A982
, 1);
667 OUT_RING(ring
, 0); /* XXX */
669 OUT_PKT4(ring
, REG_A6XX_VPC_GS_SIV_CNTL
, 1);
670 OUT_RING(ring
, 0x0000ffff); /* XXX */
672 OUT_PKT4(ring
, REG_A6XX_GRAS_CNTL
, 1);
674 CONDREG(ij_pix_regid
, A6XX_GRAS_CNTL_VARYING
) |
675 CONDREG(ij_cent_regid
, A6XX_GRAS_CNTL_CENTROID
) |
676 CONDREG(ij_samp_regid
, A6XX_GRAS_CNTL_PERSAMP_VARYING
) |
677 COND(VALIDREG(ij_size_regid
) && !sample_shading
, A6XX_GRAS_CNTL_SIZE
) |
678 COND(VALIDREG(ij_size_regid
) && sample_shading
, A6XX_GRAS_CNTL_SIZE_PERSAMP
) |
679 COND(fs
->fragcoord_compmask
!= 0, A6XX_GRAS_CNTL_SIZE
|
680 A6XX_GRAS_CNTL_COORD_MASK(fs
->fragcoord_compmask
)) |
681 COND(fs
->frag_face
, A6XX_GRAS_CNTL_SIZE
));
683 OUT_PKT4(ring
, REG_A6XX_RB_RENDER_CONTROL0
, 2);
685 CONDREG(ij_pix_regid
, A6XX_RB_RENDER_CONTROL0_VARYING
) |
686 CONDREG(ij_cent_regid
, A6XX_RB_RENDER_CONTROL0_CENTROID
) |
687 CONDREG(ij_samp_regid
, A6XX_RB_RENDER_CONTROL0_PERSAMP_VARYING
) |
688 COND(enable_varyings
, A6XX_RB_RENDER_CONTROL0_UNK10
) |
689 COND(VALIDREG(ij_size_regid
) && !sample_shading
, A6XX_RB_RENDER_CONTROL0_SIZE
) |
690 COND(VALIDREG(ij_size_regid
) && sample_shading
, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP
) |
691 COND(fs
->fragcoord_compmask
!= 0, A6XX_RB_RENDER_CONTROL0_SIZE
|
692 A6XX_RB_RENDER_CONTROL0_COORD_MASK(fs
->fragcoord_compmask
)) |
693 COND(fs
->frag_face
, A6XX_RB_RENDER_CONTROL0_SIZE
));
696 CONDREG(smask_in_regid
, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK
) |
697 CONDREG(samp_id_regid
, A6XX_RB_RENDER_CONTROL1_SAMPLEID
) |
698 CONDREG(ij_size_regid
, A6XX_RB_RENDER_CONTROL1_SIZE
) |
699 COND(fs
->frag_face
, A6XX_RB_RENDER_CONTROL1_FACENESS
));
701 OUT_PKT4(ring
, REG_A6XX_RB_SAMPLE_CNTL
, 1);
702 OUT_RING(ring
, COND(sample_shading
, A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE
));
704 OUT_PKT4(ring
, REG_A6XX_GRAS_UNKNOWN_8101
, 1);
705 OUT_RING(ring
, COND(sample_shading
, 0x6)); // XXX
707 OUT_PKT4(ring
, REG_A6XX_GRAS_SAMPLE_CNTL
, 1);
708 OUT_RING(ring
, COND(sample_shading
, A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE
));
710 OUT_PKT4(ring
, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
711 for (i
= 0; i
< 8; i
++) {
712 OUT_RING(ring
, A6XX_SP_FS_OUTPUT_REG_REGID(color_regid
[i
]) |
713 COND(color_regid
[i
] & HALF_REG_ID
, A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION
));
716 OUT_PKT4(ring
, REG_A6XX_VPC_PACK
, 1);
717 OUT_RING(ring
, A6XX_VPC_PACK_POSITIONLOC(pos_loc
) |
718 A6XX_VPC_PACK_PSIZELOC(psize_loc
) |
719 A6XX_VPC_PACK_STRIDE_IN_VPC(l
.max_loc
));
722 OUT_PKT4(ring
, REG_A6XX_SP_GS_CTRL_REG0
, 1);
723 OUT_RING(ring
, A6XX_SP_GS_CTRL_REG0_THREADSIZE(TWO_QUADS
) |
724 A6XX_SP_GS_CTRL_REG0_FULLREGFOOTPRINT(gs
->info
.max_reg
+ 1) |
725 A6XX_SP_GS_CTRL_REG0_HALFREGFOOTPRINT(gs
->info
.max_half_reg
+ 1) |
726 COND(gs
->mergedregs
, A6XX_SP_GS_CTRL_REG0_MERGEDREGS
) |
727 A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(gs
->branchstack
) |
728 COND(gs
->need_pixlod
, A6XX_SP_GS_CTRL_REG0_PIXLODENABLE
));
730 fd6_emit_shader(ring
, gs
);
731 fd6_emit_immediates(screen
, gs
, ring
);
733 fd6_emit_link_map(screen
, ds
, gs
, ring
);
735 fd6_emit_link_map(screen
, vs
, gs
, ring
);
737 OUT_PKT4(ring
, REG_A6XX_VPC_PACK_GS
, 1);
738 OUT_RING(ring
, A6XX_VPC_PACK_GS_POSITIONLOC(pos_loc
) |
739 A6XX_VPC_PACK_GS_PSIZELOC(psize_loc
) |
740 A6XX_VPC_PACK_GS_STRIDE_IN_VPC(l
.max_loc
));
742 OUT_PKT4(ring
, REG_A6XX_VPC_UNKNOWN_9105
, 1);
743 OUT_RING(ring
, A6XX_VPC_UNKNOWN_9105_LAYERLOC(layer_loc
) | 0xff00);
745 OUT_PKT4(ring
, REG_A6XX_GRAS_UNKNOWN_809C
, 1);
746 OUT_RING(ring
, CONDREG(layer_regid
, A6XX_GRAS_UNKNOWN_809C_GS_WRITES_LAYER
));
748 uint32_t flags_regid
= ir3_find_output_regid(gs
, VARYING_SLOT_GS_VERTEX_FLAGS_IR3
);
750 OUT_PKT4(ring
, REG_A6XX_SP_PRIMITIVE_CNTL_GS
, 1);
751 OUT_RING(ring
, A6XX_SP_PRIMITIVE_CNTL_GS_GSOUT(l
.cnt
) |
752 A6XX_SP_PRIMITIVE_CNTL_GS_FLAGS_REGID(flags_regid
));
754 OUT_PKT4(ring
, REG_A6XX_PC_PRIMITIVE_CNTL_2
, 1);
755 OUT_RING(ring
, A6XX_PC_PRIMITIVE_CNTL_2_STRIDE_IN_VPC(l
.max_loc
) |
756 CONDREG(psize_regid
, A6XX_PC_PRIMITIVE_CNTL_2_PSIZE
) |
757 CONDREG(layer_regid
, A6XX_PC_PRIMITIVE_CNTL_2_LAYER
) |
758 CONDREG(primitive_regid
, A6XX_PC_PRIMITIVE_CNTL_2_PRIMITIVE_ID
));
761 switch (gs
->shader
->nir
->info
.gs
.output_primitive
) {
763 output
= TESS_POINTS
;
768 case GL_TRIANGLE_STRIP
:
769 output
= TESS_CW_TRIS
;
774 OUT_PKT4(ring
, REG_A6XX_PC_PRIMITIVE_CNTL_5
, 1);
776 A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(gs
->shader
->nir
->info
.gs
.vertices_out
- 1) |
777 A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(output
) |
778 A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(gs
->shader
->nir
->info
.gs
.invocations
- 1));
780 OUT_PKT4(ring
, REG_A6XX_GRAS_UNKNOWN_8003
, 1);
783 OUT_PKT4(ring
, REG_A6XX_VPC_UNKNOWN_9100
, 1);
784 OUT_RING(ring
, 0xff);
786 OUT_PKT4(ring
, REG_A6XX_VPC_UNKNOWN_9102
, 1);
787 OUT_RING(ring
, 0xffff00);
789 const struct ir3_shader_variant
*prev
= state
->ds
? state
->ds
: state
->vs
;
791 /* Size of per-primitive alloction in ldlw memory in vec4s. */
793 gs
->shader
->nir
->info
.gs
.vertices_in
*
794 DIV_ROUND_UP(prev
->output_size
, 4);
795 OUT_PKT4(ring
, REG_A6XX_PC_PRIMITIVE_CNTL_6
, 1);
796 OUT_RING(ring
, A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC(vec4_size
));
798 OUT_PKT4(ring
, REG_A6XX_PC_UNKNOWN_9B07
, 1);
801 OUT_PKT4(ring
, REG_A6XX_SP_GS_PRIM_SIZE
, 1);
802 OUT_RING(ring
, prev
->output_size
);
804 OUT_PKT4(ring
, REG_A6XX_PC_PRIMITIVE_CNTL_6
, 1);
806 OUT_PKT4(ring
, REG_A6XX_SP_GS_PRIM_SIZE
, 1);
810 OUT_PKT4(ring
, REG_A6XX_VPC_UNKNOWN_9101
, 1);
811 OUT_RING(ring
, 0xffff00);
813 OUT_PKT4(ring
, REG_A6XX_VPC_UNKNOWN_9107
, 1);
817 fd6_emit_shader(ring
, fs
);
819 OUT_PKT4(ring
, REG_A6XX_PC_PRIMID_CNTL
, 1);
820 OUT_RING(ring
, COND(primid_passthru
, A6XX_PC_PRIMID_CNTL_PRIMID_PASSTHRU
));
822 uint32_t non_sysval_input_count
= 0;
823 for (uint32_t i
= 0; i
< vs
->inputs_count
; i
++)
824 if (!vs
->inputs
[i
].sysval
)
825 non_sysval_input_count
++;
827 OUT_PKT4(ring
, REG_A6XX_VFD_CONTROL_0
, 1);
828 OUT_RING(ring
, A6XX_VFD_CONTROL_0_FETCH_CNT(non_sysval_input_count
) |
829 A6XX_VFD_CONTROL_0_DECODE_CNT(non_sysval_input_count
));
831 OUT_PKT4(ring
, REG_A6XX_VFD_DEST_CNTL(0), non_sysval_input_count
);
832 for (uint32_t i
= 0; i
< non_sysval_input_count
; i
++) {
833 assert(vs
->inputs
[i
].compmask
);
834 OUT_RING(ring
, A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK(vs
->inputs
[i
].compmask
) |
835 A6XX_VFD_DEST_CNTL_INSTR_REGID(vs
->inputs
[i
].regid
));
838 OUT_PKT4(ring
, REG_A6XX_VFD_CONTROL_1
, 6);
839 OUT_RING(ring
, A6XX_VFD_CONTROL_1_REGID4VTX(vertex_regid
) |
840 A6XX_VFD_CONTROL_1_REGID4INST(instance_regid
) |
841 A6XX_VFD_CONTROL_1_REGID4PRIMID(primitive_regid
) |
843 OUT_RING(ring
, A6XX_VFD_CONTROL_2_REGID_HSPATCHID(hs_patch_regid
) |
844 A6XX_VFD_CONTROL_2_REGID_INVOCATIONID(hs_invocation_regid
));
845 OUT_RING(ring
, A6XX_VFD_CONTROL_3_REGID_DSPATCHID(ds_patch_regid
) |
846 A6XX_VFD_CONTROL_3_REGID_TESSX(tess_coord_x_regid
) |
847 A6XX_VFD_CONTROL_3_REGID_TESSY(tess_coord_y_regid
) |
849 OUT_RING(ring
, 0x000000fc); /* VFD_CONTROL_4 */
850 OUT_RING(ring
, A6XX_VFD_CONTROL_5_REGID_GSHEADER(gs_header_regid
) |
851 0xfc00); /* VFD_CONTROL_5 */
853 COND(primid_passthru
, A6XX_VFD_CONTROL_6_PRIMID_PASSTHRU
)); /* VFD_CONTROL_6 */
856 fd6_emit_immediates(screen
, fs
, ring
);
859 static void emit_interp_state(struct fd_ringbuffer
*ring
, struct ir3_shader_variant
*fs
,
860 bool rasterflat
, bool sprite_coord_mode
, uint32_t sprite_coord_enable
);
862 static struct fd_ringbuffer
*
863 create_interp_stateobj(struct fd_context
*ctx
, struct fd6_program_state
*state
)
865 struct fd_ringbuffer
*ring
= fd_ringbuffer_new_object(ctx
->pipe
, 18 * 4);
867 emit_interp_state(ring
, state
->fs
, false, false, 0);
872 /* build the program streaming state which is not part of the pre-
873 * baked stateobj because of dependency on other gl state (rasterflat
874 * or sprite-coord-replacement)
876 struct fd_ringbuffer
*
877 fd6_program_interp_state(struct fd6_emit
*emit
)
879 const struct fd6_program_state
*state
= fd6_emit_get_prog(emit
);
881 if (!unlikely(emit
->rasterflat
|| emit
->sprite_coord_enable
)) {
883 return fd_ringbuffer_ref(state
->interp_stateobj
);
885 struct fd_ringbuffer
*ring
= fd_submit_new_ringbuffer(
886 emit
->ctx
->batch
->submit
, 18 * 4, FD_RINGBUFFER_STREAMING
);
888 emit_interp_state(ring
, state
->fs
, emit
->rasterflat
,
889 emit
->sprite_coord_mode
, emit
->sprite_coord_enable
);
896 emit_interp_state(struct fd_ringbuffer
*ring
, struct ir3_shader_variant
*fs
,
897 bool rasterflat
, bool sprite_coord_mode
, uint32_t sprite_coord_enable
)
899 uint32_t vinterp
[8], vpsrepl
[8];
901 memset(vinterp
, 0, sizeof(vinterp
));
902 memset(vpsrepl
, 0, sizeof(vpsrepl
));
904 for (int j
= -1; (j
= ir3_next_varying(fs
, j
)) < (int)fs
->inputs_count
; ) {
906 /* NOTE: varyings are packed, so if compmask is 0xb
907 * then first, third, and fourth component occupy
908 * three consecutive varying slots:
910 unsigned compmask
= fs
->inputs
[j
].compmask
;
912 uint32_t inloc
= fs
->inputs
[j
].inloc
;
914 if ((fs
->inputs
[j
].interpolate
== INTERP_MODE_FLAT
) ||
915 (fs
->inputs
[j
].rasterflat
&& rasterflat
)) {
916 uint32_t loc
= inloc
;
918 for (int i
= 0; i
< 4; i
++) {
919 if (compmask
& (1 << i
)) {
920 vinterp
[loc
/ 16] |= 1 << ((loc
% 16) * 2);
926 bool coord_mode
= sprite_coord_mode
;
927 if (ir3_point_sprite(fs
, j
, sprite_coord_enable
, &coord_mode
)) {
928 /* mask is two 2-bit fields, where:
931 * '11' -> 1 - T (flip mode)
933 unsigned mask
= coord_mode
? 0b1101 : 0b1001;
934 uint32_t loc
= inloc
;
935 if (compmask
& 0x1) {
936 vpsrepl
[loc
/ 16] |= ((mask
>> 0) & 0x3) << ((loc
% 16) * 2);
939 if (compmask
& 0x2) {
940 vpsrepl
[loc
/ 16] |= ((mask
>> 2) & 0x3) << ((loc
% 16) * 2);
943 if (compmask
& 0x4) {
945 vinterp
[loc
/ 16] |= 0b10 << ((loc
% 16) * 2);
948 if (compmask
& 0x8) {
950 vinterp
[loc
/ 16] |= 0b11 << ((loc
% 16) * 2);
956 OUT_PKT4(ring
, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
957 for (int i
= 0; i
< 8; i
++)
958 OUT_RING(ring
, vinterp
[i
]); /* VPC_VARYING_INTERP[i].MODE */
960 OUT_PKT4(ring
, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
961 for (int i
= 0; i
< 8; i
++)
962 OUT_RING(ring
, vpsrepl
[i
]); /* VPC_VARYING_PS_REPL[i] */
965 static struct ir3_program_state
*
966 fd6_program_create(void *data
, struct ir3_shader_variant
*bs
,
967 struct ir3_shader_variant
*vs
,
968 struct ir3_shader_variant
*hs
,
969 struct ir3_shader_variant
*ds
,
970 struct ir3_shader_variant
*gs
,
971 struct ir3_shader_variant
*fs
,
972 const struct ir3_shader_key
*key
)
974 struct fd_context
*ctx
= data
;
975 struct fd6_program_state
*state
= CALLOC_STRUCT(fd6_program_state
);
977 /* if we have streamout, use full VS in binning pass, as the
978 * binning pass VS will have outputs on other than position/psize
981 state
->bs
= vs
->shader
->stream_output
.num_outputs
? vs
: bs
;
987 state
->config_stateobj
= fd_ringbuffer_new_object(ctx
->pipe
, 0x1000);
988 state
->binning_stateobj
= fd_ringbuffer_new_object(ctx
->pipe
, 0x1000);
989 state
->stateobj
= fd_ringbuffer_new_object(ctx
->pipe
, 0x1000);
990 state
->streamout_stateobj
= fd_ringbuffer_new_object(ctx
->pipe
, 0x1000);
995 for (unsigned i
= 0; i
< bs
->inputs_count
; i
++) {
996 if (vs
->inputs
[i
].sysval
)
998 debug_assert(bs
->inputs
[i
].regid
== vs
->inputs
[i
].regid
);
1003 setup_config_stateobj(state
->config_stateobj
, state
);
1004 setup_stateobj(state
->binning_stateobj
, ctx
->screen
, state
, key
, true);
1005 setup_stateobj(state
->stateobj
, ctx
->screen
, state
, key
, false);
1006 state
->interp_stateobj
= create_interp_stateobj(ctx
, state
);
1008 return &state
->base
;
1012 fd6_program_destroy(void *data
, struct ir3_program_state
*state
)
1014 struct fd6_program_state
*so
= fd6_program_state(state
);
1015 fd_ringbuffer_del(so
->stateobj
);
1016 fd_ringbuffer_del(so
->binning_stateobj
);
1017 fd_ringbuffer_del(so
->config_stateobj
);
1018 fd_ringbuffer_del(so
->interp_stateobj
);
1019 fd_ringbuffer_del(so
->streamout_stateobj
);
1023 static const struct ir3_cache_funcs cache_funcs
= {
1024 .create_state
= fd6_program_create
,
1025 .destroy_state
= fd6_program_destroy
,
1029 fd6_shader_state_create(struct pipe_context
*pctx
, const struct pipe_shader_state
*cso
)
1031 return ir3_shader_state_create(pctx
, cso
);
1035 fd6_shader_state_delete(struct pipe_context
*pctx
, void *hwcso
)
1037 struct fd_context
*ctx
= fd_context(pctx
);
1038 ir3_cache_invalidate(fd6_context(ctx
)->shader_cache
, hwcso
);
1039 ir3_shader_state_delete(pctx
, hwcso
);
1043 fd6_prog_init(struct pipe_context
*pctx
)
1045 struct fd_context
*ctx
= fd_context(pctx
);
1047 fd6_context(ctx
)->shader_cache
= ir3_cache_create(&cache_funcs
, ctx
);
1049 pctx
->create_vs_state
= fd6_shader_state_create
;
1050 pctx
->delete_vs_state
= fd6_shader_state_delete
;
1052 pctx
->create_tcs_state
= fd6_shader_state_create
;
1053 pctx
->delete_tcs_state
= fd6_shader_state_delete
;
1055 pctx
->create_tes_state
= fd6_shader_state_create
;
1056 pctx
->delete_tes_state
= fd6_shader_state_delete
;
1058 pctx
->create_gs_state
= fd6_shader_state_create
;
1059 pctx
->delete_gs_state
= fd6_shader_state_delete
;
1061 pctx
->create_gs_state
= fd6_shader_state_create
;
1062 pctx
->delete_gs_state
= fd6_shader_state_delete
;
1064 pctx
->create_fs_state
= fd6_shader_state_create
;
1065 pctx
->delete_fs_state
= fd6_shader_state_delete
;