2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25 * Rob Clark <robclark@freedesktop.org>
28 #include "pipe/p_state.h"
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_inlines.h"
32 #include "util/u_format.h"
33 #include "util/bitset.h"
35 #include "freedreno_program.h"
37 #include "fd6_program.h"
39 #include "fd6_texture.h"
40 #include "fd6_format.h"
42 static struct ir3_shader
*
43 create_shader_stateobj(struct pipe_context
*pctx
, const struct pipe_shader_state
*cso
,
46 struct fd_context
*ctx
= fd_context(pctx
);
47 struct ir3_compiler
*compiler
= ctx
->screen
->compiler
;
48 return ir3_shader_create(compiler
, cso
, type
, &ctx
->debug
, pctx
->screen
);
52 fd6_fp_state_create(struct pipe_context
*pctx
,
53 const struct pipe_shader_state
*cso
)
55 return create_shader_stateobj(pctx
, cso
, MESA_SHADER_FRAGMENT
);
59 fd6_fp_state_delete(struct pipe_context
*pctx
, void *hwcso
)
61 struct ir3_shader
*so
= hwcso
;
62 struct fd_context
*ctx
= fd_context(pctx
);
63 ir3_cache_invalidate(fd6_context(ctx
)->shader_cache
, hwcso
);
64 ir3_shader_destroy(so
);
68 fd6_vp_state_create(struct pipe_context
*pctx
,
69 const struct pipe_shader_state
*cso
)
71 return create_shader_stateobj(pctx
, cso
, MESA_SHADER_VERTEX
);
75 fd6_vp_state_delete(struct pipe_context
*pctx
, void *hwcso
)
77 struct ir3_shader
*so
= hwcso
;
78 struct fd_context
*ctx
= fd_context(pctx
);
79 ir3_cache_invalidate(fd6_context(ctx
)->shader_cache
, hwcso
);
80 ir3_shader_destroy(so
);
84 fd6_emit_shader(struct fd_ringbuffer
*ring
, const struct ir3_shader_variant
*so
)
86 const struct ir3_info
*si
= &so
->info
;
87 enum a6xx_state_block sb
= fd6_stage2shadersb(so
->type
);
88 enum a6xx_state_src src
;
92 if (fd_mesa_debug
& FD_DBG_DIRECT
) {
95 bin
= fd_bo_map(so
->bo
);
103 case MESA_SHADER_VERTEX
:
104 opcode
= CP_LOAD_STATE6_GEOM
;
106 case MESA_SHADER_FRAGMENT
:
107 case MESA_SHADER_COMPUTE
:
108 case MESA_SHADER_KERNEL
:
109 opcode
= CP_LOAD_STATE6_FRAG
;
112 unreachable("bad shader type");
115 OUT_PKT7(ring
, opcode
, 3 + sz
);
116 OUT_RING(ring
, CP_LOAD_STATE6_0_DST_OFF(0) |
117 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER
) |
118 CP_LOAD_STATE6_0_STATE_SRC(src
) |
119 CP_LOAD_STATE6_0_STATE_BLOCK(sb
) |
120 CP_LOAD_STATE6_0_NUM_UNIT(so
->instrlen
));
122 OUT_RING(ring
, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
123 OUT_RING(ring
, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
125 OUT_RELOCD(ring
, so
->bo
, 0, 0, 0);
128 /* for how clever coverity is, it is sometimes rather dull, and
129 * doesn't realize that the only case where bin==NULL, sz==0:
131 assume(bin
|| (sz
== 0));
133 for (i
= 0; i
< sz
; i
++) {
134 OUT_RING(ring
, bin
[i
]);
138 /* Add any missing varyings needed for stream-out. Otherwise varyings not
139 * used by fragment shader will be stripped out.
142 link_stream_out(struct ir3_shader_linkage
*l
, const struct ir3_shader_variant
*v
)
144 const struct ir3_stream_output_info
*strmout
= &v
->shader
->stream_output
;
147 * First, any stream-out varyings not already in linkage map (ie. also
148 * consumed by frag shader) need to be added:
150 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
151 const struct ir3_stream_output
*out
= &strmout
->output
[i
];
152 unsigned k
= out
->register_index
;
154 (1 << (out
->num_components
+ out
->start_component
)) - 1;
155 unsigned idx
, nextloc
= 0;
157 /* psize/pos need to be the last entries in linkage map, and will
158 * get added link_stream_out, so skip over them:
160 if ((v
->outputs
[k
].slot
== VARYING_SLOT_PSIZ
) ||
161 (v
->outputs
[k
].slot
== VARYING_SLOT_POS
))
164 for (idx
= 0; idx
< l
->cnt
; idx
++) {
165 if (l
->var
[idx
].regid
== v
->outputs
[k
].regid
)
167 nextloc
= MAX2(nextloc
, l
->var
[idx
].loc
+ 4);
170 /* add if not already in linkage map: */
172 ir3_link_add(l
, v
->outputs
[k
].regid
, compmask
, nextloc
);
174 /* expand component-mask if needed, ie streaming out all components
175 * but frag shader doesn't consume all components:
177 if (compmask
& ~l
->var
[idx
].compmask
) {
178 l
->var
[idx
].compmask
|= compmask
;
179 l
->max_loc
= MAX2(l
->max_loc
,
180 l
->var
[idx
].loc
+ util_last_bit(l
->var
[idx
].compmask
));
186 setup_stream_out(struct fd6_program_state
*state
, const struct ir3_shader_variant
*v
,
187 struct ir3_shader_linkage
*l
)
189 const struct ir3_stream_output_info
*strmout
= &v
->shader
->stream_output
;
190 struct fd6_streamout_state
*tf
= &state
->tf
;
192 memset(tf
, 0, sizeof(*tf
));
194 tf
->prog_count
= align(l
->max_loc
, 2) / 2;
196 debug_assert(tf
->prog_count
< ARRAY_SIZE(tf
->prog
));
198 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
199 const struct ir3_stream_output
*out
= &strmout
->output
[i
];
200 unsigned k
= out
->register_index
;
203 tf
->ncomp
[out
->output_buffer
] += out
->num_components
;
205 /* linkage map sorted by order frag shader wants things, so
206 * a bit less ideal here..
208 for (idx
= 0; idx
< l
->cnt
; idx
++)
209 if (l
->var
[idx
].regid
== v
->outputs
[k
].regid
)
212 debug_assert(idx
< l
->cnt
);
214 for (unsigned j
= 0; j
< out
->num_components
; j
++) {
215 unsigned c
= j
+ out
->start_component
;
216 unsigned loc
= l
->var
[idx
].loc
+ c
;
217 unsigned off
= j
+ out
->dst_offset
; /* in dwords */
220 tf
->prog
[loc
/2] |= A6XX_VPC_SO_PROG_B_EN
|
221 A6XX_VPC_SO_PROG_B_BUF(out
->output_buffer
) |
222 A6XX_VPC_SO_PROG_B_OFF(off
* 4);
224 tf
->prog
[loc
/2] |= A6XX_VPC_SO_PROG_A_EN
|
225 A6XX_VPC_SO_PROG_A_BUF(out
->output_buffer
) |
226 A6XX_VPC_SO_PROG_A_OFF(off
* 4);
231 tf
->vpc_so_buf_cntl
= A6XX_VPC_SO_BUF_CNTL_ENABLE
|
232 COND(tf
->ncomp
[0] > 0, A6XX_VPC_SO_BUF_CNTL_BUF0
) |
233 COND(tf
->ncomp
[1] > 0, A6XX_VPC_SO_BUF_CNTL_BUF1
) |
234 COND(tf
->ncomp
[2] > 0, A6XX_VPC_SO_BUF_CNTL_BUF2
) |
235 COND(tf
->ncomp
[3] > 0, A6XX_VPC_SO_BUF_CNTL_BUF3
);
239 const struct ir3_shader_variant
*v
;
240 const struct ir3_info
*i
;
241 /* const sizes are in units of vec4, aligned to 4*vec4 */
243 /* instr sizes are in units of 16 instructions */
257 setup_stages(struct fd6_program_state
*state
, struct stage
*s
, bool binning_pass
)
262 static const struct ir3_shader_variant dummy_fs
= {0};
271 s
[HS
].v
= s
[DS
].v
= s
[GS
].v
= NULL
; /* for now */
273 for (i
= 0; i
< MAX_STAGES
; i
++) {
275 s
[i
].i
= &s
[i
].v
->info
;
276 s
[i
].constlen
= align(s
[i
].v
->constlen
, 4);
277 /* instrlen is already in units of 16 instr.. although
278 * probably we should ditch that and not make the compiler
279 * care about instruction group size of a3xx vs a5xx
281 s
[i
].instrlen
= s
[i
].v
->instrlen
;
289 /* since we share the constant state w/ VS we need to make sure
290 * constlen is sufficiently large for full VS, even if the binning
291 * pass shader doesn't use them all
294 s
[VS
].constlen
= MAX2(s
[VS
].constlen
, align(state
->bs
->constlen
, 4));
296 /* It should be impossible for VS to have smaller constlen than BS
297 * since BS is just a subset of VS.
299 debug_assert(s
[VS
].constlen
>= state
->bs
->constlen
);
303 static inline uint32_t
304 next_regid(uint32_t reg
, uint32_t increment
)
306 if (reg
== regid(63,0))
309 return reg
+ increment
;
312 #define VALIDREG(r) ((r) != regid(63,0))
313 #define CONDREG(r, val) COND(VALIDREG(r), (val))
316 setup_stateobj(struct fd_ringbuffer
*ring
, struct fd6_program_state
*state
,
317 const struct ir3_shader_key
*key
, bool binning_pass
)
319 struct stage s
[MAX_STAGES
];
320 uint32_t pos_regid
, psize_regid
, color_regid
[8], posz_regid
;
321 uint32_t face_regid
, coord_regid
, zwcoord_regid
, samp_id_regid
;
322 uint32_t smask_in_regid
, smask_regid
;
323 uint32_t vertex_regid
, instance_regid
;
324 uint32_t ij_pix_regid
, ij_samp_regid
, ij_cent_regid
, ij_size_regid
;
325 enum a3xx_threadsize fssz
;
326 uint8_t psize_loc
= ~0;
331 setup_stages(state
, s
, binning_pass
);
333 bool sample_shading
= s
[FS
].v
->per_samp
| key
->sample_shading
;
337 pos_regid
= ir3_find_output_regid(s
[VS
].v
, VARYING_SLOT_POS
);
338 psize_regid
= ir3_find_output_regid(s
[VS
].v
, VARYING_SLOT_PSIZ
);
339 vertex_regid
= ir3_find_sysval_regid(s
[VS
].v
, SYSTEM_VALUE_VERTEX_ID
);
340 instance_regid
= ir3_find_sysval_regid(s
[VS
].v
, SYSTEM_VALUE_INSTANCE_ID
);
342 if (s
[FS
].v
->color0_mrt
) {
343 color_regid
[0] = color_regid
[1] = color_regid
[2] = color_regid
[3] =
344 color_regid
[4] = color_regid
[5] = color_regid
[6] = color_regid
[7] =
345 ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_COLOR
);
347 color_regid
[0] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA0
);
348 color_regid
[1] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA1
);
349 color_regid
[2] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA2
);
350 color_regid
[3] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA3
);
351 color_regid
[4] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA4
);
352 color_regid
[5] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA5
);
353 color_regid
[6] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA6
);
354 color_regid
[7] = ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DATA7
);
357 samp_id_regid
= ir3_find_sysval_regid(s
[FS
].v
, SYSTEM_VALUE_SAMPLE_ID
);
358 smask_in_regid
= ir3_find_sysval_regid(s
[FS
].v
, SYSTEM_VALUE_SAMPLE_MASK_IN
);
359 face_regid
= ir3_find_sysval_regid(s
[FS
].v
, SYSTEM_VALUE_FRONT_FACE
);
360 coord_regid
= ir3_find_sysval_regid(s
[FS
].v
, SYSTEM_VALUE_FRAG_COORD
);
361 zwcoord_regid
= next_regid(coord_regid
, 2);
362 ij_pix_regid
= ir3_find_sysval_regid(s
[FS
].v
, SYSTEM_VALUE_BARYCENTRIC_PIXEL
);
363 ij_samp_regid
= ir3_find_sysval_regid(s
[FS
].v
, SYSTEM_VALUE_BARYCENTRIC_SAMPLE
);
364 ij_cent_regid
= ir3_find_sysval_regid(s
[FS
].v
, SYSTEM_VALUE_BARYCENTRIC_CENTROID
);
365 ij_size_regid
= ir3_find_sysval_regid(s
[FS
].v
, SYSTEM_VALUE_BARYCENTRIC_SIZE
);
366 posz_regid
= ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_DEPTH
);
367 smask_regid
= ir3_find_output_regid(s
[FS
].v
, FRAG_RESULT_SAMPLE_MASK
);
369 /* we can't write gl_SampleMask for !msaa.. if b0 is zero then we
370 * end up masking the single sample!!
373 smask_regid
= regid(63, 0);
375 /* we could probably divide this up into things that need to be
376 * emitted if frag-prog is dirty vs if vert-prog is dirty..
379 OUT_PKT4(ring
, REG_A6XX_SP_VS_CONFIG
, 2);
380 OUT_RING(ring
, COND(s
[VS
].v
, A6XX_SP_VS_CONFIG_ENABLED
) |
381 A6XX_SP_VS_CONFIG_NIBO(s
[VS
].v
->image_mapping
.num_ibo
) |
382 A6XX_SP_VS_CONFIG_NTEX(s
[VS
].v
->num_samp
) |
383 A6XX_SP_VS_CONFIG_NSAMP(s
[VS
].v
->num_samp
)); /* SP_VS_CONFIG */
384 OUT_RING(ring
, s
[VS
].instrlen
); /* SP_VS_INSTRLEN */
386 OUT_PKT4(ring
, REG_A6XX_SP_HS_UNKNOWN_A831
, 1);
389 OUT_PKT4(ring
, REG_A6XX_SP_HS_CONFIG
, 2);
390 OUT_RING(ring
, COND(s
[HS
].v
, A6XX_SP_HS_CONFIG_ENABLED
)); /* SP_HS_CONFIG */
391 OUT_RING(ring
, s
[HS
].instrlen
); /* SP_HS_INSTRLEN */
393 OUT_PKT4(ring
, REG_A6XX_SP_DS_CONFIG
, 2);
394 OUT_RING(ring
, COND(s
[DS
].v
, A6XX_SP_DS_CONFIG_ENABLED
)); /* SP_DS_CONFIG */
395 OUT_RING(ring
, s
[DS
].instrlen
); /* SP_DS_INSTRLEN */
397 OUT_PKT4(ring
, REG_A6XX_SP_GS_UNKNOWN_A871
, 1);
400 OUT_PKT4(ring
, REG_A6XX_SP_GS_CONFIG
, 2);
401 OUT_RING(ring
, COND(s
[GS
].v
, A6XX_SP_GS_CONFIG_ENABLED
)); /* SP_GS_CONFIG */
402 OUT_RING(ring
, s
[GS
].instrlen
); /* SP_GS_INSTRLEN */
404 OUT_PKT4(ring
, REG_A6XX_SP_UNKNOWN_A99E
, 1);
405 OUT_RING(ring
, 0x7fc0);
407 OUT_PKT4(ring
, REG_A6XX_SP_UNKNOWN_A9A8
, 1);
410 OUT_PKT4(ring
, REG_A6XX_SP_UNKNOWN_AB00
, 1);
413 OUT_PKT4(ring
, REG_A6XX_SP_FS_CONFIG
, 2);
414 OUT_RING(ring
, COND(s
[FS
].v
, A6XX_SP_FS_CONFIG_ENABLED
) |
415 A6XX_SP_FS_CONFIG_NIBO(s
[FS
].v
->image_mapping
.num_ibo
) |
416 A6XX_SP_FS_CONFIG_NTEX(s
[FS
].v
->num_samp
) |
417 A6XX_SP_FS_CONFIG_NSAMP(s
[FS
].v
->num_samp
)); /* SP_FS_CONFIG */
418 OUT_RING(ring
, s
[FS
].instrlen
); /* SP_FS_INSTRLEN */
420 OUT_PKT4(ring
, REG_A6XX_SP_FS_OUTPUT_CNTL0
, 1);
421 OUT_RING(ring
, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid
) |
422 A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid
) |
425 OUT_PKT4(ring
, REG_A6XX_HLSQ_VS_CNTL
, 4);
426 OUT_RING(ring
, A6XX_HLSQ_VS_CNTL_CONSTLEN(s
[VS
].constlen
) |
427 A6XX_HLSQ_VS_CNTL_ENABLED
);
428 OUT_RING(ring
, A6XX_HLSQ_HS_CNTL_CONSTLEN(s
[HS
].constlen
)); /* HLSQ_HS_CONSTLEN */
429 OUT_RING(ring
, A6XX_HLSQ_DS_CNTL_CONSTLEN(s
[DS
].constlen
)); /* HLSQ_DS_CONSTLEN */
430 OUT_RING(ring
, A6XX_HLSQ_GS_CNTL_CONSTLEN(s
[GS
].constlen
)); /* HLSQ_GS_CONSTLEN */
432 OUT_PKT4(ring
, REG_A6XX_HLSQ_FS_CNTL
, 1);
433 OUT_RING(ring
, A6XX_HLSQ_FS_CNTL_CONSTLEN(s
[FS
].constlen
) |
434 A6XX_HLSQ_FS_CNTL_ENABLED
);
436 OUT_PKT4(ring
, REG_A6XX_SP_VS_CTRL_REG0
, 1);
437 OUT_RING(ring
, A6XX_SP_VS_CTRL_REG0_THREADSIZE(fssz
) |
438 A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(s
[VS
].i
->max_reg
+ 1) |
439 A6XX_SP_VS_CTRL_REG0_MERGEDREGS
|
440 A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(s
[VS
].v
->branchstack
) |
441 COND(s
[VS
].v
->need_pixlod
, A6XX_SP_VS_CTRL_REG0_PIXLODENABLE
));
443 struct ir3_shader_linkage l
= {0};
444 ir3_link_shaders(&l
, s
[VS
].v
, s
[FS
].v
);
446 if ((s
[VS
].v
->shader
->stream_output
.num_outputs
> 0) && !binning_pass
)
447 link_stream_out(&l
, s
[VS
].v
);
449 BITSET_DECLARE(varbs
, 128) = {0};
450 uint32_t *varmask
= (uint32_t *)varbs
;
452 for (i
= 0; i
< l
.cnt
; i
++)
453 for (j
= 0; j
< util_last_bit(l
.var
[i
].compmask
); j
++)
454 BITSET_SET(varbs
, l
.var
[i
].loc
+ j
);
456 OUT_PKT4(ring
, REG_A6XX_VPC_VAR_DISABLE(0), 4);
457 OUT_RING(ring
, ~varmask
[0]); /* VPC_VAR[0].DISABLE */
458 OUT_RING(ring
, ~varmask
[1]); /* VPC_VAR[1].DISABLE */
459 OUT_RING(ring
, ~varmask
[2]); /* VPC_VAR[2].DISABLE */
460 OUT_RING(ring
, ~varmask
[3]); /* VPC_VAR[3].DISABLE */
462 /* a6xx appends pos/psize to end of the linkage map: */
463 if (VALIDREG(pos_regid
))
464 ir3_link_add(&l
, pos_regid
, 0xf, l
.max_loc
);
466 if (VALIDREG(psize_regid
)) {
467 psize_loc
= l
.max_loc
;
468 ir3_link_add(&l
, psize_regid
, 0x1, l
.max_loc
);
471 if ((s
[VS
].v
->shader
->stream_output
.num_outputs
> 0) && !binning_pass
) {
472 setup_stream_out(state
, s
[VS
].v
, &l
);
475 for (i
= 0, j
= 0; (i
< 16) && (j
< l
.cnt
); i
++) {
478 OUT_PKT4(ring
, REG_A6XX_SP_VS_OUT_REG(i
), 1);
480 reg
|= A6XX_SP_VS_OUT_REG_A_REGID(l
.var
[j
].regid
);
481 reg
|= A6XX_SP_VS_OUT_REG_A_COMPMASK(l
.var
[j
].compmask
);
484 reg
|= A6XX_SP_VS_OUT_REG_B_REGID(l
.var
[j
].regid
);
485 reg
|= A6XX_SP_VS_OUT_REG_B_COMPMASK(l
.var
[j
].compmask
);
491 for (i
= 0, j
= 0; (i
< 8) && (j
< l
.cnt
); i
++) {
494 OUT_PKT4(ring
, REG_A6XX_SP_VS_VPC_DST_REG(i
), 1);
496 reg
|= A6XX_SP_VS_VPC_DST_REG_OUTLOC0(l
.var
[j
++].loc
);
497 reg
|= A6XX_SP_VS_VPC_DST_REG_OUTLOC1(l
.var
[j
++].loc
);
498 reg
|= A6XX_SP_VS_VPC_DST_REG_OUTLOC2(l
.var
[j
++].loc
);
499 reg
|= A6XX_SP_VS_VPC_DST_REG_OUTLOC3(l
.var
[j
++].loc
);
504 OUT_PKT4(ring
, REG_A6XX_SP_VS_OBJ_START_LO
, 2);
505 OUT_RELOC(ring
, s
[VS
].v
->bo
, 0, 0, 0); /* SP_VS_OBJ_START_LO/HI */
508 fd6_emit_shader(ring
, s
[VS
].v
);
510 // TODO depending on other bits in this reg (if any) set somewhere else?
512 OUT_PKT4(ring
, REG_A6XX_PC_PRIM_VTX_CNTL
, 1);
513 OUT_RING(ring
, COND(s
[VS
].v
->writes_psize
, A6XX_PC_PRIM_VTX_CNTL_PSIZE
));
516 OUT_PKT4(ring
, REG_A6XX_SP_PRIMITIVE_CNTL
, 1);
517 OUT_RING(ring
, A6XX_SP_PRIMITIVE_CNTL_VSOUT(l
.cnt
));
519 bool enable_varyings
= s
[FS
].v
->total_in
> 0;
521 OUT_PKT4(ring
, REG_A6XX_VPC_CNTL_0
, 1);
522 OUT_RING(ring
, A6XX_VPC_CNTL_0_NUMNONPOSVAR(s
[FS
].v
->total_in
) |
523 COND(enable_varyings
, A6XX_VPC_CNTL_0_VARYING
) |
526 OUT_PKT4(ring
, REG_A6XX_PC_PRIMITIVE_CNTL_1
, 1);
527 OUT_RING(ring
, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(l
.max_loc
) |
528 CONDREG(psize_regid
, 0x100));
531 OUT_PKT4(ring
, REG_A6XX_SP_FS_OBJ_START_LO
, 2);
532 OUT_RING(ring
, 0x00000000); /* SP_FS_OBJ_START_LO */
533 OUT_RING(ring
, 0x00000000); /* SP_FS_OBJ_START_HI */
535 OUT_PKT4(ring
, REG_A6XX_SP_FS_OBJ_START_LO
, 2);
536 OUT_RELOC(ring
, s
[FS
].v
->bo
, 0, 0, 0); /* SP_FS_OBJ_START_LO/HI */
539 OUT_PKT4(ring
, REG_A6XX_HLSQ_CONTROL_1_REG
, 5);
540 OUT_RING(ring
, 0x7); /* XXX */
541 OUT_RING(ring
, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid
) |
542 A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid
) |
543 A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(smask_in_regid
) |
544 A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_size_regid
));
545 OUT_RING(ring
, A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL(ij_pix_regid
) |
546 A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID(ij_cent_regid
) |
547 0xfc00fc00); /* XXX */
548 OUT_RING(ring
, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid
) |
549 A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid
) |
550 A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP(ij_samp_regid
) |
551 0x0000fc00); /* XXX */
552 OUT_RING(ring
, 0xfc); /* XXX */
554 OUT_PKT4(ring
, REG_A6XX_HLSQ_UNKNOWN_B980
, 1);
555 OUT_RING(ring
, enable_varyings
? 3 : 1);
557 OUT_PKT4(ring
, REG_A6XX_SP_FS_CTRL_REG0
, 1);
558 OUT_RING(ring
, A6XX_SP_FS_CTRL_REG0_THREADSIZE(fssz
) |
559 COND(enable_varyings
, A6XX_SP_FS_CTRL_REG0_VARYING
) |
560 COND(s
[FS
].v
->frag_coord
, A6XX_SP_FS_CTRL_REG0_VARYING
) |
562 A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(s
[FS
].i
->max_reg
+ 1) |
563 A6XX_SP_FS_CTRL_REG0_MERGEDREGS
|
564 A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(s
[FS
].v
->branchstack
) |
565 COND(s
[FS
].v
->need_pixlod
, A6XX_SP_FS_CTRL_REG0_PIXLODENABLE
));
567 OUT_PKT4(ring
, REG_A6XX_SP_UNKNOWN_A982
, 1);
568 OUT_RING(ring
, 0); /* XXX */
570 OUT_PKT4(ring
, REG_A6XX_HLSQ_UPDATE_CNTL
, 1);
571 OUT_RING(ring
, 0xff); /* XXX */
573 OUT_PKT4(ring
, REG_A6XX_VPC_GS_SIV_CNTL
, 1);
574 OUT_RING(ring
, 0x0000ffff); /* XXX */
577 OUT_PKT4(ring
, REG_A6XX_SP_SP_CNTL
, 1);
578 OUT_RING(ring
, 0x00000010); /* XXX */
581 OUT_PKT4(ring
, REG_A6XX_GRAS_CNTL
, 1);
583 CONDREG(ij_pix_regid
, A6XX_GRAS_CNTL_VARYING
) |
584 CONDREG(ij_cent_regid
, A6XX_GRAS_CNTL_CENTROID
) |
585 CONDREG(ij_samp_regid
, A6XX_GRAS_CNTL_PERSAMP_VARYING
) |
586 COND(VALIDREG(ij_size_regid
) && !sample_shading
, A6XX_GRAS_CNTL_SIZE
) |
587 COND(VALIDREG(ij_size_regid
) && sample_shading
, A6XX_GRAS_CNTL_SIZE_PERSAMP
) |
588 COND(s
[FS
].v
->frag_coord
,
589 A6XX_GRAS_CNTL_SIZE
|
590 A6XX_GRAS_CNTL_XCOORD
|
591 A6XX_GRAS_CNTL_YCOORD
|
592 A6XX_GRAS_CNTL_ZCOORD
|
593 A6XX_GRAS_CNTL_WCOORD
) |
594 COND(s
[FS
].v
->frag_face
, A6XX_GRAS_CNTL_SIZE
));
596 OUT_PKT4(ring
, REG_A6XX_RB_RENDER_CONTROL0
, 2);
598 CONDREG(ij_pix_regid
, A6XX_RB_RENDER_CONTROL0_VARYING
) |
599 CONDREG(ij_cent_regid
, A6XX_RB_RENDER_CONTROL0_CENTROID
) |
600 CONDREG(ij_samp_regid
, A6XX_RB_RENDER_CONTROL0_PERSAMP_VARYING
) |
601 COND(enable_varyings
, A6XX_RB_RENDER_CONTROL0_UNK10
) |
602 COND(VALIDREG(ij_size_regid
) && !sample_shading
, A6XX_RB_RENDER_CONTROL0_SIZE
) |
603 COND(VALIDREG(ij_size_regid
) && sample_shading
, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP
) |
604 COND(s
[FS
].v
->frag_coord
,
605 A6XX_RB_RENDER_CONTROL0_SIZE
|
606 A6XX_RB_RENDER_CONTROL0_XCOORD
|
607 A6XX_RB_RENDER_CONTROL0_YCOORD
|
608 A6XX_RB_RENDER_CONTROL0_ZCOORD
|
609 A6XX_RB_RENDER_CONTROL0_WCOORD
) |
610 COND(s
[FS
].v
->frag_face
, A6XX_RB_RENDER_CONTROL0_SIZE
));
613 CONDREG(smask_in_regid
, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK
) |
614 CONDREG(samp_id_regid
, A6XX_RB_RENDER_CONTROL1_SAMPLEID
) |
615 CONDREG(ij_size_regid
, A6XX_RB_RENDER_CONTROL1_SIZE
) |
616 COND(s
[FS
].v
->frag_face
, A6XX_RB_RENDER_CONTROL1_FACENESS
));
618 OUT_PKT4(ring
, REG_A6XX_RB_SAMPLE_CNTL
, 1);
619 OUT_RING(ring
, COND(sample_shading
, A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE
));
621 OUT_PKT4(ring
, REG_A6XX_GRAS_UNKNOWN_8101
, 1);
622 OUT_RING(ring
, COND(sample_shading
, 0x6)); // XXX
624 OUT_PKT4(ring
, REG_A6XX_GRAS_SAMPLE_CNTL
, 1);
625 OUT_RING(ring
, COND(sample_shading
, A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE
));
627 OUT_PKT4(ring
, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
628 for (i
= 0; i
< 8; i
++) {
629 OUT_RING(ring
, A6XX_SP_FS_OUTPUT_REG_REGID(color_regid
[i
]) |
630 COND(color_regid
[i
] & HALF_REG_ID
, A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION
));
633 OUT_PKT4(ring
, REG_A6XX_VPC_PACK
, 1);
634 OUT_RING(ring
, A6XX_VPC_PACK_NUMNONPOSVAR(s
[FS
].v
->total_in
) |
635 A6XX_VPC_PACK_PSIZELOC(psize_loc
) |
636 A6XX_VPC_PACK_STRIDE_IN_VPC(l
.max_loc
));
639 /* figure out VARYING_INTERP / VARYING_PS_REPL register values: */
640 for (j
= -1; (j
= ir3_next_varying(s
[FS
].v
, j
)) < (int)s
[FS
].v
->inputs_count
; ) {
641 /* NOTE: varyings are packed, so if compmask is 0xb
642 * then first, third, and fourth component occupy
643 * three consecutive varying slots:
645 unsigned compmask
= s
[FS
].v
->inputs
[j
].compmask
;
647 uint32_t inloc
= s
[FS
].v
->inputs
[j
].inloc
;
649 if (s
[FS
].v
->inputs
[j
].interpolate
== INTERP_MODE_FLAT
) {
650 uint32_t loc
= inloc
;
652 for (i
= 0; i
< 4; i
++) {
653 if (compmask
& (1 << i
)) {
654 state
->vinterp
[loc
/ 16] |= 1 << ((loc
% 16) * 2);
664 fd6_emit_shader(ring
, s
[FS
].v
);
666 OUT_PKT4(ring
, REG_A6XX_VFD_CONTROL_1
, 6);
667 OUT_RING(ring
, A6XX_VFD_CONTROL_1_REGID4VTX(vertex_regid
) |
668 A6XX_VFD_CONTROL_1_REGID4INST(instance_regid
) |
670 OUT_RING(ring
, 0x0000fcfc); /* VFD_CONTROL_2 */
671 OUT_RING(ring
, 0xfcfcfcfc); /* VFD_CONTROL_3 */
672 OUT_RING(ring
, 0x000000fc); /* VFD_CONTROL_4 */
673 OUT_RING(ring
, 0x0000fcfc); /* VFD_CONTROL_5 */
674 OUT_RING(ring
, 0x00000000); /* VFD_CONTROL_6 */
676 bool fragz
= s
[FS
].v
->no_earlyz
| s
[FS
].v
->writes_pos
;
678 OUT_PKT4(ring
, REG_A6XX_RB_DEPTH_PLANE_CNTL
, 1);
679 OUT_RING(ring
, COND(fragz
, A6XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z
));
681 OUT_PKT4(ring
, REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL
, 1);
682 OUT_RING(ring
, COND(fragz
, A6XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z
));
685 /* emits the program state which is not part of the stateobj because of
686 * dependency on other gl state (rasterflat or sprite-coord-replacement)
689 fd6_program_emit(struct fd_ringbuffer
*ring
, struct fd6_emit
*emit
)
691 const struct fd6_program_state
*state
= fd6_emit_get_prog(emit
);
693 if (!unlikely(emit
->rasterflat
|| emit
->sprite_coord_enable
)) {
695 OUT_PKT4(ring
, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
696 for (int i
= 0; i
< 8; i
++)
697 OUT_RING(ring
, state
->vinterp
[i
]); /* VPC_VARYING_INTERP[i].MODE */
699 OUT_PKT4(ring
, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
700 for (int i
= 0; i
< 8; i
++)
701 OUT_RING(ring
, 0x00000000); /* VPC_VARYING_PS_REPL[i] */
704 struct ir3_shader_variant
*fs
= state
->fs
;
705 uint32_t vinterp
[8], vpsrepl
[8];
707 memset(vinterp
, 0, sizeof(vinterp
));
708 memset(vpsrepl
, 0, sizeof(vpsrepl
));
710 for (int j
= -1; (j
= ir3_next_varying(fs
, j
)) < (int)fs
->inputs_count
; ) {
712 /* NOTE: varyings are packed, so if compmask is 0xb
713 * then first, third, and fourth component occupy
714 * three consecutive varying slots:
716 unsigned compmask
= fs
->inputs
[j
].compmask
;
718 uint32_t inloc
= fs
->inputs
[j
].inloc
;
720 if ((fs
->inputs
[j
].interpolate
== INTERP_MODE_FLAT
) ||
721 (fs
->inputs
[j
].rasterflat
&& emit
->rasterflat
)) {
722 uint32_t loc
= inloc
;
724 for (int i
= 0; i
< 4; i
++) {
725 if (compmask
& (1 << i
)) {
726 vinterp
[loc
/ 16] |= 1 << ((loc
% 16) * 2);
732 gl_varying_slot slot
= fs
->inputs
[j
].slot
;
734 /* since we don't enable PIPE_CAP_TGSI_TEXCOORD: */
735 if (slot
>= VARYING_SLOT_VAR0
) {
736 unsigned texmask
= 1 << (slot
- VARYING_SLOT_VAR0
);
737 /* Replace the .xy coordinates with S/T from the point sprite. Set
738 * interpolation bits for .zw such that they become .01
740 if (emit
->sprite_coord_enable
& texmask
) {
741 /* mask is two 2-bit fields, where:
744 * '11' -> 1 - T (flip mode)
746 unsigned mask
= emit
->sprite_coord_mode
? 0b1101 : 0b1001;
747 uint32_t loc
= inloc
;
748 if (compmask
& 0x1) {
749 vpsrepl
[loc
/ 16] |= ((mask
>> 0) & 0x3) << ((loc
% 16) * 2);
752 if (compmask
& 0x2) {
753 vpsrepl
[loc
/ 16] |= ((mask
>> 2) & 0x3) << ((loc
% 16) * 2);
756 if (compmask
& 0x4) {
758 vinterp
[loc
/ 16] |= 0b10 << ((loc
% 16) * 2);
761 if (compmask
& 0x8) {
763 vinterp
[loc
/ 16] |= 0b11 << ((loc
% 16) * 2);
770 OUT_PKT4(ring
, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
771 for (int i
= 0; i
< 8; i
++)
772 OUT_RING(ring
, vinterp
[i
]); /* VPC_VARYING_INTERP[i].MODE */
774 OUT_PKT4(ring
, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
775 for (int i
= 0; i
< 8; i
++)
776 OUT_RING(ring
, vpsrepl
[i
]); /* VPC_VARYING_PS_REPL[i] */
780 static struct ir3_program_state
*
781 fd6_program_create(void *data
, struct ir3_shader_variant
*bs
,
782 struct ir3_shader_variant
*vs
,
783 struct ir3_shader_variant
*fs
,
784 const struct ir3_shader_key
*key
)
786 struct fd_context
*ctx
= data
;
787 struct fd6_program_state
*state
= CALLOC_STRUCT(fd6_program_state
);
792 state
->binning_stateobj
= fd_ringbuffer_new_object(ctx
->pipe
, 0x1000);
793 state
->stateobj
= fd_ringbuffer_new_object(ctx
->pipe
, 0x1000);
795 setup_stateobj(state
->binning_stateobj
, state
, key
, true);
796 setup_stateobj(state
->stateobj
, state
, key
, false);
802 fd6_program_destroy(void *data
, struct ir3_program_state
*state
)
804 struct fd6_program_state
*so
= fd6_program_state(state
);
805 fd_ringbuffer_del(so
->stateobj
);
806 fd_ringbuffer_del(so
->binning_stateobj
);
810 static const struct ir3_cache_funcs cache_funcs
= {
811 .create_state
= fd6_program_create
,
812 .destroy_state
= fd6_program_destroy
,
816 fd6_prog_init(struct pipe_context
*pctx
)
818 struct fd_context
*ctx
= fd_context(pctx
);
820 fd6_context(ctx
)->shader_cache
= ir3_cache_create(&cache_funcs
, ctx
);
822 pctx
->create_fs_state
= fd6_fp_state_create
;
823 pctx
->delete_fs_state
= fd6_fp_state_delete
;
825 pctx
->create_vs_state
= fd6_vp_state_create
;
826 pctx
->delete_vs_state
= fd6_vp_state_delete
;