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freedreno/a6xx: streamout
[mesa.git] / src / gallium / drivers / freedreno / a6xx / fd6_program.c
1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 * Authors:
25 * Rob Clark <robclark@freedesktop.org>
26 */
27
28 #include "pipe/p_state.h"
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_inlines.h"
32 #include "util/u_format.h"
33 #include "util/bitset.h"
34
35 #include "freedreno_program.h"
36
37 #include "fd6_program.h"
38 #include "fd6_emit.h"
39 #include "fd6_texture.h"
40 #include "fd6_format.h"
41
42 static void
43 delete_shader_stateobj(struct fd6_shader_stateobj *so)
44 {
45 ir3_shader_destroy(so->shader);
46 free(so);
47 }
48
49 static struct fd6_shader_stateobj *
50 create_shader_stateobj(struct pipe_context *pctx, const struct pipe_shader_state *cso,
51 enum shader_t type)
52 {
53 struct fd_context *ctx = fd_context(pctx);
54 struct ir3_compiler *compiler = ctx->screen->compiler;
55 struct fd6_shader_stateobj *so = CALLOC_STRUCT(fd6_shader_stateobj);
56 so->shader = ir3_shader_create(compiler, cso, type, &ctx->debug);
57 return so;
58 }
59
60 static void *
61 fd6_fp_state_create(struct pipe_context *pctx,
62 const struct pipe_shader_state *cso)
63 {
64 return create_shader_stateobj(pctx, cso, SHADER_FRAGMENT);
65 }
66
67 static void
68 fd6_fp_state_delete(struct pipe_context *pctx, void *hwcso)
69 {
70 struct fd6_shader_stateobj *so = hwcso;
71 delete_shader_stateobj(so);
72 }
73
74 static void *
75 fd6_vp_state_create(struct pipe_context *pctx,
76 const struct pipe_shader_state *cso)
77 {
78 return create_shader_stateobj(pctx, cso, SHADER_VERTEX);
79 }
80
81 static void
82 fd6_vp_state_delete(struct pipe_context *pctx, void *hwcso)
83 {
84 struct fd6_shader_stateobj *so = hwcso;
85 delete_shader_stateobj(so);
86 }
87
88 void
89 fd6_emit_shader(struct fd_ringbuffer *ring, const struct ir3_shader_variant *so)
90 {
91 const struct ir3_info *si = &so->info;
92 enum a6xx_state_block sb = fd6_stage2shadersb(so->type);
93 enum a6xx_state_src src;
94 uint32_t i, sz, *bin;
95 unsigned opcode;
96
97 if (fd_mesa_debug & FD_DBG_DIRECT) {
98 sz = si->sizedwords;
99 src = SS6_DIRECT;
100 bin = fd_bo_map(so->bo);
101 } else {
102 sz = 0;
103 src = SS6_INDIRECT;
104 bin = NULL;
105 }
106
107 switch (so->type) {
108 case SHADER_VERTEX:
109 opcode = CP_LOAD_STATE6_GEOM;
110 break;
111 case SHADER_FRAGMENT:
112 case SHADER_COMPUTE:
113 opcode = CP_LOAD_STATE6_FRAG;
114 break;
115 default:
116 unreachable("bad shader type");
117 }
118
119 OUT_PKT7(ring, opcode, 3 + sz);
120 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
121 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
122 CP_LOAD_STATE6_0_STATE_SRC(src) |
123 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
124 CP_LOAD_STATE6_0_NUM_UNIT(so->instrlen));
125 if (bin) {
126 OUT_RING(ring, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
127 OUT_RING(ring, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
128 } else {
129 OUT_RELOC(ring, so->bo, 0, 0, 0);
130 }
131
132 /* for how clever coverity is, it is sometimes rather dull, and
133 * doesn't realize that the only case where bin==NULL, sz==0:
134 */
135 assume(bin || (sz == 0));
136
137 for (i = 0; i < sz; i++) {
138 OUT_RING(ring, bin[i]);
139 }
140 }
141
142 /* Add any missing varyings needed for stream-out. Otherwise varyings not
143 * used by fragment shader will be stripped out.
144 */
145 static void
146 link_stream_out(struct ir3_shader_linkage *l, const struct ir3_shader_variant *v)
147 {
148 const struct pipe_stream_output_info *strmout = &v->shader->stream_output;
149
150 /*
151 * First, any stream-out varyings not already in linkage map (ie. also
152 * consumed by frag shader) need to be added:
153 */
154 for (unsigned i = 0; i < strmout->num_outputs; i++) {
155 const struct pipe_stream_output *out = &strmout->output[i];
156 unsigned k = out->register_index;
157 unsigned compmask =
158 (1 << (out->num_components + out->start_component)) - 1;
159 unsigned idx, nextloc = 0;
160
161 /* psize/pos need to be the last entries in linkage map, and will
162 * get added link_stream_out, so skip over them:
163 */
164 if ((v->outputs[k].slot == VARYING_SLOT_PSIZ) ||
165 (v->outputs[k].slot == VARYING_SLOT_POS))
166 continue;
167
168 for (idx = 0; idx < l->cnt; idx++) {
169 if (l->var[idx].regid == v->outputs[k].regid)
170 break;
171 nextloc = MAX2(nextloc, l->var[idx].loc + 4);
172 }
173
174 /* add if not already in linkage map: */
175 if (idx == l->cnt)
176 ir3_link_add(l, v->outputs[k].regid, compmask, nextloc);
177
178 /* expand component-mask if needed, ie streaming out all components
179 * but frag shader doesn't consume all components:
180 */
181 if (compmask & ~l->var[idx].compmask) {
182 l->var[idx].compmask |= compmask;
183 l->max_loc = MAX2(l->max_loc,
184 l->var[idx].loc + util_last_bit(l->var[idx].compmask));
185 }
186 }
187 }
188
189 static void
190 setup_stream_out(struct fd_context *ctx, const struct ir3_shader_variant *v,
191 struct ir3_shader_linkage *l)
192 {
193 const struct pipe_stream_output_info *strmout = &v->shader->stream_output;
194 struct fd6_streamout_state *tf = &fd6_context(ctx)->tf;
195
196 memset(tf, 0, sizeof(*tf));
197
198 tf->prog_count = align(l->max_loc, 2) / 2;
199
200 debug_assert(tf->prog_count < ARRAY_SIZE(tf->prog));
201
202 for (unsigned i = 0; i < strmout->num_outputs; i++) {
203 const struct pipe_stream_output *out = &strmout->output[i];
204 unsigned k = out->register_index;
205 unsigned idx;
206
207 tf->ncomp[out->output_buffer] += out->num_components;
208
209 /* linkage map sorted by order frag shader wants things, so
210 * a bit less ideal here..
211 */
212 for (idx = 0; idx < l->cnt; idx++)
213 if (l->var[idx].regid == v->outputs[k].regid)
214 break;
215
216 debug_assert(idx < l->cnt);
217
218 for (unsigned j = 0; j < out->num_components; j++) {
219 unsigned c = j + out->start_component;
220 unsigned loc = l->var[idx].loc + c;
221 unsigned off = j + out->dst_offset; /* in dwords */
222
223 if (loc & 1) {
224 tf->prog[loc/2] |= A6XX_VPC_SO_PROG_B_EN |
225 A6XX_VPC_SO_PROG_B_BUF(out->output_buffer) |
226 A6XX_VPC_SO_PROG_B_OFF(off * 4);
227 } else {
228 tf->prog[loc/2] |= A6XX_VPC_SO_PROG_A_EN |
229 A6XX_VPC_SO_PROG_A_BUF(out->output_buffer) |
230 A6XX_VPC_SO_PROG_A_OFF(off * 4);
231 }
232 }
233 }
234
235 tf->vpc_so_buf_cntl = A6XX_VPC_SO_BUF_CNTL_ENABLE |
236 COND(tf->ncomp[0] > 0, A6XX_VPC_SO_BUF_CNTL_BUF0) |
237 COND(tf->ncomp[1] > 0, A6XX_VPC_SO_BUF_CNTL_BUF1) |
238 COND(tf->ncomp[2] > 0, A6XX_VPC_SO_BUF_CNTL_BUF2) |
239 COND(tf->ncomp[3] > 0, A6XX_VPC_SO_BUF_CNTL_BUF3);
240 }
241
242 struct stage {
243 const struct ir3_shader_variant *v;
244 const struct ir3_info *i;
245 /* const sizes are in units of 4 * vec4 */
246 uint8_t constoff;
247 uint8_t constlen;
248 /* instr sizes are in units of 16 instructions */
249 uint8_t instroff;
250 uint8_t instrlen;
251 };
252
253 enum {
254 VS = 0,
255 FS = 1,
256 HS = 2,
257 DS = 3,
258 GS = 4,
259 MAX_STAGES
260 };
261
262 static void
263 setup_stages(struct fd6_emit *emit, struct stage *s)
264 {
265 unsigned i;
266
267 s[VS].v = fd6_emit_get_vp(emit);
268 s[FS].v = fd6_emit_get_fp(emit);
269
270 s[HS].v = s[DS].v = s[GS].v = NULL; /* for now */
271
272 for (i = 0; i < MAX_STAGES; i++) {
273 if (s[i].v) {
274 s[i].i = &s[i].v->info;
275 /* constlen is in units of 4 * vec4: */
276 s[i].constlen = align(s[i].v->constlen, 4) / 4;
277 /* instrlen is already in units of 16 instr.. although
278 * probably we should ditch that and not make the compiler
279 * care about instruction group size of a3xx vs a5xx
280 */
281 s[i].instrlen = s[i].v->instrlen;
282 } else {
283 s[i].i = NULL;
284 s[i].constlen = 0;
285 s[i].instrlen = 0;
286 }
287 }
288
289 unsigned constoff = 0;
290 for (i = 0; i < MAX_STAGES; i++) {
291 s[i].constoff = constoff;
292 constoff += s[i].constlen;
293 }
294
295 s[VS].instroff = 0;
296 s[FS].instroff = 64 - s[FS].instrlen;
297 s[HS].instroff = s[DS].instroff = s[GS].instroff = s[FS].instroff;
298 }
299
300 void
301 fd6_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
302 struct fd6_emit *emit)
303 {
304 struct stage s[MAX_STAGES];
305 uint32_t pos_regid, psize_regid, color_regid[8];
306 uint32_t face_regid, coord_regid, zwcoord_regid, samp_id_regid, samp_mask_regid;
307 uint32_t vcoord_regid, vertex_regid, instance_regid;
308 enum a3xx_threadsize fssz;
309 uint8_t psize_loc = ~0;
310 int i, j;
311
312 setup_stages(emit, s);
313
314 fssz = (s[FS].i->max_reg >= 24) ? TWO_QUADS : FOUR_QUADS;
315
316 pos_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_POS);
317 psize_regid = ir3_find_output_regid(s[VS].v, VARYING_SLOT_PSIZ);
318 vertex_regid = ir3_find_sysval_regid(s[VS].v, SYSTEM_VALUE_VERTEX_ID_ZERO_BASE);
319 instance_regid = ir3_find_sysval_regid(s[VS].v, SYSTEM_VALUE_INSTANCE_ID);
320
321 if (s[FS].v->color0_mrt) {
322 color_regid[0] = color_regid[1] = color_regid[2] = color_regid[3] =
323 color_regid[4] = color_regid[5] = color_regid[6] = color_regid[7] =
324 ir3_find_output_regid(s[FS].v, FRAG_RESULT_COLOR);
325 } else {
326 color_regid[0] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA0);
327 color_regid[1] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA1);
328 color_regid[2] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA2);
329 color_regid[3] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA3);
330 color_regid[4] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA4);
331 color_regid[5] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA5);
332 color_regid[6] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA6);
333 color_regid[7] = ir3_find_output_regid(s[FS].v, FRAG_RESULT_DATA7);
334 }
335
336 samp_id_regid = ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_SAMPLE_ID);
337 samp_mask_regid = ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_SAMPLE_MASK_IN);
338 face_regid = ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_FRONT_FACE);
339 coord_regid = ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_FRAG_COORD);
340 zwcoord_regid = (coord_regid == regid(63,0)) ? regid(63,0) : (coord_regid + 2);
341 vcoord_regid = ir3_find_sysval_regid(s[FS].v, SYSTEM_VALUE_VARYING_COORD);
342
343 /* we could probably divide this up into things that need to be
344 * emitted if frag-prog is dirty vs if vert-prog is dirty..
345 */
346
347 OUT_PKT4(ring, REG_A6XX_SP_VS_TEX_COUNT, 1);
348 OUT_RING(ring, 0);
349
350 struct fd_texture_stateobj *tex = &ctx->tex[PIPE_SHADER_VERTEX];
351 OUT_PKT4(ring, REG_A6XX_SP_VS_CONFIG, 2);
352 OUT_RING(ring, COND(s[VS].v, A6XX_SP_VS_CONFIG_ENABLED) |
353 A6XX_SP_VS_CONFIG_NTEX(tex->num_textures) |
354 A6XX_SP_VS_CONFIG_NSAMP(tex->num_samplers)); /* SP_VS_CONFIG */
355 OUT_RING(ring, s[VS].instrlen); /* SP_VS_INSTRLEN */
356
357 OUT_PKT4(ring, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
358 OUT_RING(ring, 0);
359
360 OUT_PKT4(ring, REG_A6XX_SP_HS_CONFIG, 2);
361 OUT_RING(ring, COND(s[HS].v, A6XX_SP_HS_CONFIG_ENABLED)); /* SP_HS_CONFIG */
362 OUT_RING(ring, s[HS].instrlen); /* SP_HS_INSTRLEN */
363
364 OUT_PKT4(ring, REG_A6XX_SP_DS_CONFIG, 2);
365 OUT_RING(ring, COND(s[DS].v, A6XX_SP_DS_CONFIG_ENABLED)); /* SP_DS_CONFIG */
366 OUT_RING(ring, s[DS].instrlen); /* SP_DS_INSTRLEN */
367
368 OUT_PKT4(ring, REG_A6XX_SP_GS_UNKNOWN_A871, 1);
369 OUT_RING(ring, 0);
370
371 OUT_PKT4(ring, REG_A6XX_SP_GS_CONFIG, 2);
372 OUT_RING(ring, COND(s[GS].v, A6XX_SP_GS_CONFIG_ENABLED)); /* SP_GS_CONFIG */
373 OUT_RING(ring, s[GS].instrlen); /* SP_GS_INSTRLEN */
374
375 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A99E, 1);
376 OUT_RING(ring, 0x7fc0);
377
378 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A9A8, 1);
379 OUT_RING(ring, 0);
380
381 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_AB00, 1);
382 OUT_RING(ring, 0x5);
383
384 tex = &ctx->tex[PIPE_SHADER_FRAGMENT];
385 OUT_PKT4(ring, REG_A6XX_SP_FS_CONFIG, 2);
386 OUT_RING(ring, COND(s[FS].v, A6XX_SP_FS_CONFIG_ENABLED) |
387 A6XX_SP_FS_CONFIG_NTEX(tex->num_textures) |
388 A6XX_SP_FS_CONFIG_NSAMP(tex->num_samplers));
389 /* SP_FS_CONFIG */
390 OUT_RING(ring, s[FS].instrlen); /* SP_FS_INSTRLEN */
391
392 OUT_PKT4(ring, REG_A6XX_HLSQ_VS_CNTL, 4);
393 OUT_RING(ring, A6XX_HLSQ_VS_CNTL_CONSTLEN(align(s[VS].constlen, 4)) | 0x100); /* HLSQ_VS_CONSTLEN */
394 OUT_RING(ring, A6XX_HLSQ_HS_CNTL_CONSTLEN(align(s[HS].constlen, 4))); /* HLSQ_HS_CONSTLEN */
395 OUT_RING(ring, A6XX_HLSQ_DS_CNTL_CONSTLEN(align(s[DS].constlen, 4))); /* HLSQ_DS_CONSTLEN */
396 OUT_RING(ring, A6XX_HLSQ_GS_CNTL_CONSTLEN(align(s[GS].constlen, 4))); /* HLSQ_GS_CONSTLEN */
397
398 OUT_PKT4(ring, REG_A6XX_HLSQ_FS_CNTL, 1);
399 OUT_RING(ring, s[FS].constlen | 0x100); /* HLSQ_FS_CONSTLEN */
400
401 OUT_PKT4(ring, REG_A6XX_SP_VS_CTRL_REG0, 1);
402 OUT_RING(ring, A6XX_SP_VS_CTRL_REG0_THREADSIZE(fssz) |
403 A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(s[VS].i->max_reg + 1) |
404 A6XX_SP_VS_CTRL_REG0_MERGEDREGS |
405 A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(0x3) | // XXX need to figure this out somehow..
406 COND(s[VS].v->has_samp, A6XX_SP_VS_CTRL_REG0_PIXLODENABLE));
407
408 struct ir3_shader_linkage l = {0};
409 ir3_link_shaders(&l, s[VS].v, s[FS].v);
410
411 if ((s[VS].v->shader->stream_output.num_outputs > 0) &&
412 !emit->key.binning_pass)
413 link_stream_out(&l, s[VS].v);
414
415 BITSET_DECLARE(varbs, 128) = {0};
416 uint32_t *varmask = (uint32_t *)varbs;
417
418 for (i = 0; i < l.cnt; i++)
419 for (j = 0; j < util_last_bit(l.var[i].compmask); j++)
420 BITSET_SET(varbs, l.var[i].loc + j);
421
422 OUT_PKT4(ring, REG_A6XX_VPC_VAR_DISABLE(0), 4);
423 OUT_RING(ring, ~varmask[0]); /* VPC_VAR[0].DISABLE */
424 OUT_RING(ring, ~varmask[1]); /* VPC_VAR[1].DISABLE */
425 OUT_RING(ring, ~varmask[2]); /* VPC_VAR[2].DISABLE */
426 OUT_RING(ring, ~varmask[3]); /* VPC_VAR[3].DISABLE */
427
428 /* a6xx appends pos/psize to end of the linkage map: */
429 if (pos_regid != regid(63,0))
430 ir3_link_add(&l, pos_regid, 0xf, l.max_loc);
431
432 if (psize_regid != regid(63,0)) {
433 psize_loc = l.max_loc;
434 ir3_link_add(&l, psize_regid, 0x1, l.max_loc);
435 }
436
437 if ((s[VS].v->shader->stream_output.num_outputs > 0) &&
438 !emit->key.binning_pass) {
439 setup_stream_out(ctx, s[VS].v, &l);
440 }
441
442 for (i = 0, j = 0; (i < 16) && (j < l.cnt); i++) {
443 uint32_t reg = 0;
444
445 OUT_PKT4(ring, REG_A6XX_SP_VS_OUT_REG(i), 1);
446
447 reg |= A6XX_SP_VS_OUT_REG_A_REGID(l.var[j].regid);
448 reg |= A6XX_SP_VS_OUT_REG_A_COMPMASK(l.var[j].compmask);
449 j++;
450
451 reg |= A6XX_SP_VS_OUT_REG_B_REGID(l.var[j].regid);
452 reg |= A6XX_SP_VS_OUT_REG_B_COMPMASK(l.var[j].compmask);
453 j++;
454
455 OUT_RING(ring, reg);
456 }
457
458 for (i = 0, j = 0; (i < 8) && (j < l.cnt); i++) {
459 uint32_t reg = 0;
460
461 OUT_PKT4(ring, REG_A6XX_SP_VS_VPC_DST_REG(i), 1);
462
463 reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC0(l.var[j++].loc);
464 reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC1(l.var[j++].loc);
465 reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC2(l.var[j++].loc);
466 reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC3(l.var[j++].loc);
467
468 OUT_RING(ring, reg);
469 }
470
471 OUT_PKT4(ring, REG_A6XX_SP_VS_OBJ_START_LO, 2);
472 OUT_RELOC(ring, s[VS].v->bo, 0, 0, 0); /* SP_VS_OBJ_START_LO/HI */
473
474 if (s[VS].instrlen)
475 fd6_emit_shader(ring, s[VS].v);
476
477 // TODO depending on other bits in this reg (if any) set somewhere else?
478 #if 0
479 OUT_PKT4(ring, REG_A6XX_PC_PRIM_VTX_CNTL, 1);
480 OUT_RING(ring, COND(s[VS].v->writes_psize, A6XX_PC_PRIM_VTX_CNTL_PSIZE));
481 #endif
482
483 OUT_PKT4(ring, REG_A6XX_SP_PRIMITIVE_CNTL, 1);
484 OUT_RING(ring, A6XX_SP_PRIMITIVE_CNTL_VSOUT(l.cnt));
485
486 bool enable_varyings = s[FS].v->total_in > 0;
487
488 OUT_PKT4(ring, REG_A6XX_VPC_CNTL_0, 1);
489 OUT_RING(ring, A6XX_VPC_CNTL_0_NUMNONPOSVAR(s[FS].v->total_in) |
490 COND(enable_varyings, A6XX_VPC_CNTL_0_VARYING) |
491 0xff00ff00);
492
493 OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_1, 1);
494 OUT_RING(ring, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(l.max_loc) |
495 COND(psize_regid != regid(63,0), 0x100));
496
497 if (emit->key.binning_pass) {
498 OUT_PKT4(ring, REG_A6XX_SP_FS_OBJ_START_LO, 2);
499 OUT_RING(ring, 0x00000000); /* SP_FS_OBJ_START_LO */
500 OUT_RING(ring, 0x00000000); /* SP_FS_OBJ_START_HI */
501 } else {
502 OUT_PKT4(ring, REG_A6XX_SP_FS_OBJ_START_LO, 2);
503 OUT_RELOC(ring, s[FS].v->bo, 0, 0, 0); /* SP_FS_OBJ_START_LO/HI */
504 }
505
506 OUT_PKT4(ring, REG_A6XX_HLSQ_CONTROL_1_REG, 5);
507 OUT_RING(ring, 0x7); /* XXX */
508 OUT_RING(ring, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid) |
509 A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid) |
510 A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(samp_mask_regid) |
511 0xfc000000); /* XXX */
512 OUT_RING(ring, A6XX_HLSQ_CONTROL_3_REG_FRAGCOORDXYREGID(vcoord_regid) |
513 0xfcfcfc00); /* XXX */
514 OUT_RING(ring, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid) |
515 A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid) |
516 0x0000fcfc); /* XXX */
517 OUT_RING(ring, 0xfc); /* XXX */
518
519 OUT_PKT4(ring, REG_A6XX_HLSQ_UNKNOWN_B980, 1);
520 OUT_RING(ring, s[FS].v->total_in > 0 ? 3 : 1);
521
522 OUT_PKT4(ring, REG_A6XX_SP_FS_CTRL_REG0, 1);
523 OUT_RING(ring, A6XX_SP_FS_CTRL_REG0_THREADSIZE(fssz) |
524 COND(s[FS].v->total_in > 0, A6XX_SP_FS_CTRL_REG0_VARYING) |
525 COND(s[FS].v->frag_coord, A6XX_SP_FS_CTRL_REG0_VARYING) |
526 0x1000000 |
527 A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(s[FS].i->max_reg + 1) |
528 A6XX_SP_FS_CTRL_REG0_MERGEDREGS |
529 A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(0x3) | // XXX need to figure this out somehow..
530 COND(s[FS].v->has_samp, A6XX_SP_FS_CTRL_REG0_PIXLODENABLE));
531
532 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A982, 1);
533 OUT_RING(ring, 0); /* XXX */
534
535 OUT_PKT4(ring, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
536 OUT_RING(ring, 0xff); /* XXX */
537
538 OUT_PKT4(ring, REG_A6XX_VPC_GS_SIV_CNTL, 1);
539 OUT_RING(ring, 0x0000ffff); /* XXX */
540
541 #if 0
542 OUT_PKT4(ring, REG_A6XX_SP_SP_CNTL, 1);
543 OUT_RING(ring, 0x00000010); /* XXX */
544 #endif
545
546 OUT_PKT4(ring, REG_A6XX_GRAS_CNTL, 1);
547 OUT_RING(ring, COND(enable_varyings, A6XX_GRAS_CNTL_VARYING) |
548 COND(s[FS].v->frag_coord, A6XX_GRAS_CNTL_XCOORD |
549 A6XX_GRAS_CNTL_YCOORD |
550 A6XX_GRAS_CNTL_ZCOORD |
551 A6XX_GRAS_CNTL_WCOORD));
552
553 OUT_PKT4(ring, REG_A6XX_RB_RENDER_CONTROL0, 2);
554 OUT_RING(ring, COND(enable_varyings, A6XX_RB_RENDER_CONTROL0_VARYING |
555 A6XX_RB_RENDER_CONTROL0_UNK10) |
556 COND(s[FS].v->frag_coord, A6XX_RB_RENDER_CONTROL0_XCOORD |
557 A6XX_RB_RENDER_CONTROL0_YCOORD |
558 A6XX_RB_RENDER_CONTROL0_ZCOORD |
559 A6XX_RB_RENDER_CONTROL0_WCOORD));
560 OUT_RING(ring, COND(s[FS].v->frag_face, A6XX_RB_RENDER_CONTROL1_FACENESS));
561
562 OUT_PKT4(ring, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
563 for (i = 0; i < 8; i++) {
564 OUT_RING(ring, A6XX_SP_FS_OUTPUT_REG_REGID(color_regid[i]) |
565 COND(emit->key.half_precision,
566 A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION));
567 }
568
569 OUT_PKT4(ring, REG_A6XX_VPC_PACK, 1);
570 OUT_RING(ring, A6XX_VPC_PACK_NUMNONPOSVAR(s[FS].v->total_in) |
571 A6XX_VPC_PACK_PSIZELOC(psize_loc) |
572 A6XX_VPC_PACK_STRIDE_IN_VPC(l.max_loc));
573
574 if (!emit->key.binning_pass) {
575 uint32_t vinterp[8], vpsrepl[8];
576
577 memset(vinterp, 0, sizeof(vinterp));
578 memset(vpsrepl, 0, sizeof(vpsrepl));
579
580 /* looks like we need to do int varyings in the frag
581 * shader on a5xx (no flatshad reg? or a420.0 bug?):
582 *
583 * (sy)(ss)nop
584 * (sy)ldlv.u32 r0.x,l[r0.x], 1
585 * ldlv.u32 r0.y,l[r0.x+1], 1
586 * (ss)bary.f (ei)r63.x, 0, r0.x
587 * (ss)(rpt1)cov.s32f16 hr0.x, (r)r0.x
588 * (rpt5)nop
589 * sam (f16)(xyzw)hr0.x, hr0.x, s#0, t#0
590 *
591 * Possibly on later a5xx variants we'll be able to use
592 * something like the code below instead of workaround
593 * in the shader:
594 */
595 /* figure out VARYING_INTERP / VARYING_PS_REPL register values: */
596 for (j = -1; (j = ir3_next_varying(s[FS].v, j)) < (int)s[FS].v->inputs_count; ) {
597 /* NOTE: varyings are packed, so if compmask is 0xb
598 * then first, third, and fourth component occupy
599 * three consecutive varying slots:
600 */
601 unsigned compmask = s[FS].v->inputs[j].compmask;
602
603 uint32_t inloc = s[FS].v->inputs[j].inloc;
604
605 if ((s[FS].v->inputs[j].interpolate == INTERP_MODE_FLAT) ||
606 (s[FS].v->inputs[j].rasterflat && emit->rasterflat)) {
607 uint32_t loc = inloc;
608
609 for (i = 0; i < 4; i++) {
610 if (compmask & (1 << i)) {
611 vinterp[loc / 16] |= 1 << ((loc % 16) * 2);
612 //flatshade[loc / 32] |= 1 << (loc % 32);
613 loc++;
614 }
615 }
616 }
617
618 gl_varying_slot slot = s[FS].v->inputs[j].slot;
619
620 /* since we don't enable PIPE_CAP_TGSI_TEXCOORD: */
621 if (slot >= VARYING_SLOT_VAR0) {
622 unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
623 /* Replace the .xy coordinates with S/T from the point sprite. Set
624 * interpolation bits for .zw such that they become .01
625 */
626 if (emit->sprite_coord_enable & texmask) {
627 /* mask is two 2-bit fields, where:
628 * '01' -> S
629 * '10' -> T
630 * '11' -> 1 - T (flip mode)
631 */
632 unsigned mask = emit->sprite_coord_mode ? 0b1101 : 0b1001;
633 uint32_t loc = inloc;
634 if (compmask & 0x1) {
635 vpsrepl[loc / 16] |= ((mask >> 0) & 0x3) << ((loc % 16) * 2);
636 loc++;
637 }
638 if (compmask & 0x2) {
639 vpsrepl[loc / 16] |= ((mask >> 2) & 0x3) << ((loc % 16) * 2);
640 loc++;
641 }
642 if (compmask & 0x4) {
643 /* .z <- 0.0f */
644 vinterp[loc / 16] |= 0b10 << ((loc % 16) * 2);
645 loc++;
646 }
647 if (compmask & 0x8) {
648 /* .w <- 1.0f */
649 vinterp[loc / 16] |= 0b11 << ((loc % 16) * 2);
650 loc++;
651 }
652 }
653 }
654 }
655
656 OUT_PKT4(ring, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
657 for (i = 0; i < 8; i++)
658 OUT_RING(ring, vinterp[i]); /* VPC_VARYING_INTERP[i].MODE */
659
660 OUT_PKT4(ring, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
661 for (i = 0; i < 8; i++)
662 OUT_RING(ring, vpsrepl[i]); /* VPC_VARYING_PS_REPL[i] */
663 }
664
665 if (!emit->key.binning_pass)
666 if (s[FS].instrlen)
667 fd6_emit_shader(ring, s[FS].v);
668
669 OUT_PKT4(ring, REG_A6XX_VFD_CONTROL_1, 6);
670 OUT_RING(ring, A6XX_VFD_CONTROL_1_REGID4VTX(vertex_regid) |
671 A6XX_VFD_CONTROL_1_REGID4INST(instance_regid) |
672 0xfcfc0000);
673 OUT_RING(ring, 0x0000fcfc); /* VFD_CONTROL_2 */
674 OUT_RING(ring, 0xfcfcfcfc); /* VFD_CONTROL_3 */
675 OUT_RING(ring, 0x000000fc); /* VFD_CONTROL_4 */
676 OUT_RING(ring, 0x0000fcfc); /* VFD_CONTROL_5 */
677 OUT_RING(ring, 0x00000000); /* VFD_CONTROL_6 */
678 }
679
680 void
681 fd6_prog_init(struct pipe_context *pctx)
682 {
683 pctx->create_fs_state = fd6_fp_state_create;
684 pctx->delete_fs_state = fd6_fp_state_delete;
685
686 pctx->create_vs_state = fd6_vp_state_create;
687 pctx->delete_vs_state = fd6_vp_state_delete;
688
689 fd_prog_init(pctx);
690 }