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freedreno/a6xx: pre-calculate userconst stateobj size
[mesa.git] / src / gallium / drivers / freedreno / a6xx / fd6_program.c
1 /*
2 * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
23 *
24 * Authors:
25 * Rob Clark <robclark@freedesktop.org>
26 */
27
28 #include "pipe/p_state.h"
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_inlines.h"
32 #include "util/u_format.h"
33 #include "util/bitset.h"
34
35 #include "freedreno_program.h"
36
37 #include "fd6_program.h"
38 #include "fd6_emit.h"
39 #include "fd6_texture.h"
40 #include "fd6_format.h"
41
42 static struct ir3_shader *
43 create_shader_stateobj(struct pipe_context *pctx, const struct pipe_shader_state *cso,
44 gl_shader_stage type)
45 {
46 struct fd_context *ctx = fd_context(pctx);
47 struct ir3_compiler *compiler = ctx->screen->compiler;
48 struct ir3_shader *shader =
49 ir3_shader_create(compiler, cso, type, &ctx->debug, pctx->screen);
50 unsigned packets, size;
51
52 /* pre-calculate size required for userconst stateobj: */
53 ir3_user_consts_size(&shader->ubo_state, &packets, &size);
54
55 /* also account for UBO addresses: */
56 packets += 1;
57 size += 2 * shader->const_state.num_ubos;
58
59 unsigned sizedwords = (4 * packets) + size;
60 shader->ubo_state.cmdstream_size = sizedwords * 4;
61
62 return shader;
63 }
64
65 static void *
66 fd6_fp_state_create(struct pipe_context *pctx,
67 const struct pipe_shader_state *cso)
68 {
69 return create_shader_stateobj(pctx, cso, MESA_SHADER_FRAGMENT);
70 }
71
72 static void
73 fd6_fp_state_delete(struct pipe_context *pctx, void *hwcso)
74 {
75 struct ir3_shader *so = hwcso;
76 struct fd_context *ctx = fd_context(pctx);
77 ir3_cache_invalidate(fd6_context(ctx)->shader_cache, hwcso);
78 ir3_shader_destroy(so);
79 }
80
81 static void *
82 fd6_vp_state_create(struct pipe_context *pctx,
83 const struct pipe_shader_state *cso)
84 {
85 return create_shader_stateobj(pctx, cso, MESA_SHADER_VERTEX);
86 }
87
88 static void
89 fd6_vp_state_delete(struct pipe_context *pctx, void *hwcso)
90 {
91 struct ir3_shader *so = hwcso;
92 struct fd_context *ctx = fd_context(pctx);
93 ir3_cache_invalidate(fd6_context(ctx)->shader_cache, hwcso);
94 ir3_shader_destroy(so);
95 }
96
97 void
98 fd6_emit_shader(struct fd_ringbuffer *ring, const struct ir3_shader_variant *so)
99 {
100 enum a6xx_state_block sb = fd6_stage2shadersb(so->type);
101
102 OUT_PKT7(ring, fd6_stage2opcode(so->type), 3);
103 OUT_RING(ring, CP_LOAD_STATE6_0_DST_OFF(0) |
104 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER) |
105 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT) |
106 CP_LOAD_STATE6_0_STATE_BLOCK(sb) |
107 CP_LOAD_STATE6_0_NUM_UNIT(so->instrlen));
108 OUT_RELOCD(ring, so->bo, 0, 0, 0);
109 }
110
111 /* Add any missing varyings needed for stream-out. Otherwise varyings not
112 * used by fragment shader will be stripped out.
113 */
114 static void
115 link_stream_out(struct ir3_shader_linkage *l, const struct ir3_shader_variant *v)
116 {
117 const struct ir3_stream_output_info *strmout = &v->shader->stream_output;
118
119 /*
120 * First, any stream-out varyings not already in linkage map (ie. also
121 * consumed by frag shader) need to be added:
122 */
123 for (unsigned i = 0; i < strmout->num_outputs; i++) {
124 const struct ir3_stream_output *out = &strmout->output[i];
125 unsigned k = out->register_index;
126 unsigned compmask =
127 (1 << (out->num_components + out->start_component)) - 1;
128 unsigned idx, nextloc = 0;
129
130 /* psize/pos need to be the last entries in linkage map, and will
131 * get added link_stream_out, so skip over them:
132 */
133 if ((v->outputs[k].slot == VARYING_SLOT_PSIZ) ||
134 (v->outputs[k].slot == VARYING_SLOT_POS))
135 continue;
136
137 for (idx = 0; idx < l->cnt; idx++) {
138 if (l->var[idx].regid == v->outputs[k].regid)
139 break;
140 nextloc = MAX2(nextloc, l->var[idx].loc + 4);
141 }
142
143 /* add if not already in linkage map: */
144 if (idx == l->cnt)
145 ir3_link_add(l, v->outputs[k].regid, compmask, nextloc);
146
147 /* expand component-mask if needed, ie streaming out all components
148 * but frag shader doesn't consume all components:
149 */
150 if (compmask & ~l->var[idx].compmask) {
151 l->var[idx].compmask |= compmask;
152 l->max_loc = MAX2(l->max_loc,
153 l->var[idx].loc + util_last_bit(l->var[idx].compmask));
154 }
155 }
156 }
157
158 static void
159 setup_stream_out(struct fd6_program_state *state, const struct ir3_shader_variant *v,
160 struct ir3_shader_linkage *l)
161 {
162 const struct ir3_stream_output_info *strmout = &v->shader->stream_output;
163 struct fd6_streamout_state *tf = &state->tf;
164
165 memset(tf, 0, sizeof(*tf));
166
167 tf->prog_count = align(l->max_loc, 2) / 2;
168
169 debug_assert(tf->prog_count < ARRAY_SIZE(tf->prog));
170
171 for (unsigned i = 0; i < strmout->num_outputs; i++) {
172 const struct ir3_stream_output *out = &strmout->output[i];
173 unsigned k = out->register_index;
174 unsigned idx;
175
176 tf->ncomp[out->output_buffer] += out->num_components;
177
178 /* linkage map sorted by order frag shader wants things, so
179 * a bit less ideal here..
180 */
181 for (idx = 0; idx < l->cnt; idx++)
182 if (l->var[idx].regid == v->outputs[k].regid)
183 break;
184
185 debug_assert(idx < l->cnt);
186
187 for (unsigned j = 0; j < out->num_components; j++) {
188 unsigned c = j + out->start_component;
189 unsigned loc = l->var[idx].loc + c;
190 unsigned off = j + out->dst_offset; /* in dwords */
191
192 if (loc & 1) {
193 tf->prog[loc/2] |= A6XX_VPC_SO_PROG_B_EN |
194 A6XX_VPC_SO_PROG_B_BUF(out->output_buffer) |
195 A6XX_VPC_SO_PROG_B_OFF(off * 4);
196 } else {
197 tf->prog[loc/2] |= A6XX_VPC_SO_PROG_A_EN |
198 A6XX_VPC_SO_PROG_A_BUF(out->output_buffer) |
199 A6XX_VPC_SO_PROG_A_OFF(off * 4);
200 }
201 }
202 }
203
204 tf->vpc_so_buf_cntl = A6XX_VPC_SO_BUF_CNTL_ENABLE |
205 COND(tf->ncomp[0] > 0, A6XX_VPC_SO_BUF_CNTL_BUF0) |
206 COND(tf->ncomp[1] > 0, A6XX_VPC_SO_BUF_CNTL_BUF1) |
207 COND(tf->ncomp[2] > 0, A6XX_VPC_SO_BUF_CNTL_BUF2) |
208 COND(tf->ncomp[3] > 0, A6XX_VPC_SO_BUF_CNTL_BUF3);
209 }
210
211 static void
212 setup_config_stateobj(struct fd_ringbuffer *ring, struct fd6_program_state *state)
213 {
214 OUT_PKT4(ring, REG_A6XX_HLSQ_UPDATE_CNTL, 1);
215 OUT_RING(ring, 0xff); /* XXX */
216
217 debug_assert(state->vs->constlen >= state->bs->constlen);
218
219 OUT_PKT4(ring, REG_A6XX_HLSQ_VS_CNTL, 4);
220 OUT_RING(ring, A6XX_HLSQ_VS_CNTL_CONSTLEN(align(state->vs->constlen, 4)) |
221 A6XX_HLSQ_VS_CNTL_ENABLED);
222 OUT_RING(ring, A6XX_HLSQ_HS_CNTL_CONSTLEN(0));
223 OUT_RING(ring, A6XX_HLSQ_DS_CNTL_CONSTLEN(0));
224 OUT_RING(ring, A6XX_HLSQ_GS_CNTL_CONSTLEN(0));
225
226 OUT_PKT4(ring, REG_A6XX_HLSQ_FS_CNTL, 1);
227 OUT_RING(ring, A6XX_HLSQ_FS_CNTL_CONSTLEN(align(state->fs->constlen, 4)) |
228 A6XX_HLSQ_FS_CNTL_ENABLED);
229
230 OUT_PKT4(ring, REG_A6XX_SP_VS_CONFIG, 1);
231 OUT_RING(ring, COND(state->vs, A6XX_SP_VS_CONFIG_ENABLED) |
232 A6XX_SP_VS_CONFIG_NIBO(state->vs->image_mapping.num_ibo) |
233 A6XX_SP_VS_CONFIG_NTEX(state->vs->num_samp) |
234 A6XX_SP_VS_CONFIG_NSAMP(state->vs->num_samp));
235
236 OUT_PKT4(ring, REG_A6XX_SP_FS_CONFIG, 1);
237 OUT_RING(ring, COND(state->fs, A6XX_SP_FS_CONFIG_ENABLED) |
238 A6XX_SP_FS_CONFIG_NIBO(state->fs->image_mapping.num_ibo) |
239 A6XX_SP_FS_CONFIG_NTEX(state->fs->num_samp) |
240 A6XX_SP_FS_CONFIG_NSAMP(state->fs->num_samp));
241
242 OUT_PKT4(ring, REG_A6XX_SP_HS_CONFIG, 1);
243 OUT_RING(ring, COND(false, A6XX_SP_HS_CONFIG_ENABLED));
244
245 OUT_PKT4(ring, REG_A6XX_SP_DS_CONFIG, 1);
246 OUT_RING(ring, COND(false, A6XX_SP_DS_CONFIG_ENABLED));
247
248 OUT_PKT4(ring, REG_A6XX_SP_GS_CONFIG, 1);
249 OUT_RING(ring, COND(false, A6XX_SP_GS_CONFIG_ENABLED));
250
251 OUT_PKT4(ring, REG_A6XX_SP_IBO_COUNT, 1);
252 OUT_RING(ring, state->fs->image_mapping.num_ibo);
253 }
254
255 #define VALIDREG(r) ((r) != regid(63,0))
256 #define CONDREG(r, val) COND(VALIDREG(r), (val))
257
258 static inline uint32_t
259 next_regid(uint32_t reg, uint32_t increment)
260 {
261 if (VALIDREG(reg))
262 return reg + increment;
263 else
264 return regid(63,0);
265 }
266
267 static void
268 setup_stateobj(struct fd_ringbuffer *ring, struct fd_screen *screen,
269 struct fd6_program_state *state, const struct ir3_shader_key *key,
270 bool binning_pass)
271 {
272 uint32_t pos_regid, psize_regid, color_regid[8], posz_regid;
273 uint32_t face_regid, coord_regid, zwcoord_regid, samp_id_regid;
274 uint32_t smask_in_regid, smask_regid;
275 uint32_t vertex_regid, instance_regid;
276 uint32_t ij_pix_regid, ij_samp_regid, ij_cent_regid, ij_size_regid;
277 enum a3xx_threadsize fssz;
278 uint8_t psize_loc = ~0;
279 int i, j;
280
281 static const struct ir3_shader_variant dummy_fs = {0};
282 const struct ir3_shader_variant *vs = binning_pass ? state->bs : state->vs;
283 const struct ir3_shader_variant *fs = binning_pass ? &dummy_fs : state->fs;
284
285 bool sample_shading = fs->per_samp | key->sample_shading;
286
287 fssz = FOUR_QUADS;
288
289 pos_regid = ir3_find_output_regid(vs, VARYING_SLOT_POS);
290 psize_regid = ir3_find_output_regid(vs, VARYING_SLOT_PSIZ);
291 vertex_regid = ir3_find_sysval_regid(vs, SYSTEM_VALUE_VERTEX_ID);
292 instance_regid = ir3_find_sysval_regid(vs, SYSTEM_VALUE_INSTANCE_ID);
293
294 if (fs->color0_mrt) {
295 color_regid[0] = color_regid[1] = color_regid[2] = color_regid[3] =
296 color_regid[4] = color_regid[5] = color_regid[6] = color_regid[7] =
297 ir3_find_output_regid(fs, FRAG_RESULT_COLOR);
298 } else {
299 color_regid[0] = ir3_find_output_regid(fs, FRAG_RESULT_DATA0);
300 color_regid[1] = ir3_find_output_regid(fs, FRAG_RESULT_DATA1);
301 color_regid[2] = ir3_find_output_regid(fs, FRAG_RESULT_DATA2);
302 color_regid[3] = ir3_find_output_regid(fs, FRAG_RESULT_DATA3);
303 color_regid[4] = ir3_find_output_regid(fs, FRAG_RESULT_DATA4);
304 color_regid[5] = ir3_find_output_regid(fs, FRAG_RESULT_DATA5);
305 color_regid[6] = ir3_find_output_regid(fs, FRAG_RESULT_DATA6);
306 color_regid[7] = ir3_find_output_regid(fs, FRAG_RESULT_DATA7);
307 }
308
309 samp_id_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_ID);
310 smask_in_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_SAMPLE_MASK_IN);
311 face_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRONT_FACE);
312 coord_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_FRAG_COORD);
313 zwcoord_regid = next_regid(coord_regid, 2);
314 ij_pix_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_PIXEL);
315 ij_samp_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_SAMPLE);
316 ij_cent_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_CENTROID);
317 ij_size_regid = ir3_find_sysval_regid(fs, SYSTEM_VALUE_BARYCENTRIC_SIZE);
318 posz_regid = ir3_find_output_regid(fs, FRAG_RESULT_DEPTH);
319 smask_regid = ir3_find_output_regid(fs, FRAG_RESULT_SAMPLE_MASK);
320
321 /* we can't write gl_SampleMask for !msaa.. if b0 is zero then we
322 * end up masking the single sample!!
323 */
324 if (!key->msaa)
325 smask_regid = regid(63, 0);
326
327 /* we could probably divide this up into things that need to be
328 * emitted if frag-prog is dirty vs if vert-prog is dirty..
329 */
330
331 OUT_PKT4(ring, REG_A6XX_SP_VS_INSTRLEN, 1);
332 OUT_RING(ring, vs->instrlen); /* SP_VS_INSTRLEN */
333
334 OUT_PKT4(ring, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
335 OUT_RING(ring, 0);
336
337 OUT_PKT4(ring, REG_A6XX_SP_HS_INSTRLEN, 1);
338 OUT_RING(ring, 0); /* SP_HS_INSTRLEN */
339
340 OUT_PKT4(ring, REG_A6XX_SP_DS_INSTRLEN, 1);
341 OUT_RING(ring, 0); /* SP_DS_INSTRLEN */
342
343 OUT_PKT4(ring, REG_A6XX_SP_GS_UNKNOWN_A871, 1);
344 OUT_RING(ring, 0);
345
346 OUT_PKT4(ring, REG_A6XX_SP_GS_INSTRLEN, 1);
347 OUT_RING(ring, 0); /* SP_GS_INSTRLEN */
348
349 /* I believe this is related to pre-dispatch texture fetch.. we probably
350 * should't turn it on by accident:
351 */
352 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A99E, 1);
353 OUT_RING(ring, 0x0);
354
355 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A9A8, 1);
356 OUT_RING(ring, 0);
357
358 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_AB00, 1);
359 OUT_RING(ring, 0x5);
360
361 OUT_PKT4(ring, REG_A6XX_SP_FS_INSTRLEN, 1);
362 OUT_RING(ring, fs->instrlen); /* SP_FS_INSTRLEN */
363
364 OUT_PKT4(ring, REG_A6XX_SP_FS_OUTPUT_CNTL0, 1);
365 OUT_RING(ring, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid) |
366 A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid) |
367 0xfc000000);
368
369 OUT_PKT4(ring, REG_A6XX_SP_VS_CTRL_REG0, 1);
370 OUT_RING(ring, A6XX_SP_VS_CTRL_REG0_THREADSIZE(fssz) |
371 A6XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(vs->info.max_reg + 1) |
372 A6XX_SP_VS_CTRL_REG0_MERGEDREGS |
373 A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(vs->branchstack) |
374 COND(vs->need_pixlod, A6XX_SP_VS_CTRL_REG0_PIXLODENABLE));
375
376 struct ir3_shader_linkage l = {0};
377 ir3_link_shaders(&l, vs, fs);
378
379 if ((vs->shader->stream_output.num_outputs > 0) && !binning_pass)
380 link_stream_out(&l, vs);
381
382 BITSET_DECLARE(varbs, 128) = {0};
383 uint32_t *varmask = (uint32_t *)varbs;
384
385 for (i = 0; i < l.cnt; i++)
386 for (j = 0; j < util_last_bit(l.var[i].compmask); j++)
387 BITSET_SET(varbs, l.var[i].loc + j);
388
389 OUT_PKT4(ring, REG_A6XX_VPC_VAR_DISABLE(0), 4);
390 OUT_RING(ring, ~varmask[0]); /* VPC_VAR[0].DISABLE */
391 OUT_RING(ring, ~varmask[1]); /* VPC_VAR[1].DISABLE */
392 OUT_RING(ring, ~varmask[2]); /* VPC_VAR[2].DISABLE */
393 OUT_RING(ring, ~varmask[3]); /* VPC_VAR[3].DISABLE */
394
395 /* a6xx appends pos/psize to end of the linkage map: */
396 if (VALIDREG(pos_regid))
397 ir3_link_add(&l, pos_regid, 0xf, l.max_loc);
398
399 if (VALIDREG(psize_regid)) {
400 psize_loc = l.max_loc;
401 ir3_link_add(&l, psize_regid, 0x1, l.max_loc);
402 }
403
404 if ((vs->shader->stream_output.num_outputs > 0) && !binning_pass) {
405 setup_stream_out(state, vs, &l);
406 }
407
408 for (i = 0, j = 0; (i < 16) && (j < l.cnt); i++) {
409 uint32_t reg = 0;
410
411 OUT_PKT4(ring, REG_A6XX_SP_VS_OUT_REG(i), 1);
412
413 reg |= A6XX_SP_VS_OUT_REG_A_REGID(l.var[j].regid);
414 reg |= A6XX_SP_VS_OUT_REG_A_COMPMASK(l.var[j].compmask);
415 j++;
416
417 reg |= A6XX_SP_VS_OUT_REG_B_REGID(l.var[j].regid);
418 reg |= A6XX_SP_VS_OUT_REG_B_COMPMASK(l.var[j].compmask);
419 j++;
420
421 OUT_RING(ring, reg);
422 }
423
424 for (i = 0, j = 0; (i < 8) && (j < l.cnt); i++) {
425 uint32_t reg = 0;
426
427 OUT_PKT4(ring, REG_A6XX_SP_VS_VPC_DST_REG(i), 1);
428
429 reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC0(l.var[j++].loc);
430 reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC1(l.var[j++].loc);
431 reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC2(l.var[j++].loc);
432 reg |= A6XX_SP_VS_VPC_DST_REG_OUTLOC3(l.var[j++].loc);
433
434 OUT_RING(ring, reg);
435 }
436
437 OUT_PKT4(ring, REG_A6XX_SP_VS_OBJ_START_LO, 2);
438 OUT_RELOC(ring, vs->bo, 0, 0, 0); /* SP_VS_OBJ_START_LO/HI */
439
440 if (vs->instrlen)
441 fd6_emit_shader(ring, vs);
442
443
444 OUT_PKT4(ring, REG_A6XX_SP_PRIMITIVE_CNTL, 1);
445 OUT_RING(ring, A6XX_SP_PRIMITIVE_CNTL_VSOUT(l.cnt));
446
447 bool enable_varyings = fs->total_in > 0;
448
449 OUT_PKT4(ring, REG_A6XX_VPC_CNTL_0, 1);
450 OUT_RING(ring, A6XX_VPC_CNTL_0_NUMNONPOSVAR(fs->total_in) |
451 COND(enable_varyings, A6XX_VPC_CNTL_0_VARYING) |
452 0xff00ff00);
453
454 OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_1, 1);
455 OUT_RING(ring, A6XX_PC_PRIMITIVE_CNTL_1_STRIDE_IN_VPC(l.max_loc) |
456 CONDREG(psize_regid, 0x100));
457
458 if (binning_pass) {
459 OUT_PKT4(ring, REG_A6XX_SP_FS_OBJ_START_LO, 2);
460 OUT_RING(ring, 0x00000000); /* SP_FS_OBJ_START_LO */
461 OUT_RING(ring, 0x00000000); /* SP_FS_OBJ_START_HI */
462 } else {
463 OUT_PKT4(ring, REG_A6XX_SP_FS_OBJ_START_LO, 2);
464 OUT_RELOC(ring, fs->bo, 0, 0, 0); /* SP_FS_OBJ_START_LO/HI */
465 }
466
467 OUT_PKT4(ring, REG_A6XX_HLSQ_CONTROL_1_REG, 5);
468 OUT_RING(ring, 0x7); /* XXX */
469 OUT_RING(ring, A6XX_HLSQ_CONTROL_2_REG_FACEREGID(face_regid) |
470 A6XX_HLSQ_CONTROL_2_REG_SAMPLEID(samp_id_regid) |
471 A6XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(smask_in_regid) |
472 A6XX_HLSQ_CONTROL_2_REG_SIZE(ij_size_regid));
473 OUT_RING(ring, A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_PIXEL(ij_pix_regid) |
474 A6XX_HLSQ_CONTROL_3_REG_BARY_IJ_CENTROID(ij_cent_regid) |
475 0xfc00fc00); /* XXX */
476 OUT_RING(ring, A6XX_HLSQ_CONTROL_4_REG_XYCOORDREGID(coord_regid) |
477 A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(zwcoord_regid) |
478 A6XX_HLSQ_CONTROL_4_REG_BARY_IJ_PIXEL_PERSAMP(ij_samp_regid) |
479 0x0000fc00); /* XXX */
480 OUT_RING(ring, 0xfc); /* XXX */
481
482 OUT_PKT4(ring, REG_A6XX_HLSQ_UNKNOWN_B980, 1);
483 OUT_RING(ring, enable_varyings ? 3 : 1);
484
485 OUT_PKT4(ring, REG_A6XX_SP_FS_CTRL_REG0, 1);
486 OUT_RING(ring, A6XX_SP_FS_CTRL_REG0_THREADSIZE(fssz) |
487 COND(enable_varyings, A6XX_SP_FS_CTRL_REG0_VARYING) |
488 COND(fs->frag_coord, A6XX_SP_FS_CTRL_REG0_VARYING) |
489 0x1000000 |
490 A6XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(fs->info.max_reg + 1) |
491 A6XX_SP_FS_CTRL_REG0_MERGEDREGS |
492 A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(fs->branchstack) |
493 COND(fs->need_pixlod, A6XX_SP_FS_CTRL_REG0_PIXLODENABLE));
494
495 OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A982, 1);
496 OUT_RING(ring, 0); /* XXX */
497
498 OUT_PKT4(ring, REG_A6XX_VPC_GS_SIV_CNTL, 1);
499 OUT_RING(ring, 0x0000ffff); /* XXX */
500
501 OUT_PKT4(ring, REG_A6XX_GRAS_CNTL, 1);
502 OUT_RING(ring,
503 CONDREG(ij_pix_regid, A6XX_GRAS_CNTL_VARYING) |
504 CONDREG(ij_cent_regid, A6XX_GRAS_CNTL_CENTROID) |
505 CONDREG(ij_samp_regid, A6XX_GRAS_CNTL_PERSAMP_VARYING) |
506 COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_GRAS_CNTL_SIZE) |
507 COND(VALIDREG(ij_size_regid) && sample_shading, A6XX_GRAS_CNTL_SIZE_PERSAMP) |
508 COND(fs->frag_coord,
509 A6XX_GRAS_CNTL_SIZE |
510 A6XX_GRAS_CNTL_XCOORD |
511 A6XX_GRAS_CNTL_YCOORD |
512 A6XX_GRAS_CNTL_ZCOORD |
513 A6XX_GRAS_CNTL_WCOORD) |
514 COND(fs->frag_face, A6XX_GRAS_CNTL_SIZE));
515
516 OUT_PKT4(ring, REG_A6XX_RB_RENDER_CONTROL0, 2);
517 OUT_RING(ring,
518 CONDREG(ij_pix_regid, A6XX_RB_RENDER_CONTROL0_VARYING) |
519 CONDREG(ij_cent_regid, A6XX_RB_RENDER_CONTROL0_CENTROID) |
520 CONDREG(ij_samp_regid, A6XX_RB_RENDER_CONTROL0_PERSAMP_VARYING) |
521 COND(enable_varyings, A6XX_RB_RENDER_CONTROL0_UNK10) |
522 COND(VALIDREG(ij_size_regid) && !sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE) |
523 COND(VALIDREG(ij_size_regid) && sample_shading, A6XX_RB_RENDER_CONTROL0_SIZE_PERSAMP) |
524 COND(fs->frag_coord,
525 A6XX_RB_RENDER_CONTROL0_SIZE |
526 A6XX_RB_RENDER_CONTROL0_XCOORD |
527 A6XX_RB_RENDER_CONTROL0_YCOORD |
528 A6XX_RB_RENDER_CONTROL0_ZCOORD |
529 A6XX_RB_RENDER_CONTROL0_WCOORD) |
530 COND(fs->frag_face, A6XX_RB_RENDER_CONTROL0_SIZE));
531
532 OUT_RING(ring,
533 CONDREG(smask_in_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK) |
534 CONDREG(samp_id_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEID) |
535 CONDREG(ij_size_regid, A6XX_RB_RENDER_CONTROL1_SIZE) |
536 COND(fs->frag_face, A6XX_RB_RENDER_CONTROL1_FACENESS));
537
538 OUT_PKT4(ring, REG_A6XX_RB_SAMPLE_CNTL, 1);
539 OUT_RING(ring, COND(sample_shading, A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE));
540
541 OUT_PKT4(ring, REG_A6XX_GRAS_UNKNOWN_8101, 1);
542 OUT_RING(ring, COND(sample_shading, 0x6)); // XXX
543
544 OUT_PKT4(ring, REG_A6XX_GRAS_SAMPLE_CNTL, 1);
545 OUT_RING(ring, COND(sample_shading, A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE));
546
547 OUT_PKT4(ring, REG_A6XX_SP_FS_OUTPUT_REG(0), 8);
548 for (i = 0; i < 8; i++) {
549 OUT_RING(ring, A6XX_SP_FS_OUTPUT_REG_REGID(color_regid[i]) |
550 COND(color_regid[i] & HALF_REG_ID, A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION));
551 }
552
553 OUT_PKT4(ring, REG_A6XX_VPC_PACK, 1);
554 OUT_RING(ring, A6XX_VPC_PACK_NUMNONPOSVAR(fs->total_in) |
555 A6XX_VPC_PACK_PSIZELOC(psize_loc) |
556 A6XX_VPC_PACK_STRIDE_IN_VPC(l.max_loc));
557
558 if (!binning_pass) {
559 /* figure out VARYING_INTERP / VARYING_PS_REPL register values: */
560 for (j = -1; (j = ir3_next_varying(fs, j)) < (int)fs->inputs_count; ) {
561 /* NOTE: varyings are packed, so if compmask is 0xb
562 * then first, third, and fourth component occupy
563 * three consecutive varying slots:
564 */
565 unsigned compmask = fs->inputs[j].compmask;
566
567 uint32_t inloc = fs->inputs[j].inloc;
568
569 if (fs->inputs[j].interpolate == INTERP_MODE_FLAT) {
570 uint32_t loc = inloc;
571
572 for (i = 0; i < 4; i++) {
573 if (compmask & (1 << i)) {
574 state->vinterp[loc / 16] |= 1 << ((loc % 16) * 2);
575 loc++;
576 }
577 }
578 }
579 }
580 }
581
582 if (!binning_pass)
583 if (fs->instrlen)
584 fd6_emit_shader(ring, fs);
585
586 OUT_PKT4(ring, REG_A6XX_VFD_CONTROL_1, 6);
587 OUT_RING(ring, A6XX_VFD_CONTROL_1_REGID4VTX(vertex_regid) |
588 A6XX_VFD_CONTROL_1_REGID4INST(instance_regid) |
589 0xfcfc0000);
590 OUT_RING(ring, 0x0000fcfc); /* VFD_CONTROL_2 */
591 OUT_RING(ring, 0xfcfcfcfc); /* VFD_CONTROL_3 */
592 OUT_RING(ring, 0x000000fc); /* VFD_CONTROL_4 */
593 OUT_RING(ring, 0x0000fcfc); /* VFD_CONTROL_5 */
594 OUT_RING(ring, 0x00000000); /* VFD_CONTROL_6 */
595
596 bool fragz = fs->no_earlyz | fs->writes_pos;
597
598 OUT_PKT4(ring, REG_A6XX_RB_DEPTH_PLANE_CNTL, 1);
599 OUT_RING(ring, COND(fragz, A6XX_RB_DEPTH_PLANE_CNTL_FRAG_WRITES_Z));
600
601 OUT_PKT4(ring, REG_A6XX_GRAS_SU_DEPTH_PLANE_CNTL, 1);
602 OUT_RING(ring, COND(fragz, A6XX_GRAS_SU_DEPTH_PLANE_CNTL_FRAG_WRITES_Z));
603
604 ir3_emit_immediates(screen, vs, ring);
605 if (!binning_pass)
606 ir3_emit_immediates(screen, fs, ring);
607 }
608
609 /* emits the program state which is not part of the stateobj because of
610 * dependency on other gl state (rasterflat or sprite-coord-replacement)
611 */
612 void
613 fd6_program_emit(struct fd_ringbuffer *ring, struct fd6_emit *emit)
614 {
615 const struct fd6_program_state *state = fd6_emit_get_prog(emit);
616
617 if (!unlikely(emit->rasterflat || emit->sprite_coord_enable)) {
618 /* fastpath: */
619 OUT_PKT4(ring, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
620 for (int i = 0; i < 8; i++)
621 OUT_RING(ring, state->vinterp[i]); /* VPC_VARYING_INTERP[i].MODE */
622
623 OUT_PKT4(ring, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
624 for (int i = 0; i < 8; i++)
625 OUT_RING(ring, 0x00000000); /* VPC_VARYING_PS_REPL[i] */
626 } else {
627 /* slow-path: */
628 struct ir3_shader_variant *fs = state->fs;
629 uint32_t vinterp[8], vpsrepl[8];
630
631 memset(vinterp, 0, sizeof(vinterp));
632 memset(vpsrepl, 0, sizeof(vpsrepl));
633
634 for (int j = -1; (j = ir3_next_varying(fs, j)) < (int)fs->inputs_count; ) {
635
636 /* NOTE: varyings are packed, so if compmask is 0xb
637 * then first, third, and fourth component occupy
638 * three consecutive varying slots:
639 */
640 unsigned compmask = fs->inputs[j].compmask;
641
642 uint32_t inloc = fs->inputs[j].inloc;
643
644 if ((fs->inputs[j].interpolate == INTERP_MODE_FLAT) ||
645 (fs->inputs[j].rasterflat && emit->rasterflat)) {
646 uint32_t loc = inloc;
647
648 for (int i = 0; i < 4; i++) {
649 if (compmask & (1 << i)) {
650 vinterp[loc / 16] |= 1 << ((loc % 16) * 2);
651 loc++;
652 }
653 }
654 }
655
656 gl_varying_slot slot = fs->inputs[j].slot;
657
658 /* since we don't enable PIPE_CAP_TGSI_TEXCOORD: */
659 if (slot >= VARYING_SLOT_VAR0) {
660 unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
661 /* Replace the .xy coordinates with S/T from the point sprite. Set
662 * interpolation bits for .zw such that they become .01
663 */
664 if (emit->sprite_coord_enable & texmask) {
665 /* mask is two 2-bit fields, where:
666 * '01' -> S
667 * '10' -> T
668 * '11' -> 1 - T (flip mode)
669 */
670 unsigned mask = emit->sprite_coord_mode ? 0b1101 : 0b1001;
671 uint32_t loc = inloc;
672 if (compmask & 0x1) {
673 vpsrepl[loc / 16] |= ((mask >> 0) & 0x3) << ((loc % 16) * 2);
674 loc++;
675 }
676 if (compmask & 0x2) {
677 vpsrepl[loc / 16] |= ((mask >> 2) & 0x3) << ((loc % 16) * 2);
678 loc++;
679 }
680 if (compmask & 0x4) {
681 /* .z <- 0.0f */
682 vinterp[loc / 16] |= 0b10 << ((loc % 16) * 2);
683 loc++;
684 }
685 if (compmask & 0x8) {
686 /* .w <- 1.0f */
687 vinterp[loc / 16] |= 0b11 << ((loc % 16) * 2);
688 loc++;
689 }
690 }
691 }
692 }
693
694 OUT_PKT4(ring, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
695 for (int i = 0; i < 8; i++)
696 OUT_RING(ring, vinterp[i]); /* VPC_VARYING_INTERP[i].MODE */
697
698 OUT_PKT4(ring, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
699 for (int i = 0; i < 8; i++)
700 OUT_RING(ring, vpsrepl[i]); /* VPC_VARYING_PS_REPL[i] */
701 }
702 }
703
704 static struct ir3_program_state *
705 fd6_program_create(void *data, struct ir3_shader_variant *bs,
706 struct ir3_shader_variant *vs,
707 struct ir3_shader_variant *fs,
708 const struct ir3_shader_key *key)
709 {
710 struct fd_context *ctx = data;
711 struct fd6_program_state *state = CALLOC_STRUCT(fd6_program_state);
712
713 state->bs = bs;
714 state->vs = vs;
715 state->fs = fs;
716 state->config_stateobj = fd_ringbuffer_new_object(ctx->pipe, 0x1000);
717 state->binning_stateobj = fd_ringbuffer_new_object(ctx->pipe, 0x1000);
718 state->stateobj = fd_ringbuffer_new_object(ctx->pipe, 0x1000);
719
720 #ifdef DEBUG
721 for (unsigned i = 0; i < bs->inputs_count; i++) {
722 if (vs->inputs[i].sysval)
723 continue;
724 debug_assert(bs->inputs[i].regid == vs->inputs[i].regid);
725 }
726 #endif
727
728 setup_config_stateobj(state->config_stateobj, state);
729 setup_stateobj(state->binning_stateobj, ctx->screen, state, key, true);
730 setup_stateobj(state->stateobj, ctx->screen, state, key, false);
731
732 return &state->base;
733 }
734
735 static void
736 fd6_program_destroy(void *data, struct ir3_program_state *state)
737 {
738 struct fd6_program_state *so = fd6_program_state(state);
739 fd_ringbuffer_del(so->stateobj);
740 fd_ringbuffer_del(so->binning_stateobj);
741 fd_ringbuffer_del(so->config_stateobj);
742 free(so);
743 }
744
745 static const struct ir3_cache_funcs cache_funcs = {
746 .create_state = fd6_program_create,
747 .destroy_state = fd6_program_destroy,
748 };
749
750 void
751 fd6_prog_init(struct pipe_context *pctx)
752 {
753 struct fd_context *ctx = fd_context(pctx);
754
755 fd6_context(ctx)->shader_cache = ir3_cache_create(&cache_funcs, ctx);
756
757 pctx->create_fs_state = fd6_fp_state_create;
758 pctx->delete_fs_state = fd6_fp_state_delete;
759
760 pctx->create_vs_state = fd6_vp_state_create;
761 pctx->delete_vs_state = fd6_vp_state_delete;
762
763 fd_prog_init(pctx);
764 }