2 * Copyright (C) 2018 Rob Clark <robclark@freedesktop.org>
3 * Copyright © 2018 Google, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25 * Rob Clark <robclark@freedesktop.org>
28 #include "fd6_resource.h"
29 #include "fd6_format.h"
33 /* indexed by cpp, including msaa 2x and 4x: */
37 } tile_alignment
[] = {
51 /* special cases for r16: */
55 /* NOTE: good way to test this is: (for example)
56 * piglit/bin/texelFetch fs sampler3D 100x100x8
59 setup_slices(struct fd_resource
*rsc
, uint32_t alignment
, enum pipe_format format
)
61 struct pipe_resource
*prsc
= &rsc
->base
;
62 struct fd_screen
*screen
= fd_screen(prsc
->screen
);
63 enum util_format_layout layout
= util_format_description(format
)->layout
;
64 uint32_t pitchalign
= screen
->gmem_alignw
;
65 uint32_t level
, size
= 0;
66 uint32_t depth
= prsc
->depth0
;
67 /* linear dimensions: */
68 uint32_t lwidth
= prsc
->width0
;
69 uint32_t lheight
= prsc
->height0
;
70 /* tile_mode dimensions: */
71 uint32_t twidth
= util_next_power_of_two(lwidth
);
72 uint32_t theight
= util_next_power_of_two(lheight
);
73 /* in layer_first layout, the level (slice) contains just one
74 * layer (since in fact the layer contains the slices)
76 uint32_t layers_in_level
= rsc
->layer_first
? 1 : prsc
->array_size
;
79 /* The z16/r16 formats seem to not play by the normal tiling rules: */
80 if ((rsc
->cpp
== 2) && (util_format_get_nr_components(format
) == 1))
83 debug_assert(ta
< ARRAY_SIZE(tile_alignment
));
84 debug_assert(tile_alignment
[ta
].pitchalign
);
86 for (level
= 0; level
<= prsc
->last_level
; level
++) {
87 struct fd_resource_slice
*slice
= fd_resource_slice(rsc
, level
);
88 bool linear_level
= fd_resource_level_linear(prsc
, level
);
89 uint32_t width
, height
;
91 /* tiled levels of 3D textures are rounded up to PoT dimensions: */
92 if ((prsc
->target
== PIPE_TEXTURE_3D
) && rsc
->tile_mode
&& !linear_level
) {
99 uint32_t aligned_height
= height
;
102 if (rsc
->tile_mode
&& !linear_level
) {
103 pitchalign
= tile_alignment
[ta
].pitchalign
;
104 aligned_height
= align(aligned_height
,
105 tile_alignment
[ta
].heightalign
);
110 /* The blits used for mem<->gmem work at a granularity of
111 * 32x32, which can cause faults due to over-fetch on the
112 * last level. The simple solution is to over-allocate a
113 * bit the last level to ensure any over-fetch is harmless.
114 * The pitch is already sufficiently aligned, but height
117 if ((level
== prsc
->last_level
) && (prsc
->target
!= PIPE_BUFFER
))
118 aligned_height
= align(aligned_height
, 32);
120 if (layout
== UTIL_FORMAT_LAYOUT_ASTC
)
122 util_align_npot(width
, pitchalign
* util_format_get_blockwidth(format
));
124 slice
->pitch
= align(width
, pitchalign
);
126 slice
->offset
= size
;
127 blocks
= util_format_get_nblocks(format
, slice
->pitch
, aligned_height
);
129 /* 1d array and 2d array textures must all have the same layer size
130 * for each miplevel on a6xx. 3d textures can have different layer
131 * sizes for high levels, but the hw auto-sizer is buggy (or at least
132 * different than what this code does), so as soon as the layer size
133 * range gets into range, we stop reducing it.
135 if (prsc
->target
== PIPE_TEXTURE_3D
) {
136 if (level
< 1 || (rsc
->slices
[level
- 1].size0
> 0xf000)) {
137 slice
->size0
= align(blocks
* rsc
->cpp
, alignment
);
139 slice
->size0
= rsc
->slices
[level
- 1].size0
;
142 slice
->size0
= align(blocks
* rsc
->cpp
, alignment
);
145 size
+= slice
->size0
* depth
* layers_in_level
;
148 debug_printf("%s: %ux%ux%u@%u:\t%2u: stride=%4u, size=%6u,%7u, aligned_height=%3u, blocks=%u, offset=0x%x\n",
149 util_format_name(prsc
->format
),
150 width
, height
, depth
, rsc
->cpp
,
151 level
, slice
->pitch
* rsc
->cpp
,
152 slice
->size0
, size
, aligned_height
, blocks
,
156 depth
= u_minify(depth
, 1);
157 lwidth
= u_minify(lwidth
, 1);
158 lheight
= u_minify(lheight
, 1);
159 twidth
= u_minify(twidth
, 1);
160 theight
= u_minify(theight
, 1);
166 /* A subset of the valid tiled formats can be compressed. We do
167 * already require tiled in order to be compressed, but just because
168 * it can be tiled doesn't mean it can be compressed.
171 ok_ubwc_format(enum pipe_format pfmt
)
173 /* NOTE: both x24s8 and z24s8 map to RB6_X8Z24_UNORM, but UBWC
174 * does not seem to work properly when sampling x24s8.. possibly
175 * because we sample it as TFMT6_8_8_8_8_UINT.
177 * This could possibly be a hw limitation, or maybe something
178 * else wrong somewhere (although z24s8 blits and sampling with
179 * UBWC seem fine). Recheck on a later revision of a6xx
181 if (pfmt
== PIPE_FORMAT_X24S8_UINT
)
184 switch (fd6_pipe2color(pfmt
)) {
185 case RB6_R10G10B10A2_UINT
:
186 case RB6_R10G10B10A2_UNORM
:
187 case RB6_R11G11B10_FLOAT
:
189 case RB6_R16G16B16A16_FLOAT
:
190 case RB6_R16G16B16A16_SINT
:
191 case RB6_R16G16B16A16_UINT
:
192 case RB6_R16G16_FLOAT
:
193 case RB6_R16G16_SINT
:
194 case RB6_R16G16_UINT
:
197 case RB6_R32G32B32A32_SINT
:
198 case RB6_R32G32B32A32_UINT
:
199 case RB6_R32G32_SINT
:
200 case RB6_R32G32_UINT
:
201 case RB6_R5G6B5_UNORM
:
202 case RB6_R8G8B8A8_SINT
:
203 case RB6_R8G8B8A8_UINT
:
204 case RB6_R8G8B8A8_UNORM
:
205 case RB6_R8G8B8_UNORM
:
209 case RB6_Z24_UNORM_S8_UINT
:
210 case RB6_Z24_UNORM_S8_UINT_AS_R8G8B8A8
:
218 fd6_fill_ubwc_buffer_sizes(struct fd_resource
*rsc
)
220 #define RBG_TILE_WIDTH_ALIGNMENT 64
221 #define RGB_TILE_HEIGHT_ALIGNMENT 16
222 #define UBWC_PLANE_SIZE_ALIGNMENT 4096
224 struct pipe_resource
*prsc
= &rsc
->base
;
225 uint32_t width
= prsc
->width0
;
226 uint32_t height
= prsc
->height0
;
228 if (!ok_ubwc_format(prsc
->format
))
231 /* limit things to simple single level 2d for now: */
232 if ((prsc
->depth0
!= 1) || (prsc
->array_size
!= 1) || (prsc
->last_level
!= 0))
235 uint32_t block_width
, block_height
;
254 uint32_t meta_stride
=
255 ALIGN_POT(DIV_ROUND_UP(width
, block_width
), RBG_TILE_WIDTH_ALIGNMENT
);
256 uint32_t meta_height
=
257 ALIGN_POT(DIV_ROUND_UP(height
, block_height
), RGB_TILE_HEIGHT_ALIGNMENT
);
259 ALIGN_POT(meta_stride
* meta_height
, UBWC_PLANE_SIZE_ALIGNMENT
);
261 /* UBWC goes first, then color data.. this constraint is mainly only
262 * because it is what the kernel expects for scanout. For non-2D we
263 * could just use a separate UBWC buffer..
265 rsc
->ubwc_offset
= 0;
266 rsc
->offset
= meta_size
;
267 rsc
->ubwc_pitch
= meta_stride
;
268 rsc
->ubwc_size
= meta_size
>> 2; /* in dwords??? */
269 rsc
->tile_mode
= TILE6_3
;
275 * Ensure the rsc is in an ok state to be used with the specified format.
276 * This handles the case of UBWC buffers used with non-UBWC compatible
277 * formats, by triggering an uncompress.
280 fd6_validate_format(struct fd_context
*ctx
, struct fd_resource
*rsc
,
281 enum pipe_format format
)
286 if (ok_ubwc_format(format
))
289 fd_resource_uncompress(ctx
, rsc
);
293 fd6_setup_slices(struct fd_resource
*rsc
)
297 switch (rsc
->base
.target
) {
298 case PIPE_TEXTURE_3D
:
299 rsc
->layer_first
= false;
303 rsc
->layer_first
= true;
308 return setup_slices(rsc
, alignment
, rsc
->base
.format
);