src/gallium/drivers/freedreno/a6xx/fd6_texture.c

   1 /*
   2  * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
   3  * Copyright © 2018 Google, Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  22  * SOFTWARE.
  23  *
  24  * Authors:
  25  *    Rob Clark <robclark@freedesktop.org>
  26  */
  27
  28 #include "pipe/p_state.h"
  29 #include "util/u_string.h"
  30 #include "util/u_memory.h"
  31 #include "util/u_inlines.h"
  32 #include "util/u_format.h"
  33 #include "util/hash_table.h"
  34
  35 #include "fd6_texture.h"
  36 #include "fd6_format.h"
  37 #include "fd6_emit.h"
  38
  39 static void fd6_texture_state_destroy(struct fd6_texture_state *state);
  40
  41 static enum a6xx_tex_clamp
  42 tex_clamp(unsigned wrap, bool clamp_to_edge, bool *needs_border)
  43 {
  44         /* Hardware does not support _CLAMP, but we emulate it: */
  45         if (wrap == PIPE_TEX_WRAP_CLAMP) {
  46                 wrap = (clamp_to_edge) ?
  47                         PIPE_TEX_WRAP_CLAMP_TO_EDGE : PIPE_TEX_WRAP_CLAMP_TO_BORDER;
  48         }
  49
  50         switch (wrap) {
  51         case PIPE_TEX_WRAP_REPEAT:
  52                 return A6XX_TEX_REPEAT;
  53         case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
  54                 return A6XX_TEX_CLAMP_TO_EDGE;
  55         case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
  56                 *needs_border = true;
  57                 return A6XX_TEX_CLAMP_TO_BORDER;
  58         case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
  59                 /* only works for PoT.. need to emulate otherwise! */
  60                 return A6XX_TEX_MIRROR_CLAMP;
  61         case PIPE_TEX_WRAP_MIRROR_REPEAT:
  62                 return A6XX_TEX_MIRROR_REPEAT;
  63         case PIPE_TEX_WRAP_MIRROR_CLAMP:
  64         case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
  65                 /* these two we could perhaps emulate, but we currently
  66                  * just don't advertise PIPE_CAP_TEXTURE_MIRROR_CLAMP
  67                  */
  68         default:
  69                 DBG("invalid wrap: %u", wrap);
  70                 return 0;
  71         }
  72 }
  73
  74 static enum a6xx_tex_filter
  75 tex_filter(unsigned filter, bool aniso)
  76 {
  77         switch (filter) {
  78         case PIPE_TEX_FILTER_NEAREST:
  79                 return A6XX_TEX_NEAREST;
  80         case PIPE_TEX_FILTER_LINEAR:
  81                 return aniso ? A6XX_TEX_ANISO : A6XX_TEX_LINEAR;
  82         default:
  83                 DBG("invalid filter: %u", filter);
  84                 return 0;
  85         }
  86 }
  87
  88 static void *
  89 fd6_sampler_state_create(struct pipe_context *pctx,
  90                 const struct pipe_sampler_state *cso)
  91 {
  92         struct fd6_sampler_stateobj *so = CALLOC_STRUCT(fd6_sampler_stateobj);
  93         unsigned aniso = util_last_bit(MIN2(cso->max_anisotropy >> 1, 8));
  94         bool miplinear = false;
  95         bool clamp_to_edge;
  96
  97         if (!so)
  98                 return NULL;
  99
 100         so->base = *cso;
 101         so->seqno = ++fd6_context(fd_context(pctx))->tex_seqno;
 102
 103         if (cso->min_mip_filter == PIPE_TEX_MIPFILTER_LINEAR)
 104                 miplinear = true;
 105
 106         /*
 107          * For nearest filtering, _CLAMP means _CLAMP_TO_EDGE;  for linear
 108          * filtering, _CLAMP means _CLAMP_TO_BORDER while additionally
 109          * clamping the texture coordinates to [0.0, 1.0].
 110          *
 111          * The clamping will be taken care of in the shaders.  There are two
 112          * filters here, but let the minification one has a say.
 113          */
 114         clamp_to_edge = (cso->min_img_filter == PIPE_TEX_FILTER_NEAREST);
 115         if (!clamp_to_edge) {
 116                 so->saturate_s = (cso->wrap_s == PIPE_TEX_WRAP_CLAMP);
 117                 so->saturate_t = (cso->wrap_t == PIPE_TEX_WRAP_CLAMP);
 118                 so->saturate_r = (cso->wrap_r == PIPE_TEX_WRAP_CLAMP);
 119         }
 120
 121         so->needs_border = false;
 122         so->texsamp0 =
 123                 COND(miplinear, A6XX_TEX_SAMP_0_MIPFILTER_LINEAR_NEAR) |
 124                 A6XX_TEX_SAMP_0_XY_MAG(tex_filter(cso->mag_img_filter, aniso)) |
 125                 A6XX_TEX_SAMP_0_XY_MIN(tex_filter(cso->min_img_filter, aniso)) |
 126                 A6XX_TEX_SAMP_0_ANISO(aniso) |
 127                 A6XX_TEX_SAMP_0_WRAP_S(tex_clamp(cso->wrap_s, clamp_to_edge, &so->needs_border)) |
 128                 A6XX_TEX_SAMP_0_WRAP_T(tex_clamp(cso->wrap_t, clamp_to_edge, &so->needs_border)) |
 129                 A6XX_TEX_SAMP_0_WRAP_R(tex_clamp(cso->wrap_r, clamp_to_edge, &so->needs_border));
 130
 131         so->texsamp1 =
 132                 COND(!cso->seamless_cube_map, A6XX_TEX_SAMP_1_CUBEMAPSEAMLESSFILTOFF) |
 133                 COND(!cso->normalized_coords, A6XX_TEX_SAMP_1_UNNORM_COORDS);
 134
 135         if (cso->min_mip_filter != PIPE_TEX_MIPFILTER_NONE) {
 136                 so->texsamp0 |= A6XX_TEX_SAMP_0_LOD_BIAS(cso->lod_bias);
 137                 so->texsamp1 |=
 138                         A6XX_TEX_SAMP_1_MIN_LOD(cso->min_lod) |
 139                         A6XX_TEX_SAMP_1_MAX_LOD(cso->max_lod);
 140         }
 141
 142         if (cso->compare_mode)
 143                 so->texsamp1 |= A6XX_TEX_SAMP_1_COMPARE_FUNC(cso->compare_func); /* maps 1:1 */
 144
 145         return so;
 146 }
 147
 148 static void
 149 fd6_sampler_state_delete(struct pipe_context *pctx, void *hwcso)
 150 {
 151         struct fd6_context *fd6_ctx = fd6_context(fd_context(pctx));
 152         struct fd6_sampler_stateobj *samp = hwcso;
 153
 154         hash_table_foreach(fd6_ctx->tex_cache, entry) {
 155                 struct fd6_texture_state *state = entry->data;
 156
 157                 for (unsigned i = 0; i < ARRAY_SIZE(state->key.samp); i++) {
 158                         if (samp->seqno == state->key.samp[i].seqno) {
 159                                 fd6_texture_state_destroy(entry->data);
 160                                 _mesa_hash_table_remove(fd6_ctx->tex_cache, entry);
 161                                 break;
 162                         }
 163                 }
 164         }
 165
 166         free(hwcso);
 167 }
 168
 169 static void
 170 fd6_sampler_states_bind(struct pipe_context *pctx,
 171                 enum pipe_shader_type shader, unsigned start,
 172                 unsigned nr, void **hwcso)
 173 {
 174         struct fd_context *ctx = fd_context(pctx);
 175         struct fd6_context *fd6_ctx = fd6_context(ctx);
 176         uint16_t saturate_s = 0, saturate_t = 0, saturate_r = 0;
 177         unsigned i;
 178
 179         if (!hwcso)
 180                 nr = 0;
 181
 182         for (i = 0; i < nr; i++) {
 183                 if (hwcso[i]) {
 184                         struct fd6_sampler_stateobj *sampler =
 185                                         fd6_sampler_stateobj(hwcso[i]);
 186                         if (sampler->saturate_s)
 187                                 saturate_s |= (1 << i);
 188                         if (sampler->saturate_t)
 189                                 saturate_t |= (1 << i);
 190                         if (sampler->saturate_r)
 191                                 saturate_r |= (1 << i);
 192                 }
 193         }
 194
 195         fd_sampler_states_bind(pctx, shader, start, nr, hwcso);
 196
 197         if (shader == PIPE_SHADER_FRAGMENT) {
 198                 fd6_ctx->fsaturate =
 199                         (saturate_s != 0) ||
 200                         (saturate_t != 0) ||
 201                         (saturate_r != 0);
 202                 fd6_ctx->fsaturate_s = saturate_s;
 203                 fd6_ctx->fsaturate_t = saturate_t;
 204                 fd6_ctx->fsaturate_r = saturate_r;
 205         } else if (shader == PIPE_SHADER_VERTEX) {
 206                 fd6_ctx->vsaturate =
 207                         (saturate_s != 0) ||
 208                         (saturate_t != 0) ||
 209                         (saturate_r != 0);
 210                 fd6_ctx->vsaturate_s = saturate_s;
 211                 fd6_ctx->vsaturate_t = saturate_t;
 212                 fd6_ctx->vsaturate_r = saturate_r;
 213         }
 214 }
 215
 216 static bool
 217 use_astc_srgb_workaround(struct pipe_context *pctx, enum pipe_format format)
 218 {
 219         return false;  // TODO check if this is still needed on a5xx
 220 }
 221
 222 static struct pipe_sampler_view *
 223 fd6_sampler_view_create(struct pipe_context *pctx, struct pipe_resource *prsc,
 224                 const struct pipe_sampler_view *cso)
 225 {
 226         struct fd6_pipe_sampler_view *so = CALLOC_STRUCT(fd6_pipe_sampler_view);
 227         struct fd_resource *rsc = fd_resource(prsc);
 228         enum pipe_format format = cso->format;
 229         unsigned lvl, layers;
 230
 231         if (!so)
 232                 return NULL;
 233
 234         if (format == PIPE_FORMAT_X32_S8X24_UINT) {
 235                 rsc = rsc->stencil;
 236                 format = rsc->base.format;
 237         }
 238
 239         so->base = *cso;
 240         pipe_reference(NULL, &prsc->reference);
 241         so->base.texture = prsc;
 242         so->base.reference.count = 1;
 243         so->base.context = pctx;
 244         so->seqno = ++fd6_context(fd_context(pctx))->tex_seqno;
 245
 246         so->texconst0 =
 247                 A6XX_TEX_CONST_0_FMT(fd6_pipe2tex(format)) |
 248                 A6XX_TEX_CONST_0_SAMPLES(fd_msaa_samples(prsc->nr_samples)) |
 249                 fd6_tex_swiz(prsc, cso->swizzle_r, cso->swizzle_g,
 250                                 cso->swizzle_b, cso->swizzle_a);
 251
 252         /* NOTE: since we sample z24s8 using 8888_UINT format, the swizzle
 253          * we get isn't quite right.  Use SWAP(XYZW) as a cheap and cheerful
 254          * way to re-arrange things so stencil component is where the swiz
 255          * expects.
 256          *
 257          * Note that gallium expects stencil sampler to return (s,s,s,s)
 258          * which isn't quite true.  To make that happen we'd have to massage
 259          * the swizzle.  But in practice only the .x component is used.
 260          *
 261          * Skip this in the tile case because tiled formats are not swapped
 262          * and we have already applied the inverse swap in fd6_tex_swiz()
 263          * to componsate for that.
 264          */
 265         if ((format == PIPE_FORMAT_X24S8_UINT) && !rsc->tile_mode) {
 266                 so->texconst0 |= A6XX_TEX_CONST_0_SWAP(XYZW);
 267         }
 268
 269         if (util_format_is_srgb(format)) {
 270                 if (use_astc_srgb_workaround(pctx, format))
 271                         so->astc_srgb = true;
 272                 so->texconst0 |= A6XX_TEX_CONST_0_SRGB;
 273         }
 274
 275         if (cso->target == PIPE_BUFFER) {
 276                 unsigned elements = cso->u.buf.size / util_format_get_blocksize(format);
 277
 278                 lvl = 0;
 279                 so->texconst1 =
 280                         A6XX_TEX_CONST_1_WIDTH(elements) |
 281                         A6XX_TEX_CONST_1_HEIGHT(1);
 282                 so->texconst2 =
 283                         A6XX_TEX_CONST_2_FETCHSIZE(fd6_pipe2fetchsize(format)) |
 284                         A6XX_TEX_CONST_2_PITCH(elements * rsc->cpp);
 285                 so->offset = cso->u.buf.offset;
 286         } else {
 287                 unsigned miplevels;
 288                 enum a6xx_tile_mode tile_mode = TILE6_LINEAR;
 289
 290                 lvl = fd_sampler_first_level(cso);
 291                 miplevels = fd_sampler_last_level(cso) - lvl;
 292                 layers = cso->u.tex.last_layer - cso->u.tex.first_layer + 1;
 293
 294                 if (!fd_resource_level_linear(prsc, lvl))
 295                         tile_mode = fd_resource(prsc)->tile_mode;
 296
 297                 so->texconst0 |= A6XX_TEX_CONST_0_MIPLVLS(miplevels) |
 298                         A6XX_TEX_CONST_0_TILE_MODE(tile_mode);
 299                 so->texconst1 =
 300                         A6XX_TEX_CONST_1_WIDTH(u_minify(prsc->width0, lvl)) |
 301                         A6XX_TEX_CONST_1_HEIGHT(u_minify(prsc->height0, lvl));
 302                 so->texconst2 =
 303                         A6XX_TEX_CONST_2_FETCHSIZE(fd6_pipe2fetchsize(format)) |
 304                         A6XX_TEX_CONST_2_PITCH(
 305                                         util_format_get_nblocksx(
 306                                                         format, rsc->slices[lvl].pitch) * rsc->cpp);
 307                 so->offset = fd_resource_offset(rsc, lvl, cso->u.tex.first_layer);
 308         }
 309
 310         so->texconst2 |= A6XX_TEX_CONST_2_TYPE(fd6_tex_type(cso->target));
 311
 312         switch (cso->target) {
 313         case PIPE_TEXTURE_RECT:
 314         case PIPE_TEXTURE_1D:
 315         case PIPE_TEXTURE_2D:
 316                 so->texconst3 =
 317                         A6XX_TEX_CONST_3_ARRAY_PITCH(rsc->layer_size);
 318                 so->texconst5 =
 319                         A6XX_TEX_CONST_5_DEPTH(1);
 320                 break;
 321         case PIPE_TEXTURE_1D_ARRAY:
 322         case PIPE_TEXTURE_2D_ARRAY:
 323                 so->texconst3 =
 324                         A6XX_TEX_CONST_3_ARRAY_PITCH(rsc->layer_size);
 325                 so->texconst5 =
 326                         A6XX_TEX_CONST_5_DEPTH(layers);
 327                 break;
 328         case PIPE_TEXTURE_CUBE:
 329         case PIPE_TEXTURE_CUBE_ARRAY:
 330                 so->texconst3 =
 331                         A6XX_TEX_CONST_3_ARRAY_PITCH(rsc->layer_size);
 332                 so->texconst5 =
 333                         A6XX_TEX_CONST_5_DEPTH(layers / 6);
 334                 break;
 335         case PIPE_TEXTURE_3D:
 336                 so->texconst3 =
 337                         A6XX_TEX_CONST_3_MIN_LAYERSZ(rsc->slices[prsc->last_level].size0) |
 338                         A6XX_TEX_CONST_3_ARRAY_PITCH(rsc->slices[lvl].size0);
 339                 so->texconst5 =
 340                         A6XX_TEX_CONST_5_DEPTH(u_minify(prsc->depth0, lvl));
 341                 break;
 342         default:
 343                 break;
 344         }
 345
 346         return &so->base;
 347 }
 348
 349 static void
 350 fd6_sampler_view_destroy(struct pipe_context *pctx,
 351                 struct pipe_sampler_view *_view)
 352 {
 353         struct fd6_context *fd6_ctx = fd6_context(fd_context(pctx));
 354         struct fd6_pipe_sampler_view *view = fd6_pipe_sampler_view(_view);
 355
 356         hash_table_foreach(fd6_ctx->tex_cache, entry) {
 357                 struct fd6_texture_state *state = entry->data;
 358
 359                 for (unsigned i = 0; i < ARRAY_SIZE(state->key.view); i++) {
 360                         if (view->seqno == state->key.view[i].seqno) {
 361                                 fd6_texture_state_destroy(entry->data);
 362                                 _mesa_hash_table_remove(fd6_ctx->tex_cache, entry);
 363                                 break;
 364                         }
 365                 }
 366         }
 367
 368         pipe_resource_reference(&view->base.texture, NULL);
 369
 370         free(view);
 371 }
 372
 373 static void
 374 fd6_set_sampler_views(struct pipe_context *pctx, enum pipe_shader_type shader,
 375                 unsigned start, unsigned nr,
 376                 struct pipe_sampler_view **views)
 377 {
 378         struct fd_context *ctx = fd_context(pctx);
 379         struct fd6_context *fd6_ctx = fd6_context(ctx);
 380         uint16_t astc_srgb = 0;
 381         unsigned i;
 382
 383         for (i = 0; i < nr; i++) {
 384                 if (views[i]) {
 385                         struct fd6_pipe_sampler_view *view =
 386                                         fd6_pipe_sampler_view(views[i]);
 387                         if (view->astc_srgb)
 388                                 astc_srgb |= (1 << i);
 389                 }
 390         }
 391
 392         fd_set_sampler_views(pctx, shader, start, nr, views);
 393
 394         if (shader == PIPE_SHADER_FRAGMENT) {
 395                 fd6_ctx->fastc_srgb = astc_srgb;
 396         } else if (shader == PIPE_SHADER_VERTEX) {
 397                 fd6_ctx->vastc_srgb = astc_srgb;
 398         }
 399 }
 400
 401
 402 static uint32_t
 403 key_hash(const void *_key)
 404 {
 405         const struct fd6_texture_key *key = _key;
 406         uint32_t hash = _mesa_fnv32_1a_offset_bias;
 407         hash = _mesa_fnv32_1a_accumulate_block(hash, key, sizeof(*key));
 408         return hash;
 409 }
 410
 411 static bool
 412 key_equals(const void *_a, const void *_b)
 413 {
 414         const struct fd6_texture_key *a = _a;
 415         const struct fd6_texture_key *b = _b;
 416         return memcmp(a, b, sizeof(struct fd6_texture_key)) == 0;
 417 }
 418
 419 struct fd6_texture_state *
 420 fd6_texture_state(struct fd_context *ctx, enum a6xx_state_block sb,
 421                 struct fd_texture_stateobj *tex)
 422 {
 423         struct fd6_context *fd6_ctx = fd6_context(ctx);
 424         struct fd6_texture_key key;
 425         bool needs_border = false;
 426
 427         memset(&key, 0, sizeof(key));
 428
 429         for (unsigned i = 0; i < tex->num_textures; i++) {
 430                 if (!tex->textures[i])
 431                         continue;
 432
 433                 struct fd6_pipe_sampler_view *view =
 434                         fd6_pipe_sampler_view(tex->textures[i]);
 435
 436                 key.view[i].rsc_seqno = fd_resource(view->base.texture)->seqno;
 437                 key.view[i].seqno = view->seqno;
 438         }
 439
 440         for (unsigned i = 0; i < tex->num_samplers; i++) {
 441                 if (!tex->samplers[i])
 442                         continue;
 443
 444                 struct fd6_sampler_stateobj *sampler =
 445                         fd6_sampler_stateobj(tex->samplers[i]);
 446
 447                 key.samp[i].seqno = sampler->seqno;
 448
 449                 needs_border |= sampler->needs_border;
 450         }
 451
 452         /* This will need update for HS/DS/GS: */
 453         if (unlikely(needs_border && (sb == SB6_FS_TEX))) {
 454                 /* TODO we could probably use fixed offsets for each shader
 455                  * stage and avoid the need for # of VS samplers to be part
 456                  * of the FS tex state.. but I don't think our handling of
 457                  * BCOLOR_OFFSET is actually correct, and trying to use a
 458                  * hard coded offset of 16 breaks things.
 459                  *
 460                  * Note that when this changes, then a corresponding change
 461                  * in emit_border_color() is also needed.
 462                  */
 463                 key.bcolor_offset = ctx->tex[PIPE_SHADER_VERTEX].num_samplers;
 464         }
 465
 466         uint32_t hash = key_hash(&key);
 467         struct hash_entry *entry =
 468                 _mesa_hash_table_search_pre_hashed(fd6_ctx->tex_cache, hash, &key);
 469
 470         if (entry) {
 471                 return entry->data;
 472         }
 473
 474         struct fd6_texture_state *state = CALLOC_STRUCT(fd6_texture_state);
 475
 476         state->key = key;
 477         state->stateobj = fd_ringbuffer_new_object(ctx->pipe, 0x1000);
 478         state->needs_border = needs_border;
 479
 480         fd6_emit_textures(ctx->pipe, state->stateobj, sb, tex, key.bcolor_offset);
 481
 482         /* NOTE: uses copy of key in state obj, because pointer passed by caller
 483          * is probably on the stack
 484          */
 485         _mesa_hash_table_insert_pre_hashed(fd6_ctx->tex_cache, hash,
 486                         &state->key, state);
 487
 488         return state;
 489 }
 490
 491 static void
 492 fd6_texture_state_destroy(struct fd6_texture_state *state)
 493 {
 494         fd_ringbuffer_del(state->stateobj);
 495         free(state);
 496 }
 497
 498 void
 499 fd6_texture_init(struct pipe_context *pctx)
 500 {
 501         struct fd6_context *fd6_ctx = fd6_context(fd_context(pctx));
 502
 503         pctx->create_sampler_state = fd6_sampler_state_create;
 504         pctx->delete_sampler_state = fd6_sampler_state_delete;
 505         pctx->bind_sampler_states = fd6_sampler_states_bind;
 506
 507         pctx->create_sampler_view = fd6_sampler_view_create;
 508         pctx->sampler_view_destroy = fd6_sampler_view_destroy;
 509         pctx->set_sampler_views = fd6_set_sampler_views;
 510
 511         fd6_ctx->tex_cache = _mesa_hash_table_create(NULL, key_hash, key_equals);
 512 }
 513
 514 void
 515 fd6_texture_fini(struct pipe_context *pctx)
 516 {
 517         struct fd6_context *fd6_ctx = fd6_context(fd_context(pctx));
 518
 519         hash_table_foreach(fd6_ctx->tex_cache, entry) {
 520                 fd6_texture_state_destroy(entry->data);
 521         }
 522         ralloc_free(fd6_ctx->tex_cache);
 523 }