src/gallium/drivers/freedreno/a6xx/fd6_zsa.c

   1 /*
   2  * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
   3  * Copyright © 2018 Google, Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  22  * SOFTWARE.
  23  *
  24  * Authors:
  25  *    Rob Clark <robclark@freedesktop.org>
  26  */
  27
  28
  29 #include "pipe/p_state.h"
  30 #include "util/u_string.h"
  31 #include "util/u_memory.h"
  32
  33 #include "fd6_zsa.h"
  34 #include "fd6_context.h"
  35 #include "fd6_format.h"
  36
  37 /* update lza state based on stencil/alpha-test func: */
  38 static void
  39 update_lrz_sa(struct fd6_zsa_stateobj *so, enum pipe_compare_func func)
  40 {
  41         switch (func) {
  42         case PIPE_FUNC_ALWAYS:
  43                 /* nothing to do for LRZ: */
  44                 break;
  45         case PIPE_FUNC_NEVER:
  46                 /* fragment never passes, disable lrz_write for this draw: */
  47                 so->lrz_write = false;
  48                 break;
  49         default:
  50                 /* whether the fragment passes or not depends on result
  51                  * of stencil test, which we cannot know when doing binning
  52                  * pass:
  53                  *
  54                  * TODO we maybe don't have to invalidate_lrz, depending on
  55                  * the depth/stencil func?  Ie. if there is an opaque surface
  56                  * behind what is currently being drawn, we could just disable
  57                  * lrz_write for a conservative but correct result?
  58                  */
  59                 so->invalidate_lrz = true;
  60                 so->lrz_write = false;
  61                 break;
  62         }
  63 }
  64
  65 void *
  66 fd6_zsa_state_create(struct pipe_context *pctx,
  67                 const struct pipe_depth_stencil_alpha_state *cso)
  68 {
  69         struct fd_context *ctx = fd_context(pctx);
  70         struct fd6_zsa_stateobj *so;
  71
  72         so = CALLOC_STRUCT(fd6_zsa_stateobj);
  73         if (!so)
  74                 return NULL;
  75
  76         so->base = *cso;
  77
  78         so->rb_depth_cntl |=
  79                 A6XX_RB_DEPTH_CNTL_ZFUNC(cso->depth.func); /* maps 1:1 */
  80
  81         if (cso->depth.enabled) {
  82                 so->rb_depth_cntl |=
  83                         A6XX_RB_DEPTH_CNTL_Z_ENABLE |
  84                         A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE;
  85
  86                 so->gras_lrz_cntl |= A6XX_GRAS_LRZ_CNTL_Z_TEST_ENABLE;
  87
  88                 if (cso->depth.writemask) {
  89                         so->lrz_write = true;
  90                 }
  91
  92                 switch (cso->depth.func) {
  93                 case PIPE_FUNC_LESS:
  94                 case PIPE_FUNC_LEQUAL:
  95                         so->gras_lrz_cntl |= A6XX_GRAS_LRZ_CNTL_ENABLE;
  96                         so->rb_lrz_cntl |= A6XX_RB_LRZ_CNTL_ENABLE;
  97                         break;
  98
  99                 case PIPE_FUNC_GREATER:
 100                 case PIPE_FUNC_GEQUAL:
 101                         so->gras_lrz_cntl |= A6XX_GRAS_LRZ_CNTL_ENABLE | A6XX_GRAS_LRZ_CNTL_GREATER;
 102                         so->rb_lrz_cntl |= A6XX_RB_LRZ_CNTL_ENABLE;
 103                         break;
 104
 105                 case PIPE_FUNC_NEVER:
 106                         so->gras_lrz_cntl |= A6XX_GRAS_LRZ_CNTL_ENABLE;
 107                         so->rb_lrz_cntl |= A6XX_RB_LRZ_CNTL_ENABLE;
 108                         so->lrz_write = false;
 109                         break;
 110
 111                 case PIPE_FUNC_EQUAL:
 112                 case PIPE_FUNC_NOTEQUAL:
 113                 case PIPE_FUNC_ALWAYS:
 114                         so->lrz_write = false;
 115                         so->invalidate_lrz = true;
 116                         break;
 117                 }
 118         }
 119
 120         if (cso->depth.writemask)
 121                 so->rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE;
 122
 123         if (cso->stencil[0].enabled) {
 124                 const struct pipe_stencil_state *s = &cso->stencil[0];
 125
 126                 /* stencil test happens before depth test, so without performing
 127                  * stencil test we don't really know what the updates to the
 128                  * depth buffer will be.
 129                  */
 130                 update_lrz_sa(so, s->func);
 131
 132                 so->rb_stencil_control |=
 133                         A6XX_RB_STENCIL_CONTROL_STENCIL_READ |
 134                         A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE |
 135                         A6XX_RB_STENCIL_CONTROL_FUNC(s->func) | /* maps 1:1 */
 136                         A6XX_RB_STENCIL_CONTROL_FAIL(fd_stencil_op(s->fail_op)) |
 137                         A6XX_RB_STENCIL_CONTROL_ZPASS(fd_stencil_op(s->zpass_op)) |
 138                         A6XX_RB_STENCIL_CONTROL_ZFAIL(fd_stencil_op(s->zfail_op));
 139
 140                 so->rb_stencilmask = A6XX_RB_STENCILMASK_MASK(s->valuemask);
 141                 so->rb_stencilwrmask = A6XX_RB_STENCILWRMASK_WRMASK(s->writemask);
 142
 143                 if (cso->stencil[1].enabled) {
 144                         const struct pipe_stencil_state *bs = &cso->stencil[1];
 145
 146                         update_lrz_sa(so, bs->func);
 147
 148                         so->rb_stencil_control |=
 149                                 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF |
 150                                 A6XX_RB_STENCIL_CONTROL_FUNC_BF(bs->func) | /* maps 1:1 */
 151                                 A6XX_RB_STENCIL_CONTROL_FAIL_BF(fd_stencil_op(bs->fail_op)) |
 152                                 A6XX_RB_STENCIL_CONTROL_ZPASS_BF(fd_stencil_op(bs->zpass_op)) |
 153                                 A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(fd_stencil_op(bs->zfail_op));
 154
 155                         so->rb_stencilmask |= A6XX_RB_STENCILMASK_BFMASK(bs->valuemask);
 156                         so->rb_stencilwrmask |= A6XX_RB_STENCILWRMASK_BFWRMASK(bs->writemask);
 157                 }
 158         }
 159
 160         if (cso->alpha.enabled) {
 161                 /* stencil test happens before depth test, so without performing
 162                  * stencil test we don't really know what the updates to the
 163                  * depth buffer will be.
 164                  */
 165                 update_lrz_sa(so, cso->alpha.func);
 166
 167                 uint32_t ref = cso->alpha.ref_value * 255.0;
 168                 so->rb_alpha_control =
 169                         A6XX_RB_ALPHA_CONTROL_ALPHA_TEST |
 170                         A6XX_RB_ALPHA_CONTROL_ALPHA_REF(ref) |
 171                         A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(cso->alpha.func);
 172 //              so->rb_depth_control |=
 173 //                      A6XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE;
 174         }
 175
 176         so->stateobj = fd_ringbuffer_new_object(ctx->pipe, 9 * 4);
 177         struct fd_ringbuffer *ring = so->stateobj;
 178
 179         OUT_PKT4(ring, REG_A6XX_RB_ALPHA_CONTROL, 1);
 180         OUT_RING(ring, so->rb_alpha_control);
 181
 182         OUT_PKT4(ring, REG_A6XX_RB_STENCIL_CONTROL, 1);
 183         OUT_RING(ring, so->rb_stencil_control);
 184
 185         OUT_PKT4(ring, REG_A6XX_RB_DEPTH_CNTL, 1);
 186         OUT_RING(ring, so->rb_depth_cntl);
 187
 188         OUT_PKT4(ring, REG_A6XX_RB_STENCILMASK, 2);
 189         OUT_RING(ring, so->rb_stencilmask);
 190         OUT_RING(ring, so->rb_stencilwrmask);
 191
 192         so->stateobj_no_alpha = fd_ringbuffer_new_object(ctx->pipe, 9 * 4);
 193         ring = so->stateobj_no_alpha;
 194
 195         OUT_PKT4(ring, REG_A6XX_RB_ALPHA_CONTROL, 1);
 196         OUT_RING(ring, so->rb_alpha_control & ~A6XX_RB_ALPHA_CONTROL_ALPHA_TEST);
 197
 198         OUT_PKT4(ring, REG_A6XX_RB_STENCIL_CONTROL, 1);
 199         OUT_RING(ring, so->rb_stencil_control);
 200
 201         OUT_PKT4(ring, REG_A6XX_RB_DEPTH_CNTL, 1);
 202         OUT_RING(ring, so->rb_depth_cntl);
 203
 204         OUT_PKT4(ring, REG_A6XX_RB_STENCILMASK, 2);
 205         OUT_RING(ring, so->rb_stencilmask);
 206         OUT_RING(ring, so->rb_stencilwrmask);
 207
 208         return so;
 209 }
 210
 211 void
 212 fd6_depth_stencil_alpha_state_delete(struct pipe_context *pctx, void *hwcso)
 213 {
 214         struct fd6_zsa_stateobj *so = hwcso;
 215
 216         fd_ringbuffer_del(so->stateobj);
 217         fd_ringbuffer_del(so->stateobj_no_alpha);
 218         FREE(hwcso);
 219 }