src/gallium/drivers/freedreno/a6xx/fd6_zsa.c

   1 /*
   2  * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
   3  * Copyright © 2018 Google, Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  22  * SOFTWARE.
  23  *
  24  * Authors:
  25  *    Rob Clark <robclark@freedesktop.org>
  26  */
  27
  28
  29 #include "pipe/p_state.h"
  30 #include "util/u_string.h"
  31 #include "util/u_memory.h"
  32
  33 #include "fd6_zsa.h"
  34 #include "fd6_context.h"
  35 #include "fd6_format.h"
  36
  37 void *
  38 fd6_zsa_state_create(struct pipe_context *pctx,
  39                 const struct pipe_depth_stencil_alpha_state *cso)
  40 {
  41         struct fd_context *ctx = fd_context(pctx);
  42         struct fd6_zsa_stateobj *so;
  43
  44         so = CALLOC_STRUCT(fd6_zsa_stateobj);
  45         if (!so)
  46                 return NULL;
  47
  48         so->base = *cso;
  49
  50         so->rb_depth_cntl |=
  51                 A6XX_RB_DEPTH_CNTL_ZFUNC(cso->depth.func); /* maps 1:1 */
  52
  53         if (cso->depth.enabled) {
  54                 so->rb_depth_cntl |=
  55                         A6XX_RB_DEPTH_CNTL_Z_ENABLE |
  56                         A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE;
  57
  58                 so->gras_lrz_cntl |= A6XX_GRAS_LRZ_CNTL_Z_TEST_ENABLE;
  59
  60                 if (cso->depth.writemask) {
  61                         so->lrz_write = true;
  62                 }
  63
  64                 switch (cso->depth.func) {
  65                 case PIPE_FUNC_LESS:
  66                 case PIPE_FUNC_LEQUAL:
  67                         so->gras_lrz_cntl |= A6XX_GRAS_LRZ_CNTL_ENABLE;
  68                         so->rb_lrz_cntl |= A6XX_RB_LRZ_CNTL_ENABLE;
  69                         break;
  70
  71                 case PIPE_FUNC_GREATER:
  72                 case PIPE_FUNC_GEQUAL:
  73                         so->gras_lrz_cntl |= A6XX_GRAS_LRZ_CNTL_ENABLE | A6XX_GRAS_LRZ_CNTL_GREATER;
  74                         so->rb_lrz_cntl |= A6XX_RB_LRZ_CNTL_ENABLE;
  75                         break;
  76
  77                 case PIPE_FUNC_NEVER:
  78                         so->gras_lrz_cntl |= A6XX_GRAS_LRZ_CNTL_ENABLE;
  79                         so->rb_lrz_cntl |= A6XX_RB_LRZ_CNTL_ENABLE;
  80                         so->lrz_write = false;
  81                         break;
  82
  83                 case PIPE_FUNC_EQUAL:
  84                 case PIPE_FUNC_NOTEQUAL:
  85                 case PIPE_FUNC_ALWAYS:
  86                         so->lrz_write = false;
  87                         so->invalidate_lrz = true;
  88                         break;
  89                 }
  90         }
  91
  92         if (cso->depth.writemask)
  93                 so->rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE;
  94
  95         if (cso->stencil[0].enabled) {
  96                 const struct pipe_stencil_state *s = &cso->stencil[0];
  97
  98                 /* stencil test happens before depth test, so without performing
  99                  * stencil test we don't really know what the updates to the
 100                  * depth buffer will be.
 101                  */
 102                 so->lrz_write = false;
 103                 so->invalidate_lrz = true;
 104
 105                 so->rb_stencil_control |=
 106                         A6XX_RB_STENCIL_CONTROL_STENCIL_READ |
 107                         A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE |
 108                         A6XX_RB_STENCIL_CONTROL_FUNC(s->func) | /* maps 1:1 */
 109                         A6XX_RB_STENCIL_CONTROL_FAIL(fd_stencil_op(s->fail_op)) |
 110                         A6XX_RB_STENCIL_CONTROL_ZPASS(fd_stencil_op(s->zpass_op)) |
 111                         A6XX_RB_STENCIL_CONTROL_ZFAIL(fd_stencil_op(s->zfail_op));
 112
 113                 so->rb_stencilmask = A6XX_RB_STENCILMASK_MASK(s->valuemask);
 114                 so->rb_stencilwrmask = A6XX_RB_STENCILWRMASK_WRMASK(s->writemask);
 115
 116                 if (cso->stencil[1].enabled) {
 117                         const struct pipe_stencil_state *bs = &cso->stencil[1];
 118
 119                         so->rb_stencil_control |=
 120                                 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF |
 121                                 A6XX_RB_STENCIL_CONTROL_FUNC_BF(bs->func) | /* maps 1:1 */
 122                                 A6XX_RB_STENCIL_CONTROL_FAIL_BF(fd_stencil_op(bs->fail_op)) |
 123                                 A6XX_RB_STENCIL_CONTROL_ZPASS_BF(fd_stencil_op(bs->zpass_op)) |
 124                                 A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(fd_stencil_op(bs->zfail_op));
 125
 126                         so->rb_stencilmask |= A6XX_RB_STENCILMASK_BFMASK(bs->valuemask);
 127                         so->rb_stencilwrmask |= A6XX_RB_STENCILWRMASK_BFWRMASK(bs->writemask);
 128                 }
 129         }
 130
 131         if (cso->alpha.enabled) {
 132                 uint32_t ref = cso->alpha.ref_value * 255.0;
 133                 so->rb_alpha_control =
 134                         A6XX_RB_ALPHA_CONTROL_ALPHA_TEST |
 135                         A6XX_RB_ALPHA_CONTROL_ALPHA_REF(ref) |
 136                         A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(cso->alpha.func);
 137 //              so->rb_depth_control |=
 138 //                      A6XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE;
 139         }
 140
 141         so->stateobj = fd_ringbuffer_new_object(ctx->pipe, 9 * 4);
 142         struct fd_ringbuffer *ring = so->stateobj;
 143
 144         OUT_PKT4(ring, REG_A6XX_RB_ALPHA_CONTROL, 1);
 145         OUT_RING(ring, so->rb_alpha_control);
 146
 147         OUT_PKT4(ring, REG_A6XX_RB_STENCIL_CONTROL, 1);
 148         OUT_RING(ring, so->rb_stencil_control);
 149
 150         OUT_PKT4(ring, REG_A6XX_RB_DEPTH_CNTL, 1);
 151         OUT_RING(ring, so->rb_depth_cntl);
 152
 153         OUT_PKT4(ring, REG_A6XX_RB_STENCILMASK, 2);
 154         OUT_RING(ring, so->rb_stencilmask);
 155         OUT_RING(ring, so->rb_stencilwrmask);
 156
 157         so->stateobj_no_alpha = fd_ringbuffer_new_object(ctx->pipe, 9 * 4);
 158         ring = so->stateobj_no_alpha;
 159
 160         OUT_PKT4(ring, REG_A6XX_RB_ALPHA_CONTROL, 1);
 161         OUT_RING(ring, so->rb_alpha_control & ~A6XX_RB_ALPHA_CONTROL_ALPHA_TEST);
 162
 163         OUT_PKT4(ring, REG_A6XX_RB_STENCIL_CONTROL, 1);
 164         OUT_RING(ring, so->rb_stencil_control);
 165
 166         OUT_PKT4(ring, REG_A6XX_RB_DEPTH_CNTL, 1);
 167         OUT_RING(ring, so->rb_depth_cntl);
 168
 169         OUT_PKT4(ring, REG_A6XX_RB_STENCILMASK, 2);
 170         OUT_RING(ring, so->rb_stencilmask);
 171         OUT_RING(ring, so->rb_stencilwrmask);
 172
 173         return so;
 174 }
 175
 176 void
 177 fd6_depth_stencil_alpha_state_delete(struct pipe_context *pctx, void *hwcso)
 178 {
 179         struct fd6_zsa_stateobj *so = hwcso;
 180
 181         fd_ringbuffer_del(so->stateobj);
 182         fd_ringbuffer_del(so->stateobj_no_alpha);
 183         FREE(hwcso);
 184 }