src/gallium/drivers/freedreno/a6xx/fd6_zsa.c

   1 /*
   2  * Copyright (C) 2016 Rob Clark <robclark@freedesktop.org>
   3  * Copyright © 2018 Google, Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  22  * SOFTWARE.
  23  *
  24  * Authors:
  25  *    Rob Clark <robclark@freedesktop.org>
  26  */
  27
  28
  29 #include "pipe/p_state.h"
  30 #include "util/u_string.h"
  31 #include "util/u_memory.h"
  32
  33 #include "fd6_zsa.h"
  34 #include "fd6_context.h"
  35 #include "fd6_format.h"
  36
  37 void *
  38 fd6_zsa_state_create(struct pipe_context *pctx,
  39                 const struct pipe_depth_stencil_alpha_state *cso)
  40 {
  41         struct fd6_zsa_stateobj *so;
  42
  43         so = CALLOC_STRUCT(fd6_zsa_stateobj);
  44         if (!so)
  45                 return NULL;
  46
  47         so->base = *cso;
  48
  49         switch (cso->depth.func) {
  50         case PIPE_FUNC_LESS:
  51         case PIPE_FUNC_LEQUAL:
  52                 so->gras_lrz_cntl = A6XX_GRAS_LRZ_CNTL_ENABLE;
  53                 so->rb_lrz_cntl = A6XX_RB_LRZ_CNTL_ENABLE;
  54                 break;
  55
  56         case PIPE_FUNC_GREATER:
  57         case PIPE_FUNC_GEQUAL:
  58                 so->gras_lrz_cntl = A6XX_GRAS_LRZ_CNTL_ENABLE | A6XX_GRAS_LRZ_CNTL_GREATER;
  59                 so->rb_lrz_cntl = A6XX_RB_LRZ_CNTL_ENABLE;
  60                 break;
  61
  62         default:
  63                 /* LRZ not enabled */
  64                 so->gras_lrz_cntl = 0;
  65                 break;
  66         }
  67
  68         if (cso->depth.writemask) {
  69                 if (cso->depth.enabled)
  70                         so->gras_lrz_cntl |= A6XX_GRAS_LRZ_CNTL_UNK4;
  71                 so->lrz_write = true;
  72         }
  73
  74         so->rb_depth_cntl |=
  75                 A6XX_RB_DEPTH_CNTL_ZFUNC(cso->depth.func); /* maps 1:1 */
  76
  77         if (cso->depth.enabled)
  78                 so->rb_depth_cntl |=
  79                         A6XX_RB_DEPTH_CNTL_Z_ENABLE |
  80                         A6XX_RB_DEPTH_CNTL_Z_TEST_ENABLE;
  81
  82         if (cso->depth.writemask)
  83                 so->rb_depth_cntl |= A6XX_RB_DEPTH_CNTL_Z_WRITE_ENABLE;
  84
  85         if (cso->stencil[0].enabled) {
  86                 const struct pipe_stencil_state *s = &cso->stencil[0];
  87
  88                 so->rb_stencil_control |=
  89                         A6XX_RB_STENCIL_CONTROL_STENCIL_READ |
  90                         A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE |
  91                         A6XX_RB_STENCIL_CONTROL_FUNC(s->func) | /* maps 1:1 */
  92                         A6XX_RB_STENCIL_CONTROL_FAIL(fd_stencil_op(s->fail_op)) |
  93                         A6XX_RB_STENCIL_CONTROL_ZPASS(fd_stencil_op(s->zpass_op)) |
  94                         A6XX_RB_STENCIL_CONTROL_ZFAIL(fd_stencil_op(s->zfail_op));
  95
  96                 so->rb_stencilmask = A6XX_RB_STENCILMASK_MASK(s->valuemask);
  97                 so->rb_stencilwrmask = A6XX_RB_STENCILWRMASK_WRMASK(s->writemask);
  98
  99                 if (cso->stencil[1].enabled) {
 100                         const struct pipe_stencil_state *bs = &cso->stencil[1];
 101
 102                         so->rb_stencil_control |=
 103                                 A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF |
 104                                 A6XX_RB_STENCIL_CONTROL_FUNC_BF(bs->func) | /* maps 1:1 */
 105                                 A6XX_RB_STENCIL_CONTROL_FAIL_BF(fd_stencil_op(bs->fail_op)) |
 106                                 A6XX_RB_STENCIL_CONTROL_ZPASS_BF(fd_stencil_op(bs->zpass_op)) |
 107                                 A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(fd_stencil_op(bs->zfail_op));
 108
 109                         so->rb_stencilmask |= A6XX_RB_STENCILMASK_BFMASK(bs->valuemask);
 110                         so->rb_stencilwrmask |= A6XX_RB_STENCILWRMASK_BFWRMASK(bs->writemask);
 111                 }
 112         }
 113
 114         if (cso->alpha.enabled) {
 115                 uint32_t ref = cso->alpha.ref_value * 255.0;
 116                 so->rb_alpha_control =
 117                         A6XX_RB_ALPHA_CONTROL_ALPHA_TEST |
 118                         A6XX_RB_ALPHA_CONTROL_ALPHA_REF(ref) |
 119                         A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(cso->alpha.func);
 120 //              so->rb_depth_control |=
 121 //                      A6XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE;
 122         }
 123
 124         return so;
 125 }