1 #ifndef ADRENO_COMMON_XML
2 #define ADRENO_COMMON_XML
4 /* Autogenerated file, DO NOT EDIT manually!
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
10 The rules-ng-ng source files this header was generated from are:
11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 398 bytes, from 2015-09-24 17:25:31)
12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
13 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14)
14 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10755 bytes, from 2015-09-14 20:46:55)
15 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14968 bytes, from 2015-05-20 20:12:27)
16 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 68291 bytes, from 2015-11-17 16:39:59)
17 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 64038 bytes, from 2015-11-17 16:37:36)
18 - /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00)
20 Copyright (C) 2013-2015 by the following authors:
21 - Rob Clark <robdclark@gmail.com> (robclark)
23 Permission is hereby granted, free of charge, to any person obtaining
24 a copy of this software and associated documentation files (the
25 "Software"), to deal in the Software without restriction, including
26 without limitation the rights to use, copy, modify, merge, publish,
27 distribute, sublicense, and/or sell copies of the Software, and to
28 permit persons to whom the Software is furnished to do so, subject to
29 the following conditions:
31 The above copyright notice and this permission notice (including the
32 next paragraph) shall be included in all copies or substantial
33 portions of the Software.
35 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
37 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
38 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
39 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
40 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
41 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
45 enum adreno_pa_su_sc_draw
{
48 PC_DRAW_TRIANGLES
= 2,
51 enum adreno_compare_func
{
62 enum adreno_stencil_op
{
66 STENCIL_INCR_CLAMP
= 3,
67 STENCIL_DECR_CLAMP
= 4,
69 STENCIL_INCR_WRAP
= 6,
70 STENCIL_DECR_WRAP
= 7,
73 enum adreno_rb_blend_factor
{
77 FACTOR_ONE_MINUS_SRC_COLOR
= 5,
79 FACTOR_ONE_MINUS_SRC_ALPHA
= 7,
81 FACTOR_ONE_MINUS_DST_COLOR
= 9,
82 FACTOR_DST_ALPHA
= 10,
83 FACTOR_ONE_MINUS_DST_ALPHA
= 11,
84 FACTOR_CONSTANT_COLOR
= 12,
85 FACTOR_ONE_MINUS_CONSTANT_COLOR
= 13,
86 FACTOR_CONSTANT_ALPHA
= 14,
87 FACTOR_ONE_MINUS_CONSTANT_ALPHA
= 15,
88 FACTOR_SRC_ALPHA_SATURATE
= 16,
89 FACTOR_SRC1_COLOR
= 20,
90 FACTOR_ONE_MINUS_SRC1_COLOR
= 21,
91 FACTOR_SRC1_ALPHA
= 22,
92 FACTOR_ONE_MINUS_SRC1_ALPHA
= 23,
95 enum adreno_rb_surface_endian
{
104 enum adreno_rb_dither_mode
{
107 DITHER_IF_ALPHA_OFF
= 2,
110 enum adreno_rb_depth_format
{
116 enum adreno_rb_copy_control_mode
{
119 RB_COPY_DEPTH_STENCIL
= 5,
125 ROP_AND_INVERTED
= 2,
126 ROP_COPY_INVERTED
= 3,
134 ROP_OR_INVERTED
= 11,
141 enum a3xx_render_mode
{
142 RB_RENDERING_PASS
= 0,
148 enum a3xx_msaa_samples
{
154 enum a3xx_threadmode
{
159 enum a3xx_instrbuffermode
{
164 enum a3xx_threadsize
{
169 enum a3xx_color_swap
{
176 #define REG_AXXX_CP_RB_BASE 0x000001c0
178 #define REG_AXXX_CP_RB_CNTL 0x000001c1
179 #define AXXX_CP_RB_CNTL_BUFSZ__MASK 0x0000003f
180 #define AXXX_CP_RB_CNTL_BUFSZ__SHIFT 0
181 static inline uint32_t AXXX_CP_RB_CNTL_BUFSZ(uint32_t val
)
183 return ((val
) << AXXX_CP_RB_CNTL_BUFSZ__SHIFT
) & AXXX_CP_RB_CNTL_BUFSZ__MASK
;
185 #define AXXX_CP_RB_CNTL_BLKSZ__MASK 0x00003f00
186 #define AXXX_CP_RB_CNTL_BLKSZ__SHIFT 8
187 static inline uint32_t AXXX_CP_RB_CNTL_BLKSZ(uint32_t val
)
189 return ((val
) << AXXX_CP_RB_CNTL_BLKSZ__SHIFT
) & AXXX_CP_RB_CNTL_BLKSZ__MASK
;
191 #define AXXX_CP_RB_CNTL_BUF_SWAP__MASK 0x00030000
192 #define AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT 16
193 static inline uint32_t AXXX_CP_RB_CNTL_BUF_SWAP(uint32_t val
)
195 return ((val
) << AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT
) & AXXX_CP_RB_CNTL_BUF_SWAP__MASK
;
197 #define AXXX_CP_RB_CNTL_POLL_EN 0x00100000
198 #define AXXX_CP_RB_CNTL_NO_UPDATE 0x08000000
199 #define AXXX_CP_RB_CNTL_RPTR_WR_EN 0x80000000
201 #define REG_AXXX_CP_RB_RPTR_ADDR 0x000001c3
202 #define AXXX_CP_RB_RPTR_ADDR_SWAP__MASK 0x00000003
203 #define AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT 0
204 static inline uint32_t AXXX_CP_RB_RPTR_ADDR_SWAP(uint32_t val
)
206 return ((val
) << AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT
) & AXXX_CP_RB_RPTR_ADDR_SWAP__MASK
;
208 #define AXXX_CP_RB_RPTR_ADDR_ADDR__MASK 0xfffffffc
209 #define AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT 2
210 static inline uint32_t AXXX_CP_RB_RPTR_ADDR_ADDR(uint32_t val
)
212 return ((val
>> 2) << AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT
) & AXXX_CP_RB_RPTR_ADDR_ADDR__MASK
;
215 #define REG_AXXX_CP_RB_RPTR 0x000001c4
217 #define REG_AXXX_CP_RB_WPTR 0x000001c5
219 #define REG_AXXX_CP_RB_WPTR_DELAY 0x000001c6
221 #define REG_AXXX_CP_RB_RPTR_WR 0x000001c7
223 #define REG_AXXX_CP_RB_WPTR_BASE 0x000001c8
225 #define REG_AXXX_CP_QUEUE_THRESHOLDS 0x000001d5
226 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK 0x0000000f
227 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT 0
228 static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(uint32_t val
)
230 return ((val
) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT
) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK
;
232 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK 0x00000f00
233 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT 8
234 static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(uint32_t val
)
236 return ((val
) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT
) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK
;
238 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK 0x000f0000
239 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT 16
240 static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START(uint32_t val
)
242 return ((val
) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT
) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK
;
245 #define REG_AXXX_CP_MEQ_THRESHOLDS 0x000001d6
246 #define AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK 0x001f0000
247 #define AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT 16
248 static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_MEQ_END(uint32_t val
)
250 return ((val
) << AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT
) & AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK
;
252 #define AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK 0x1f000000
253 #define AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT 24
254 static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_ROQ_END(uint32_t val
)
256 return ((val
) << AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT
) & AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK
;
259 #define REG_AXXX_CP_CSQ_AVAIL 0x000001d7
260 #define AXXX_CP_CSQ_AVAIL_RING__MASK 0x0000007f
261 #define AXXX_CP_CSQ_AVAIL_RING__SHIFT 0
262 static inline uint32_t AXXX_CP_CSQ_AVAIL_RING(uint32_t val
)
264 return ((val
) << AXXX_CP_CSQ_AVAIL_RING__SHIFT
) & AXXX_CP_CSQ_AVAIL_RING__MASK
;
266 #define AXXX_CP_CSQ_AVAIL_IB1__MASK 0x00007f00
267 #define AXXX_CP_CSQ_AVAIL_IB1__SHIFT 8
268 static inline uint32_t AXXX_CP_CSQ_AVAIL_IB1(uint32_t val
)
270 return ((val
) << AXXX_CP_CSQ_AVAIL_IB1__SHIFT
) & AXXX_CP_CSQ_AVAIL_IB1__MASK
;
272 #define AXXX_CP_CSQ_AVAIL_IB2__MASK 0x007f0000
273 #define AXXX_CP_CSQ_AVAIL_IB2__SHIFT 16
274 static inline uint32_t AXXX_CP_CSQ_AVAIL_IB2(uint32_t val
)
276 return ((val
) << AXXX_CP_CSQ_AVAIL_IB2__SHIFT
) & AXXX_CP_CSQ_AVAIL_IB2__MASK
;
279 #define REG_AXXX_CP_STQ_AVAIL 0x000001d8
280 #define AXXX_CP_STQ_AVAIL_ST__MASK 0x0000007f
281 #define AXXX_CP_STQ_AVAIL_ST__SHIFT 0
282 static inline uint32_t AXXX_CP_STQ_AVAIL_ST(uint32_t val
)
284 return ((val
) << AXXX_CP_STQ_AVAIL_ST__SHIFT
) & AXXX_CP_STQ_AVAIL_ST__MASK
;
287 #define REG_AXXX_CP_MEQ_AVAIL 0x000001d9
288 #define AXXX_CP_MEQ_AVAIL_MEQ__MASK 0x0000001f
289 #define AXXX_CP_MEQ_AVAIL_MEQ__SHIFT 0
290 static inline uint32_t AXXX_CP_MEQ_AVAIL_MEQ(uint32_t val
)
292 return ((val
) << AXXX_CP_MEQ_AVAIL_MEQ__SHIFT
) & AXXX_CP_MEQ_AVAIL_MEQ__MASK
;
295 #define REG_AXXX_SCRATCH_UMSK 0x000001dc
296 #define AXXX_SCRATCH_UMSK_UMSK__MASK 0x000000ff
297 #define AXXX_SCRATCH_UMSK_UMSK__SHIFT 0
298 static inline uint32_t AXXX_SCRATCH_UMSK_UMSK(uint32_t val
)
300 return ((val
) << AXXX_SCRATCH_UMSK_UMSK__SHIFT
) & AXXX_SCRATCH_UMSK_UMSK__MASK
;
302 #define AXXX_SCRATCH_UMSK_SWAP__MASK 0x00030000
303 #define AXXX_SCRATCH_UMSK_SWAP__SHIFT 16
304 static inline uint32_t AXXX_SCRATCH_UMSK_SWAP(uint32_t val
)
306 return ((val
) << AXXX_SCRATCH_UMSK_SWAP__SHIFT
) & AXXX_SCRATCH_UMSK_SWAP__MASK
;
309 #define REG_AXXX_SCRATCH_ADDR 0x000001dd
311 #define REG_AXXX_CP_ME_RDADDR 0x000001ea
313 #define REG_AXXX_CP_STATE_DEBUG_INDEX 0x000001ec
315 #define REG_AXXX_CP_STATE_DEBUG_DATA 0x000001ed
317 #define REG_AXXX_CP_INT_CNTL 0x000001f2
319 #define REG_AXXX_CP_INT_STATUS 0x000001f3
321 #define REG_AXXX_CP_INT_ACK 0x000001f4
323 #define REG_AXXX_CP_ME_CNTL 0x000001f6
324 #define AXXX_CP_ME_CNTL_BUSY 0x20000000
325 #define AXXX_CP_ME_CNTL_HALT 0x10000000
327 #define REG_AXXX_CP_ME_STATUS 0x000001f7
329 #define REG_AXXX_CP_ME_RAM_WADDR 0x000001f8
331 #define REG_AXXX_CP_ME_RAM_RADDR 0x000001f9
333 #define REG_AXXX_CP_ME_RAM_DATA 0x000001fa
335 #define REG_AXXX_CP_DEBUG 0x000001fc
336 #define AXXX_CP_DEBUG_PREDICATE_DISABLE 0x00800000
337 #define AXXX_CP_DEBUG_PROG_END_PTR_ENABLE 0x01000000
338 #define AXXX_CP_DEBUG_MIU_128BIT_WRITE_ENABLE 0x02000000
339 #define AXXX_CP_DEBUG_PREFETCH_PASS_NOPS 0x04000000
340 #define AXXX_CP_DEBUG_DYNAMIC_CLK_DISABLE 0x08000000
341 #define AXXX_CP_DEBUG_PREFETCH_MATCH_DISABLE 0x10000000
342 #define AXXX_CP_DEBUG_SIMPLE_ME_FLOW_CONTROL 0x40000000
343 #define AXXX_CP_DEBUG_MIU_WRITE_PACK_DISABLE 0x80000000
345 #define REG_AXXX_CP_CSQ_RB_STAT 0x000001fd
346 #define AXXX_CP_CSQ_RB_STAT_RPTR__MASK 0x0000007f
347 #define AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT 0
348 static inline uint32_t AXXX_CP_CSQ_RB_STAT_RPTR(uint32_t val
)
350 return ((val
) << AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT
) & AXXX_CP_CSQ_RB_STAT_RPTR__MASK
;
352 #define AXXX_CP_CSQ_RB_STAT_WPTR__MASK 0x007f0000
353 #define AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT 16
354 static inline uint32_t AXXX_CP_CSQ_RB_STAT_WPTR(uint32_t val
)
356 return ((val
) << AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT
) & AXXX_CP_CSQ_RB_STAT_WPTR__MASK
;
359 #define REG_AXXX_CP_CSQ_IB1_STAT 0x000001fe
360 #define AXXX_CP_CSQ_IB1_STAT_RPTR__MASK 0x0000007f
361 #define AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT 0
362 static inline uint32_t AXXX_CP_CSQ_IB1_STAT_RPTR(uint32_t val
)
364 return ((val
) << AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT
) & AXXX_CP_CSQ_IB1_STAT_RPTR__MASK
;
366 #define AXXX_CP_CSQ_IB1_STAT_WPTR__MASK 0x007f0000
367 #define AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT 16
368 static inline uint32_t AXXX_CP_CSQ_IB1_STAT_WPTR(uint32_t val
)
370 return ((val
) << AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT
) & AXXX_CP_CSQ_IB1_STAT_WPTR__MASK
;
373 #define REG_AXXX_CP_CSQ_IB2_STAT 0x000001ff
374 #define AXXX_CP_CSQ_IB2_STAT_RPTR__MASK 0x0000007f
375 #define AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT 0
376 static inline uint32_t AXXX_CP_CSQ_IB2_STAT_RPTR(uint32_t val
)
378 return ((val
) << AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT
) & AXXX_CP_CSQ_IB2_STAT_RPTR__MASK
;
380 #define AXXX_CP_CSQ_IB2_STAT_WPTR__MASK 0x007f0000
381 #define AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT 16
382 static inline uint32_t AXXX_CP_CSQ_IB2_STAT_WPTR(uint32_t val
)
384 return ((val
) << AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT
) & AXXX_CP_CSQ_IB2_STAT_WPTR__MASK
;
387 #define REG_AXXX_CP_NON_PREFETCH_CNTRS 0x00000440
389 #define REG_AXXX_CP_STQ_ST_STAT 0x00000443
391 #define REG_AXXX_CP_ST_BASE 0x0000044d
393 #define REG_AXXX_CP_ST_BUFSZ 0x0000044e
395 #define REG_AXXX_CP_MEQ_STAT 0x0000044f
397 #define REG_AXXX_CP_MIU_TAG_STAT 0x00000452
399 #define REG_AXXX_CP_BIN_MASK_LO 0x00000454
401 #define REG_AXXX_CP_BIN_MASK_HI 0x00000455
403 #define REG_AXXX_CP_BIN_SELECT_LO 0x00000456
405 #define REG_AXXX_CP_BIN_SELECT_HI 0x00000457
407 #define REG_AXXX_CP_IB1_BASE 0x00000458
409 #define REG_AXXX_CP_IB1_BUFSZ 0x00000459
411 #define REG_AXXX_CP_IB2_BASE 0x0000045a
413 #define REG_AXXX_CP_IB2_BUFSZ 0x0000045b
415 #define REG_AXXX_CP_STAT 0x0000047f
417 #define REG_AXXX_CP_SCRATCH_REG0 0x00000578
419 #define REG_AXXX_CP_SCRATCH_REG1 0x00000579
421 #define REG_AXXX_CP_SCRATCH_REG2 0x0000057a
423 #define REG_AXXX_CP_SCRATCH_REG3 0x0000057b
425 #define REG_AXXX_CP_SCRATCH_REG4 0x0000057c
427 #define REG_AXXX_CP_SCRATCH_REG5 0x0000057d
429 #define REG_AXXX_CP_SCRATCH_REG6 0x0000057e
431 #define REG_AXXX_CP_SCRATCH_REG7 0x0000057f
433 #define REG_AXXX_CP_ME_VS_EVENT_SRC 0x00000600
435 #define REG_AXXX_CP_ME_VS_EVENT_ADDR 0x00000601
437 #define REG_AXXX_CP_ME_VS_EVENT_DATA 0x00000602
439 #define REG_AXXX_CP_ME_VS_EVENT_ADDR_SWM 0x00000603
441 #define REG_AXXX_CP_ME_VS_EVENT_DATA_SWM 0x00000604
443 #define REG_AXXX_CP_ME_PS_EVENT_SRC 0x00000605
445 #define REG_AXXX_CP_ME_PS_EVENT_ADDR 0x00000606
447 #define REG_AXXX_CP_ME_PS_EVENT_DATA 0x00000607
449 #define REG_AXXX_CP_ME_PS_EVENT_ADDR_SWM 0x00000608
451 #define REG_AXXX_CP_ME_PS_EVENT_DATA_SWM 0x00000609
453 #define REG_AXXX_CP_ME_CF_EVENT_SRC 0x0000060a
455 #define REG_AXXX_CP_ME_CF_EVENT_ADDR 0x0000060b
457 #define REG_AXXX_CP_ME_CF_EVENT_DATA 0x0000060c
459 #define REG_AXXX_CP_ME_NRT_ADDR 0x0000060d
461 #define REG_AXXX_CP_ME_NRT_DATA 0x0000060e
463 #define REG_AXXX_CP_ME_VS_FETCH_DONE_SRC 0x00000612
465 #define REG_AXXX_CP_ME_VS_FETCH_DONE_ADDR 0x00000613
467 #define REG_AXXX_CP_ME_VS_FETCH_DONE_DATA 0x00000614
470 #endif /* ADRENO_COMMON_XML */