1 #ifndef ADRENO_COMMON_XML
2 #define ADRENO_COMMON_XML
4 /* Autogenerated file, DO NOT EDIT manually!
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
10 The rules-ng-ng source files this header was generated from are:
11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2013-11-30 14:47:15)
12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
13 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2014-05-21 20:40:21)
14 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 9859 bytes, from 2014-05-21 20:39:42)
15 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14477 bytes, from 2014-05-16 11:51:57)
16 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 57954 bytes, from 2014-05-26 12:57:46)
17 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 26602 bytes, from 2014-05-21 20:46:17)
19 Copyright (C) 2013-2014 by the following authors:
20 - Rob Clark <robdclark@gmail.com> (robclark)
22 Permission is hereby granted, free of charge, to any person obtaining
23 a copy of this software and associated documentation files (the
24 "Software"), to deal in the Software without restriction, including
25 without limitation the rights to use, copy, modify, merge, publish,
26 distribute, sublicense, and/or sell copies of the Software, and to
27 permit persons to whom the Software is furnished to do so, subject to
28 the following conditions:
30 The above copyright notice and this permission notice (including the
31 next paragraph) shall be included in all copies or substantial
32 portions of the Software.
34 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
36 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
37 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
38 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
39 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
40 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
44 enum adreno_pa_su_sc_draw
{
47 PC_DRAW_TRIANGLES
= 2,
50 enum adreno_compare_func
{
61 enum adreno_stencil_op
{
65 STENCIL_INCR_CLAMP
= 3,
66 STENCIL_DECR_CLAMP
= 4,
68 STENCIL_INCR_WRAP
= 6,
69 STENCIL_DECR_WRAP
= 7,
72 enum adreno_rb_blend_factor
{
76 FACTOR_ONE_MINUS_SRC_COLOR
= 5,
78 FACTOR_ONE_MINUS_SRC_ALPHA
= 7,
80 FACTOR_ONE_MINUS_DST_COLOR
= 9,
81 FACTOR_DST_ALPHA
= 10,
82 FACTOR_ONE_MINUS_DST_ALPHA
= 11,
83 FACTOR_CONSTANT_COLOR
= 12,
84 FACTOR_ONE_MINUS_CONSTANT_COLOR
= 13,
85 FACTOR_CONSTANT_ALPHA
= 14,
86 FACTOR_ONE_MINUS_CONSTANT_ALPHA
= 15,
87 FACTOR_SRC_ALPHA_SATURATE
= 16,
90 enum adreno_rb_surface_endian
{
99 enum adreno_rb_dither_mode
{
102 DITHER_IF_ALPHA_OFF
= 2,
105 enum adreno_rb_depth_format
{
110 enum adreno_rb_copy_control_mode
{
113 RB_COPY_DEPTH_STENCIL
= 5,
116 enum a3xx_render_mode
{
117 RB_RENDERING_PASS
= 0,
123 enum a3xx_msaa_samples
{
129 enum a3xx_threadmode
{
134 enum a3xx_instrbuffermode
{
138 enum a3xx_threadsize
{
143 #define REG_AXXX_CP_RB_BASE 0x000001c0
145 #define REG_AXXX_CP_RB_CNTL 0x000001c1
146 #define AXXX_CP_RB_CNTL_BUFSZ__MASK 0x0000003f
147 #define AXXX_CP_RB_CNTL_BUFSZ__SHIFT 0
148 static inline uint32_t AXXX_CP_RB_CNTL_BUFSZ(uint32_t val
)
150 return ((val
) << AXXX_CP_RB_CNTL_BUFSZ__SHIFT
) & AXXX_CP_RB_CNTL_BUFSZ__MASK
;
152 #define AXXX_CP_RB_CNTL_BLKSZ__MASK 0x00003f00
153 #define AXXX_CP_RB_CNTL_BLKSZ__SHIFT 8
154 static inline uint32_t AXXX_CP_RB_CNTL_BLKSZ(uint32_t val
)
156 return ((val
) << AXXX_CP_RB_CNTL_BLKSZ__SHIFT
) & AXXX_CP_RB_CNTL_BLKSZ__MASK
;
158 #define AXXX_CP_RB_CNTL_BUF_SWAP__MASK 0x00030000
159 #define AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT 16
160 static inline uint32_t AXXX_CP_RB_CNTL_BUF_SWAP(uint32_t val
)
162 return ((val
) << AXXX_CP_RB_CNTL_BUF_SWAP__SHIFT
) & AXXX_CP_RB_CNTL_BUF_SWAP__MASK
;
164 #define AXXX_CP_RB_CNTL_POLL_EN 0x00100000
165 #define AXXX_CP_RB_CNTL_NO_UPDATE 0x08000000
166 #define AXXX_CP_RB_CNTL_RPTR_WR_EN 0x80000000
168 #define REG_AXXX_CP_RB_RPTR_ADDR 0x000001c3
169 #define AXXX_CP_RB_RPTR_ADDR_SWAP__MASK 0x00000003
170 #define AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT 0
171 static inline uint32_t AXXX_CP_RB_RPTR_ADDR_SWAP(uint32_t val
)
173 return ((val
) << AXXX_CP_RB_RPTR_ADDR_SWAP__SHIFT
) & AXXX_CP_RB_RPTR_ADDR_SWAP__MASK
;
175 #define AXXX_CP_RB_RPTR_ADDR_ADDR__MASK 0xfffffffc
176 #define AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT 2
177 static inline uint32_t AXXX_CP_RB_RPTR_ADDR_ADDR(uint32_t val
)
179 return ((val
>> 2) << AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT
) & AXXX_CP_RB_RPTR_ADDR_ADDR__MASK
;
182 #define REG_AXXX_CP_RB_RPTR 0x000001c4
184 #define REG_AXXX_CP_RB_WPTR 0x000001c5
186 #define REG_AXXX_CP_RB_WPTR_DELAY 0x000001c6
188 #define REG_AXXX_CP_RB_RPTR_WR 0x000001c7
190 #define REG_AXXX_CP_RB_WPTR_BASE 0x000001c8
192 #define REG_AXXX_CP_QUEUE_THRESHOLDS 0x000001d5
193 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK 0x0000000f
194 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT 0
195 static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(uint32_t val
)
197 return ((val
) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__SHIFT
) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START__MASK
;
199 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK 0x00000f00
200 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT 8
201 static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(uint32_t val
)
203 return ((val
) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__SHIFT
) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START__MASK
;
205 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK 0x000f0000
206 #define AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT 16
207 static inline uint32_t AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START(uint32_t val
)
209 return ((val
) << AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__SHIFT
) & AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START__MASK
;
212 #define REG_AXXX_CP_MEQ_THRESHOLDS 0x000001d6
213 #define AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK 0x001f0000
214 #define AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT 16
215 static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_MEQ_END(uint32_t val
)
217 return ((val
) << AXXX_CP_MEQ_THRESHOLDS_MEQ_END__SHIFT
) & AXXX_CP_MEQ_THRESHOLDS_MEQ_END__MASK
;
219 #define AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK 0x1f000000
220 #define AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT 24
221 static inline uint32_t AXXX_CP_MEQ_THRESHOLDS_ROQ_END(uint32_t val
)
223 return ((val
) << AXXX_CP_MEQ_THRESHOLDS_ROQ_END__SHIFT
) & AXXX_CP_MEQ_THRESHOLDS_ROQ_END__MASK
;
226 #define REG_AXXX_CP_CSQ_AVAIL 0x000001d7
227 #define AXXX_CP_CSQ_AVAIL_RING__MASK 0x0000007f
228 #define AXXX_CP_CSQ_AVAIL_RING__SHIFT 0
229 static inline uint32_t AXXX_CP_CSQ_AVAIL_RING(uint32_t val
)
231 return ((val
) << AXXX_CP_CSQ_AVAIL_RING__SHIFT
) & AXXX_CP_CSQ_AVAIL_RING__MASK
;
233 #define AXXX_CP_CSQ_AVAIL_IB1__MASK 0x00007f00
234 #define AXXX_CP_CSQ_AVAIL_IB1__SHIFT 8
235 static inline uint32_t AXXX_CP_CSQ_AVAIL_IB1(uint32_t val
)
237 return ((val
) << AXXX_CP_CSQ_AVAIL_IB1__SHIFT
) & AXXX_CP_CSQ_AVAIL_IB1__MASK
;
239 #define AXXX_CP_CSQ_AVAIL_IB2__MASK 0x007f0000
240 #define AXXX_CP_CSQ_AVAIL_IB2__SHIFT 16
241 static inline uint32_t AXXX_CP_CSQ_AVAIL_IB2(uint32_t val
)
243 return ((val
) << AXXX_CP_CSQ_AVAIL_IB2__SHIFT
) & AXXX_CP_CSQ_AVAIL_IB2__MASK
;
246 #define REG_AXXX_CP_STQ_AVAIL 0x000001d8
247 #define AXXX_CP_STQ_AVAIL_ST__MASK 0x0000007f
248 #define AXXX_CP_STQ_AVAIL_ST__SHIFT 0
249 static inline uint32_t AXXX_CP_STQ_AVAIL_ST(uint32_t val
)
251 return ((val
) << AXXX_CP_STQ_AVAIL_ST__SHIFT
) & AXXX_CP_STQ_AVAIL_ST__MASK
;
254 #define REG_AXXX_CP_MEQ_AVAIL 0x000001d9
255 #define AXXX_CP_MEQ_AVAIL_MEQ__MASK 0x0000001f
256 #define AXXX_CP_MEQ_AVAIL_MEQ__SHIFT 0
257 static inline uint32_t AXXX_CP_MEQ_AVAIL_MEQ(uint32_t val
)
259 return ((val
) << AXXX_CP_MEQ_AVAIL_MEQ__SHIFT
) & AXXX_CP_MEQ_AVAIL_MEQ__MASK
;
262 #define REG_AXXX_SCRATCH_UMSK 0x000001dc
263 #define AXXX_SCRATCH_UMSK_UMSK__MASK 0x000000ff
264 #define AXXX_SCRATCH_UMSK_UMSK__SHIFT 0
265 static inline uint32_t AXXX_SCRATCH_UMSK_UMSK(uint32_t val
)
267 return ((val
) << AXXX_SCRATCH_UMSK_UMSK__SHIFT
) & AXXX_SCRATCH_UMSK_UMSK__MASK
;
269 #define AXXX_SCRATCH_UMSK_SWAP__MASK 0x00030000
270 #define AXXX_SCRATCH_UMSK_SWAP__SHIFT 16
271 static inline uint32_t AXXX_SCRATCH_UMSK_SWAP(uint32_t val
)
273 return ((val
) << AXXX_SCRATCH_UMSK_SWAP__SHIFT
) & AXXX_SCRATCH_UMSK_SWAP__MASK
;
276 #define REG_AXXX_SCRATCH_ADDR 0x000001dd
278 #define REG_AXXX_CP_ME_RDADDR 0x000001ea
280 #define REG_AXXX_CP_STATE_DEBUG_INDEX 0x000001ec
282 #define REG_AXXX_CP_STATE_DEBUG_DATA 0x000001ed
284 #define REG_AXXX_CP_INT_CNTL 0x000001f2
286 #define REG_AXXX_CP_INT_STATUS 0x000001f3
288 #define REG_AXXX_CP_INT_ACK 0x000001f4
290 #define REG_AXXX_CP_ME_CNTL 0x000001f6
291 #define AXXX_CP_ME_CNTL_BUSY 0x20000000
292 #define AXXX_CP_ME_CNTL_HALT 0x10000000
294 #define REG_AXXX_CP_ME_STATUS 0x000001f7
296 #define REG_AXXX_CP_ME_RAM_WADDR 0x000001f8
298 #define REG_AXXX_CP_ME_RAM_RADDR 0x000001f9
300 #define REG_AXXX_CP_ME_RAM_DATA 0x000001fa
302 #define REG_AXXX_CP_DEBUG 0x000001fc
303 #define AXXX_CP_DEBUG_PREDICATE_DISABLE 0x00800000
304 #define AXXX_CP_DEBUG_PROG_END_PTR_ENABLE 0x01000000
305 #define AXXX_CP_DEBUG_MIU_128BIT_WRITE_ENABLE 0x02000000
306 #define AXXX_CP_DEBUG_PREFETCH_PASS_NOPS 0x04000000
307 #define AXXX_CP_DEBUG_DYNAMIC_CLK_DISABLE 0x08000000
308 #define AXXX_CP_DEBUG_PREFETCH_MATCH_DISABLE 0x10000000
309 #define AXXX_CP_DEBUG_SIMPLE_ME_FLOW_CONTROL 0x40000000
310 #define AXXX_CP_DEBUG_MIU_WRITE_PACK_DISABLE 0x80000000
312 #define REG_AXXX_CP_CSQ_RB_STAT 0x000001fd
313 #define AXXX_CP_CSQ_RB_STAT_RPTR__MASK 0x0000007f
314 #define AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT 0
315 static inline uint32_t AXXX_CP_CSQ_RB_STAT_RPTR(uint32_t val
)
317 return ((val
) << AXXX_CP_CSQ_RB_STAT_RPTR__SHIFT
) & AXXX_CP_CSQ_RB_STAT_RPTR__MASK
;
319 #define AXXX_CP_CSQ_RB_STAT_WPTR__MASK 0x007f0000
320 #define AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT 16
321 static inline uint32_t AXXX_CP_CSQ_RB_STAT_WPTR(uint32_t val
)
323 return ((val
) << AXXX_CP_CSQ_RB_STAT_WPTR__SHIFT
) & AXXX_CP_CSQ_RB_STAT_WPTR__MASK
;
326 #define REG_AXXX_CP_CSQ_IB1_STAT 0x000001fe
327 #define AXXX_CP_CSQ_IB1_STAT_RPTR__MASK 0x0000007f
328 #define AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT 0
329 static inline uint32_t AXXX_CP_CSQ_IB1_STAT_RPTR(uint32_t val
)
331 return ((val
) << AXXX_CP_CSQ_IB1_STAT_RPTR__SHIFT
) & AXXX_CP_CSQ_IB1_STAT_RPTR__MASK
;
333 #define AXXX_CP_CSQ_IB1_STAT_WPTR__MASK 0x007f0000
334 #define AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT 16
335 static inline uint32_t AXXX_CP_CSQ_IB1_STAT_WPTR(uint32_t val
)
337 return ((val
) << AXXX_CP_CSQ_IB1_STAT_WPTR__SHIFT
) & AXXX_CP_CSQ_IB1_STAT_WPTR__MASK
;
340 #define REG_AXXX_CP_CSQ_IB2_STAT 0x000001ff
341 #define AXXX_CP_CSQ_IB2_STAT_RPTR__MASK 0x0000007f
342 #define AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT 0
343 static inline uint32_t AXXX_CP_CSQ_IB2_STAT_RPTR(uint32_t val
)
345 return ((val
) << AXXX_CP_CSQ_IB2_STAT_RPTR__SHIFT
) & AXXX_CP_CSQ_IB2_STAT_RPTR__MASK
;
347 #define AXXX_CP_CSQ_IB2_STAT_WPTR__MASK 0x007f0000
348 #define AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT 16
349 static inline uint32_t AXXX_CP_CSQ_IB2_STAT_WPTR(uint32_t val
)
351 return ((val
) << AXXX_CP_CSQ_IB2_STAT_WPTR__SHIFT
) & AXXX_CP_CSQ_IB2_STAT_WPTR__MASK
;
354 #define REG_AXXX_CP_NON_PREFETCH_CNTRS 0x00000440
356 #define REG_AXXX_CP_STQ_ST_STAT 0x00000443
358 #define REG_AXXX_CP_ST_BASE 0x0000044d
360 #define REG_AXXX_CP_ST_BUFSZ 0x0000044e
362 #define REG_AXXX_CP_MEQ_STAT 0x0000044f
364 #define REG_AXXX_CP_MIU_TAG_STAT 0x00000452
366 #define REG_AXXX_CP_BIN_MASK_LO 0x00000454
368 #define REG_AXXX_CP_BIN_MASK_HI 0x00000455
370 #define REG_AXXX_CP_BIN_SELECT_LO 0x00000456
372 #define REG_AXXX_CP_BIN_SELECT_HI 0x00000457
374 #define REG_AXXX_CP_IB1_BASE 0x00000458
376 #define REG_AXXX_CP_IB1_BUFSZ 0x00000459
378 #define REG_AXXX_CP_IB2_BASE 0x0000045a
380 #define REG_AXXX_CP_IB2_BUFSZ 0x0000045b
382 #define REG_AXXX_CP_STAT 0x0000047f
384 #define REG_AXXX_CP_SCRATCH_REG0 0x00000578
386 #define REG_AXXX_CP_SCRATCH_REG1 0x00000579
388 #define REG_AXXX_CP_SCRATCH_REG2 0x0000057a
390 #define REG_AXXX_CP_SCRATCH_REG3 0x0000057b
392 #define REG_AXXX_CP_SCRATCH_REG4 0x0000057c
394 #define REG_AXXX_CP_SCRATCH_REG5 0x0000057d
396 #define REG_AXXX_CP_SCRATCH_REG6 0x0000057e
398 #define REG_AXXX_CP_SCRATCH_REG7 0x0000057f
400 #define REG_AXXX_CP_ME_VS_EVENT_SRC 0x00000600
402 #define REG_AXXX_CP_ME_VS_EVENT_ADDR 0x00000601
404 #define REG_AXXX_CP_ME_VS_EVENT_DATA 0x00000602
406 #define REG_AXXX_CP_ME_VS_EVENT_ADDR_SWM 0x00000603
408 #define REG_AXXX_CP_ME_VS_EVENT_DATA_SWM 0x00000604
410 #define REG_AXXX_CP_ME_PS_EVENT_SRC 0x00000605
412 #define REG_AXXX_CP_ME_PS_EVENT_ADDR 0x00000606
414 #define REG_AXXX_CP_ME_PS_EVENT_DATA 0x00000607
416 #define REG_AXXX_CP_ME_PS_EVENT_ADDR_SWM 0x00000608
418 #define REG_AXXX_CP_ME_PS_EVENT_DATA_SWM 0x00000609
420 #define REG_AXXX_CP_ME_CF_EVENT_SRC 0x0000060a
422 #define REG_AXXX_CP_ME_CF_EVENT_ADDR 0x0000060b
424 #define REG_AXXX_CP_ME_CF_EVENT_DATA 0x0000060c
426 #define REG_AXXX_CP_ME_NRT_ADDR 0x0000060d
428 #define REG_AXXX_CP_ME_NRT_DATA 0x0000060e
430 #define REG_AXXX_CP_ME_VS_FETCH_DONE_SRC 0x00000612
432 #define REG_AXXX_CP_ME_VS_FETCH_DONE_ADDR 0x00000613
434 #define REG_AXXX_CP_ME_VS_FETCH_DONE_DATA 0x00000614
437 #endif /* ADRENO_COMMON_XML */