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freedreno/a3xx/compiler: refactor trans_samp()
[mesa.git] / src / gallium / drivers / freedreno / adreno_pm4.xml.h
1 #ifndef ADRENO_PM4_XML
2 #define ADRENO_PM4_XML
3
4 /* Autogenerated file, DO NOT EDIT manually!
5
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
9
10 The rules-ng-ng source files this header was generated from are:
11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2013-11-30 14:47:15)
12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
13 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32580 bytes, from 2014-05-16 11:51:57)
14 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10186 bytes, from 2014-05-16 11:51:57)
15 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14477 bytes, from 2014-05-16 11:51:57)
16 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 57831 bytes, from 2014-05-19 21:02:34)
17 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 26293 bytes, from 2014-05-16 11:51:57)
18
19 Copyright (C) 2013-2014 by the following authors:
20 - Rob Clark <robdclark@gmail.com> (robclark)
21
22 Permission is hereby granted, free of charge, to any person obtaining
23 a copy of this software and associated documentation files (the
24 "Software"), to deal in the Software without restriction, including
25 without limitation the rights to use, copy, modify, merge, publish,
26 distribute, sublicense, and/or sell copies of the Software, and to
27 permit persons to whom the Software is furnished to do so, subject to
28 the following conditions:
29
30 The above copyright notice and this permission notice (including the
31 next paragraph) shall be included in all copies or substantial
32 portions of the Software.
33
34 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
36 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
37 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
38 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
39 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
40 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43
44 enum vgt_event_type {
45 VS_DEALLOC = 0,
46 PS_DEALLOC = 1,
47 VS_DONE_TS = 2,
48 PS_DONE_TS = 3,
49 CACHE_FLUSH_TS = 4,
50 CONTEXT_DONE = 5,
51 CACHE_FLUSH = 6,
52 HLSQ_FLUSH = 7,
53 VIZQUERY_START = 7,
54 VIZQUERY_END = 8,
55 SC_WAIT_WC = 9,
56 RST_PIX_CNT = 13,
57 RST_VTX_CNT = 14,
58 TILE_FLUSH = 15,
59 CACHE_FLUSH_AND_INV_TS_EVENT = 20,
60 ZPASS_DONE = 21,
61 CACHE_FLUSH_AND_INV_EVENT = 22,
62 PERFCOUNTER_START = 23,
63 PERFCOUNTER_STOP = 24,
64 VS_FETCH_DONE = 27,
65 FACENESS_FLUSH = 28,
66 };
67
68 enum pc_di_primtype {
69 DI_PT_NONE = 0,
70 DI_PT_POINTLIST_A2XX = 1,
71 DI_PT_LINELIST = 2,
72 DI_PT_LINESTRIP = 3,
73 DI_PT_TRILIST = 4,
74 DI_PT_TRIFAN = 5,
75 DI_PT_TRISTRIP = 6,
76 DI_PT_LINELOOP = 7,
77 DI_PT_RECTLIST = 8,
78 DI_PT_POINTLIST_A3XX = 9,
79 DI_PT_QUADLIST = 13,
80 DI_PT_QUADSTRIP = 14,
81 DI_PT_POLYGON = 15,
82 DI_PT_2D_COPY_RECT_LIST_V0 = 16,
83 DI_PT_2D_COPY_RECT_LIST_V1 = 17,
84 DI_PT_2D_COPY_RECT_LIST_V2 = 18,
85 DI_PT_2D_COPY_RECT_LIST_V3 = 19,
86 DI_PT_2D_FILL_RECT_LIST = 20,
87 DI_PT_2D_LINE_STRIP = 21,
88 DI_PT_2D_TRI_STRIP = 22,
89 };
90
91 enum pc_di_src_sel {
92 DI_SRC_SEL_DMA = 0,
93 DI_SRC_SEL_IMMEDIATE = 1,
94 DI_SRC_SEL_AUTO_INDEX = 2,
95 DI_SRC_SEL_RESERVED = 3,
96 };
97
98 enum pc_di_index_size {
99 INDEX_SIZE_IGN = 0,
100 INDEX_SIZE_16_BIT = 0,
101 INDEX_SIZE_32_BIT = 1,
102 INDEX_SIZE_8_BIT = 2,
103 INDEX_SIZE_INVALID = 0,
104 };
105
106 enum pc_di_vis_cull_mode {
107 IGNORE_VISIBILITY = 0,
108 USE_VISIBILITY = 1,
109 };
110
111 enum adreno_pm4_packet_type {
112 CP_TYPE0_PKT = 0,
113 CP_TYPE1_PKT = 0x40000000,
114 CP_TYPE2_PKT = 0x80000000,
115 CP_TYPE3_PKT = 0xc0000000,
116 };
117
118 enum adreno_pm4_type3_packets {
119 CP_ME_INIT = 72,
120 CP_NOP = 16,
121 CP_INDIRECT_BUFFER = 63,
122 CP_INDIRECT_BUFFER_PFD = 55,
123 CP_WAIT_FOR_IDLE = 38,
124 CP_WAIT_REG_MEM = 60,
125 CP_WAIT_REG_EQ = 82,
126 CP_WAIT_REG_GTE = 83,
127 CP_WAIT_UNTIL_READ = 92,
128 CP_WAIT_IB_PFD_COMPLETE = 93,
129 CP_REG_RMW = 33,
130 CP_SET_BIN_DATA = 47,
131 CP_REG_TO_MEM = 62,
132 CP_MEM_WRITE = 61,
133 CP_MEM_WRITE_CNTR = 79,
134 CP_COND_EXEC = 68,
135 CP_COND_WRITE = 69,
136 CP_EVENT_WRITE = 70,
137 CP_EVENT_WRITE_SHD = 88,
138 CP_EVENT_WRITE_CFL = 89,
139 CP_EVENT_WRITE_ZPD = 91,
140 CP_RUN_OPENCL = 49,
141 CP_DRAW_INDX = 34,
142 CP_DRAW_INDX_2 = 54,
143 CP_DRAW_INDX_BIN = 52,
144 CP_DRAW_INDX_2_BIN = 53,
145 CP_VIZ_QUERY = 35,
146 CP_SET_STATE = 37,
147 CP_SET_CONSTANT = 45,
148 CP_IM_LOAD = 39,
149 CP_IM_LOAD_IMMEDIATE = 43,
150 CP_LOAD_CONSTANT_CONTEXT = 46,
151 CP_INVALIDATE_STATE = 59,
152 CP_SET_SHADER_BASES = 74,
153 CP_SET_BIN_MASK = 80,
154 CP_SET_BIN_SELECT = 81,
155 CP_CONTEXT_UPDATE = 94,
156 CP_INTERRUPT = 64,
157 CP_IM_STORE = 44,
158 CP_SET_DRAW_INIT_FLAGS = 75,
159 CP_SET_PROTECTED_MODE = 95,
160 CP_LOAD_STATE = 48,
161 CP_COND_INDIRECT_BUFFER_PFE = 58,
162 CP_COND_INDIRECT_BUFFER_PFD = 50,
163 CP_INDIRECT_BUFFER_PFE = 63,
164 CP_SET_BIN = 76,
165 CP_TEST_TWO_MEMS = 113,
166 CP_WAIT_FOR_ME = 19,
167 CP_SET_DRAW_STATE = 67,
168 CP_DRAW_INDX_OFFSET = 56,
169 CP_DRAW_INDIRECT = 40,
170 CP_DRAW_INDX_INDIRECT = 41,
171 CP_DRAW_AUTO = 36,
172 IN_IB_PREFETCH_END = 23,
173 IN_SUBBLK_PREFETCH = 31,
174 IN_INSTR_PREFETCH = 32,
175 IN_INSTR_MATCH = 71,
176 IN_CONST_PREFETCH = 73,
177 IN_INCR_UPDT_STATE = 85,
178 IN_INCR_UPDT_CONST = 86,
179 IN_INCR_UPDT_INSTR = 87,
180 };
181
182 enum adreno_state_block {
183 SB_VERT_TEX = 0,
184 SB_VERT_MIPADDR = 1,
185 SB_FRAG_TEX = 2,
186 SB_FRAG_MIPADDR = 3,
187 SB_VERT_SHADER = 4,
188 SB_FRAG_SHADER = 6,
189 };
190
191 enum adreno_state_type {
192 ST_SHADER = 0,
193 ST_CONSTANTS = 1,
194 };
195
196 enum adreno_state_src {
197 SS_DIRECT = 0,
198 SS_INDIRECT = 4,
199 };
200
201 #define REG_CP_LOAD_STATE_0 0x00000000
202 #define CP_LOAD_STATE_0_DST_OFF__MASK 0x0000ffff
203 #define CP_LOAD_STATE_0_DST_OFF__SHIFT 0
204 static inline uint32_t CP_LOAD_STATE_0_DST_OFF(uint32_t val)
205 {
206 return ((val) << CP_LOAD_STATE_0_DST_OFF__SHIFT) & CP_LOAD_STATE_0_DST_OFF__MASK;
207 }
208 #define CP_LOAD_STATE_0_STATE_SRC__MASK 0x00070000
209 #define CP_LOAD_STATE_0_STATE_SRC__SHIFT 16
210 static inline uint32_t CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val)
211 {
212 return ((val) << CP_LOAD_STATE_0_STATE_SRC__SHIFT) & CP_LOAD_STATE_0_STATE_SRC__MASK;
213 }
214 #define CP_LOAD_STATE_0_STATE_BLOCK__MASK 0x00380000
215 #define CP_LOAD_STATE_0_STATE_BLOCK__SHIFT 19
216 static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val)
217 {
218 return ((val) << CP_LOAD_STATE_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE_0_STATE_BLOCK__MASK;
219 }
220 #define CP_LOAD_STATE_0_NUM_UNIT__MASK 0x7fc00000
221 #define CP_LOAD_STATE_0_NUM_UNIT__SHIFT 22
222 static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val)
223 {
224 return ((val) << CP_LOAD_STATE_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE_0_NUM_UNIT__MASK;
225 }
226
227 #define REG_CP_LOAD_STATE_1 0x00000001
228 #define CP_LOAD_STATE_1_STATE_TYPE__MASK 0x00000003
229 #define CP_LOAD_STATE_1_STATE_TYPE__SHIFT 0
230 static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val)
231 {
232 return ((val) << CP_LOAD_STATE_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE_1_STATE_TYPE__MASK;
233 }
234 #define CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK 0xfffffffc
235 #define CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT 2
236 static inline uint32_t CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val)
237 {
238 return ((val >> 2) << CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK;
239 }
240
241 #define REG_CP_DRAW_INDX_0 0x00000000
242 #define CP_DRAW_INDX_0_VIZ_QUERY__MASK 0xffffffff
243 #define CP_DRAW_INDX_0_VIZ_QUERY__SHIFT 0
244 static inline uint32_t CP_DRAW_INDX_0_VIZ_QUERY(uint32_t val)
245 {
246 return ((val) << CP_DRAW_INDX_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_0_VIZ_QUERY__MASK;
247 }
248
249 #define REG_CP_DRAW_INDX_1 0x00000001
250 #define CP_DRAW_INDX_1_PRIM_TYPE__MASK 0x0000003f
251 #define CP_DRAW_INDX_1_PRIM_TYPE__SHIFT 0
252 static inline uint32_t CP_DRAW_INDX_1_PRIM_TYPE(enum pc_di_primtype val)
253 {
254 return ((val) << CP_DRAW_INDX_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_1_PRIM_TYPE__MASK;
255 }
256 #define CP_DRAW_INDX_1_SOURCE_SELECT__MASK 0x000000c0
257 #define CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT 6
258 static inline uint32_t CP_DRAW_INDX_1_SOURCE_SELECT(enum pc_di_src_sel val)
259 {
260 return ((val) << CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_1_SOURCE_SELECT__MASK;
261 }
262 #define CP_DRAW_INDX_1_VIS_CULL__MASK 0x00000600
263 #define CP_DRAW_INDX_1_VIS_CULL__SHIFT 9
264 static inline uint32_t CP_DRAW_INDX_1_VIS_CULL(enum pc_di_vis_cull_mode val)
265 {
266 return ((val) << CP_DRAW_INDX_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_1_VIS_CULL__MASK;
267 }
268 #define CP_DRAW_INDX_1_INDEX_SIZE__MASK 0x00000800
269 #define CP_DRAW_INDX_1_INDEX_SIZE__SHIFT 11
270 static inline uint32_t CP_DRAW_INDX_1_INDEX_SIZE(enum pc_di_index_size val)
271 {
272 return ((val) << CP_DRAW_INDX_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_1_INDEX_SIZE__MASK;
273 }
274 #define CP_DRAW_INDX_1_NOT_EOP 0x00001000
275 #define CP_DRAW_INDX_1_SMALL_INDEX 0x00002000
276 #define CP_DRAW_INDX_1_PRE_DRAW_INITIATOR_ENABLE 0x00004000
277 #define CP_DRAW_INDX_1_NUM_INDICES__MASK 0xffff0000
278 #define CP_DRAW_INDX_1_NUM_INDICES__SHIFT 16
279 static inline uint32_t CP_DRAW_INDX_1_NUM_INDICES(uint32_t val)
280 {
281 return ((val) << CP_DRAW_INDX_1_NUM_INDICES__SHIFT) & CP_DRAW_INDX_1_NUM_INDICES__MASK;
282 }
283
284 #define REG_CP_DRAW_INDX_2 0x00000002
285 #define CP_DRAW_INDX_2_NUM_INDICES__MASK 0xffffffff
286 #define CP_DRAW_INDX_2_NUM_INDICES__SHIFT 0
287 static inline uint32_t CP_DRAW_INDX_2_NUM_INDICES(uint32_t val)
288 {
289 return ((val) << CP_DRAW_INDX_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_NUM_INDICES__MASK;
290 }
291
292 #define REG_CP_DRAW_INDX_2 0x00000002
293 #define CP_DRAW_INDX_2_INDX_BASE__MASK 0xffffffff
294 #define CP_DRAW_INDX_2_INDX_BASE__SHIFT 0
295 static inline uint32_t CP_DRAW_INDX_2_INDX_BASE(uint32_t val)
296 {
297 return ((val) << CP_DRAW_INDX_2_INDX_BASE__SHIFT) & CP_DRAW_INDX_2_INDX_BASE__MASK;
298 }
299
300 #define REG_CP_DRAW_INDX_2 0x00000002
301 #define CP_DRAW_INDX_2_INDX_SIZE__MASK 0xffffffff
302 #define CP_DRAW_INDX_2_INDX_SIZE__SHIFT 0
303 static inline uint32_t CP_DRAW_INDX_2_INDX_SIZE(uint32_t val)
304 {
305 return ((val) << CP_DRAW_INDX_2_INDX_SIZE__SHIFT) & CP_DRAW_INDX_2_INDX_SIZE__MASK;
306 }
307
308 #define REG_CP_DRAW_INDX_2_0 0x00000000
309 #define CP_DRAW_INDX_2_0_VIZ_QUERY__MASK 0xffffffff
310 #define CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT 0
311 static inline uint32_t CP_DRAW_INDX_2_0_VIZ_QUERY(uint32_t val)
312 {
313 return ((val) << CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_2_0_VIZ_QUERY__MASK;
314 }
315
316 #define REG_CP_DRAW_INDX_2_1 0x00000001
317 #define CP_DRAW_INDX_2_1_PRIM_TYPE__MASK 0x0000003f
318 #define CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT 0
319 static inline uint32_t CP_DRAW_INDX_2_1_PRIM_TYPE(enum pc_di_primtype val)
320 {
321 return ((val) << CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_2_1_PRIM_TYPE__MASK;
322 }
323 #define CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK 0x000000c0
324 #define CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT 6
325 static inline uint32_t CP_DRAW_INDX_2_1_SOURCE_SELECT(enum pc_di_src_sel val)
326 {
327 return ((val) << CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK;
328 }
329 #define CP_DRAW_INDX_2_1_VIS_CULL__MASK 0x00000600
330 #define CP_DRAW_INDX_2_1_VIS_CULL__SHIFT 9
331 static inline uint32_t CP_DRAW_INDX_2_1_VIS_CULL(enum pc_di_vis_cull_mode val)
332 {
333 return ((val) << CP_DRAW_INDX_2_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_2_1_VIS_CULL__MASK;
334 }
335 #define CP_DRAW_INDX_2_1_INDEX_SIZE__MASK 0x00000800
336 #define CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT 11
337 static inline uint32_t CP_DRAW_INDX_2_1_INDEX_SIZE(enum pc_di_index_size val)
338 {
339 return ((val) << CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_2_1_INDEX_SIZE__MASK;
340 }
341 #define CP_DRAW_INDX_2_1_NOT_EOP 0x00001000
342 #define CP_DRAW_INDX_2_1_SMALL_INDEX 0x00002000
343 #define CP_DRAW_INDX_2_1_PRE_DRAW_INITIATOR_ENABLE 0x00004000
344 #define CP_DRAW_INDX_2_1_NUM_INDICES__MASK 0xffff0000
345 #define CP_DRAW_INDX_2_1_NUM_INDICES__SHIFT 16
346 static inline uint32_t CP_DRAW_INDX_2_1_NUM_INDICES(uint32_t val)
347 {
348 return ((val) << CP_DRAW_INDX_2_1_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_1_NUM_INDICES__MASK;
349 }
350
351 #define REG_CP_DRAW_INDX_2_2 0x00000002
352 #define CP_DRAW_INDX_2_2_NUM_INDICES__MASK 0xffffffff
353 #define CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT 0
354 static inline uint32_t CP_DRAW_INDX_2_2_NUM_INDICES(uint32_t val)
355 {
356 return ((val) << CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_2_NUM_INDICES__MASK;
357 }
358
359 #define REG_CP_DRAW_INDX_OFFSET_0 0x00000000
360 #define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK 0x0000003f
361 #define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT 0
362 static inline uint32_t CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(enum pc_di_primtype val)
363 {
364 return ((val) << CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK;
365 }
366 #define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK 0x000000c0
367 #define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT 6
368 static inline uint32_t CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel val)
369 {
370 return ((val) << CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK;
371 }
372 #define CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK 0x00000700
373 #define CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT 8
374 static inline uint32_t CP_DRAW_INDX_OFFSET_0_VIS_CULL(enum pc_di_vis_cull_mode val)
375 {
376 return ((val) << CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT) & CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK;
377 }
378 #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK 0x00000800
379 #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT 11
380 static inline uint32_t CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum pc_di_index_size val)
381 {
382 return ((val) << CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK;
383 }
384 #define CP_DRAW_INDX_OFFSET_0_NOT_EOP 0x00001000
385 #define CP_DRAW_INDX_OFFSET_0_SMALL_INDEX 0x00002000
386 #define CP_DRAW_INDX_OFFSET_0_PRE_DRAW_INITIATOR_ENABLE 0x00004000
387 #define CP_DRAW_INDX_OFFSET_0_NUM_INDICES__MASK 0xffff0000
388 #define CP_DRAW_INDX_OFFSET_0_NUM_INDICES__SHIFT 16
389 static inline uint32_t CP_DRAW_INDX_OFFSET_0_NUM_INDICES(uint32_t val)
390 {
391 return ((val) << CP_DRAW_INDX_OFFSET_0_NUM_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_0_NUM_INDICES__MASK;
392 }
393
394 #define REG_CP_DRAW_INDX_OFFSET_1 0x00000001
395
396 #define REG_CP_DRAW_INDX_OFFSET_2 0x00000002
397 #define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK 0xffffffff
398 #define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT 0
399 static inline uint32_t CP_DRAW_INDX_OFFSET_2_NUM_INDICES(uint32_t val)
400 {
401 return ((val) << CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK;
402 }
403
404 #define REG_CP_DRAW_INDX_OFFSET_2 0x00000002
405 #define CP_DRAW_INDX_OFFSET_2_INDX_BASE__MASK 0xffffffff
406 #define CP_DRAW_INDX_OFFSET_2_INDX_BASE__SHIFT 0
407 static inline uint32_t CP_DRAW_INDX_OFFSET_2_INDX_BASE(uint32_t val)
408 {
409 return ((val) << CP_DRAW_INDX_OFFSET_2_INDX_BASE__SHIFT) & CP_DRAW_INDX_OFFSET_2_INDX_BASE__MASK;
410 }
411
412 #define REG_CP_DRAW_INDX_OFFSET_2 0x00000002
413 #define CP_DRAW_INDX_OFFSET_2_INDX_SIZE__MASK 0xffffffff
414 #define CP_DRAW_INDX_OFFSET_2_INDX_SIZE__SHIFT 0
415 static inline uint32_t CP_DRAW_INDX_OFFSET_2_INDX_SIZE(uint32_t val)
416 {
417 return ((val) << CP_DRAW_INDX_OFFSET_2_INDX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_2_INDX_SIZE__MASK;
418 }
419
420 #define REG_CP_SET_DRAW_STATE_0 0x00000000
421 #define CP_SET_DRAW_STATE_0_COUNT__MASK 0x0000ffff
422 #define CP_SET_DRAW_STATE_0_COUNT__SHIFT 0
423 static inline uint32_t CP_SET_DRAW_STATE_0_COUNT(uint32_t val)
424 {
425 return ((val) << CP_SET_DRAW_STATE_0_COUNT__SHIFT) & CP_SET_DRAW_STATE_0_COUNT__MASK;
426 }
427 #define CP_SET_DRAW_STATE_0_DIRTY 0x00010000
428 #define CP_SET_DRAW_STATE_0_DISABLE 0x00020000
429 #define CP_SET_DRAW_STATE_0_DISABLE_ALL_GROUPS 0x00040000
430 #define CP_SET_DRAW_STATE_0_LOAD_IMMED 0x00080000
431 #define CP_SET_DRAW_STATE_0_GROUP_ID__MASK 0x1f000000
432 #define CP_SET_DRAW_STATE_0_GROUP_ID__SHIFT 24
433 static inline uint32_t CP_SET_DRAW_STATE_0_GROUP_ID(uint32_t val)
434 {
435 return ((val) << CP_SET_DRAW_STATE_0_GROUP_ID__SHIFT) & CP_SET_DRAW_STATE_0_GROUP_ID__MASK;
436 }
437
438 #define REG_CP_SET_DRAW_STATE_1 0x00000001
439 #define CP_SET_DRAW_STATE_1_ADDR__MASK 0xffffffff
440 #define CP_SET_DRAW_STATE_1_ADDR__SHIFT 0
441 static inline uint32_t CP_SET_DRAW_STATE_1_ADDR(uint32_t val)
442 {
443 return ((val) << CP_SET_DRAW_STATE_1_ADDR__SHIFT) & CP_SET_DRAW_STATE_1_ADDR__MASK;
444 }
445
446 #define REG_CP_SET_BIN_0 0x00000000
447
448 #define REG_CP_SET_BIN_1 0x00000001
449 #define CP_SET_BIN_1_X1__MASK 0x0000ffff
450 #define CP_SET_BIN_1_X1__SHIFT 0
451 static inline uint32_t CP_SET_BIN_1_X1(uint32_t val)
452 {
453 return ((val) << CP_SET_BIN_1_X1__SHIFT) & CP_SET_BIN_1_X1__MASK;
454 }
455 #define CP_SET_BIN_1_Y1__MASK 0xffff0000
456 #define CP_SET_BIN_1_Y1__SHIFT 16
457 static inline uint32_t CP_SET_BIN_1_Y1(uint32_t val)
458 {
459 return ((val) << CP_SET_BIN_1_Y1__SHIFT) & CP_SET_BIN_1_Y1__MASK;
460 }
461
462 #define REG_CP_SET_BIN_2 0x00000002
463 #define CP_SET_BIN_2_X2__MASK 0x0000ffff
464 #define CP_SET_BIN_2_X2__SHIFT 0
465 static inline uint32_t CP_SET_BIN_2_X2(uint32_t val)
466 {
467 return ((val) << CP_SET_BIN_2_X2__SHIFT) & CP_SET_BIN_2_X2__MASK;
468 }
469 #define CP_SET_BIN_2_Y2__MASK 0xffff0000
470 #define CP_SET_BIN_2_Y2__SHIFT 16
471 static inline uint32_t CP_SET_BIN_2_Y2(uint32_t val)
472 {
473 return ((val) << CP_SET_BIN_2_Y2__SHIFT) & CP_SET_BIN_2_Y2__MASK;
474 }
475
476 #define REG_CP_SET_BIN_DATA_0 0x00000000
477 #define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK 0xffffffff
478 #define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT 0
479 static inline uint32_t CP_SET_BIN_DATA_0_BIN_DATA_ADDR(uint32_t val)
480 {
481 return ((val) << CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT) & CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK;
482 }
483
484 #define REG_CP_SET_BIN_DATA_1 0x00000001
485 #define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK 0xffffffff
486 #define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT 0
487 static inline uint32_t CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS(uint32_t val)
488 {
489 return ((val) << CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT) & CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK;
490 }
491
492
493 #endif /* ADRENO_PM4_XML */