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freedreno: update generated headers
[mesa.git] / src / gallium / drivers / freedreno / adreno_pm4.xml.h
1 #ifndef ADRENO_PM4_XML
2 #define ADRENO_PM4_XML
3
4 /* Autogenerated file, DO NOT EDIT manually!
5
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
9
10 The rules-ng-ng source files this header was generated from are:
11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2016-04-26 17:56:44)
12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2016-02-10 17:07:21)
13 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32907 bytes, from 2016-11-26 23:01:08)
14 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 12025 bytes, from 2016-11-26 23:01:08)
15 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 22544 bytes, from 2016-12-05 13:03:25)
16 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2016-11-26 23:01:08)
17 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 110765 bytes, from 2016-11-26 23:01:48)
18 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 92389 bytes, from 2016-12-06 22:06:14)
19 - /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2015-09-24 17:30:00)
20
21 Copyright (C) 2013-2016 by the following authors:
22 - Rob Clark <robdclark@gmail.com> (robclark)
23 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
24
25 Permission is hereby granted, free of charge, to any person obtaining
26 a copy of this software and associated documentation files (the
27 "Software"), to deal in the Software without restriction, including
28 without limitation the rights to use, copy, modify, merge, publish,
29 distribute, sublicense, and/or sell copies of the Software, and to
30 permit persons to whom the Software is furnished to do so, subject to
31 the following conditions:
32
33 The above copyright notice and this permission notice (including the
34 next paragraph) shall be included in all copies or substantial
35 portions of the Software.
36
37 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
38 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
39 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
40 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
41 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
42 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
43 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
44 */
45
46
47 enum vgt_event_type {
48 VS_DEALLOC = 0,
49 PS_DEALLOC = 1,
50 VS_DONE_TS = 2,
51 PS_DONE_TS = 3,
52 CACHE_FLUSH_TS = 4,
53 CONTEXT_DONE = 5,
54 CACHE_FLUSH = 6,
55 HLSQ_FLUSH = 7,
56 VIZQUERY_START = 7,
57 VIZQUERY_END = 8,
58 SC_WAIT_WC = 9,
59 RST_PIX_CNT = 13,
60 RST_VTX_CNT = 14,
61 TILE_FLUSH = 15,
62 STAT_EVENT = 16,
63 CACHE_FLUSH_AND_INV_TS_EVENT = 20,
64 ZPASS_DONE = 21,
65 CACHE_FLUSH_AND_INV_EVENT = 22,
66 PERFCOUNTER_START = 23,
67 PERFCOUNTER_STOP = 24,
68 VS_FETCH_DONE = 27,
69 FACENESS_FLUSH = 28,
70 UNK_1C = 28,
71 UNK_1D = 29,
72 BLIT = 30,
73 UNK_26 = 38,
74 };
75
76 enum pc_di_primtype {
77 DI_PT_NONE = 0,
78 DI_PT_POINTLIST_PSIZE = 1,
79 DI_PT_LINELIST = 2,
80 DI_PT_LINESTRIP = 3,
81 DI_PT_TRILIST = 4,
82 DI_PT_TRIFAN = 5,
83 DI_PT_TRISTRIP = 6,
84 DI_PT_LINELOOP = 7,
85 DI_PT_RECTLIST = 8,
86 DI_PT_POINTLIST = 9,
87 DI_PT_LINE_ADJ = 10,
88 DI_PT_LINESTRIP_ADJ = 11,
89 DI_PT_TRI_ADJ = 12,
90 DI_PT_TRISTRIP_ADJ = 13,
91 };
92
93 enum pc_di_src_sel {
94 DI_SRC_SEL_DMA = 0,
95 DI_SRC_SEL_IMMEDIATE = 1,
96 DI_SRC_SEL_AUTO_INDEX = 2,
97 DI_SRC_SEL_RESERVED = 3,
98 };
99
100 enum pc_di_index_size {
101 INDEX_SIZE_IGN = 0,
102 INDEX_SIZE_16_BIT = 0,
103 INDEX_SIZE_32_BIT = 1,
104 INDEX_SIZE_8_BIT = 2,
105 INDEX_SIZE_INVALID = 0,
106 };
107
108 enum pc_di_vis_cull_mode {
109 IGNORE_VISIBILITY = 0,
110 USE_VISIBILITY = 1,
111 };
112
113 enum adreno_pm4_packet_type {
114 CP_TYPE0_PKT = 0,
115 CP_TYPE1_PKT = 0x40000000,
116 CP_TYPE2_PKT = 0x80000000,
117 CP_TYPE3_PKT = 0xc0000000,
118 CP_TYPE4_PKT = 0x40000000,
119 CP_TYPE7_PKT = 0x70000000,
120 };
121
122 enum adreno_pm4_type3_packets {
123 CP_ME_INIT = 72,
124 CP_NOP = 16,
125 CP_PREEMPT_ENABLE = 28,
126 CP_PREEMPT_TOKEN = 30,
127 CP_INDIRECT_BUFFER = 63,
128 CP_INDIRECT_BUFFER_PFD = 55,
129 CP_WAIT_FOR_IDLE = 38,
130 CP_WAIT_REG_MEM = 60,
131 CP_WAIT_REG_EQ = 82,
132 CP_WAIT_REG_GTE = 83,
133 CP_WAIT_UNTIL_READ = 92,
134 CP_WAIT_IB_PFD_COMPLETE = 93,
135 CP_REG_RMW = 33,
136 CP_SET_BIN_DATA = 47,
137 CP_REG_TO_MEM = 62,
138 CP_MEM_WRITE = 61,
139 CP_MEM_WRITE_CNTR = 79,
140 CP_COND_EXEC = 68,
141 CP_COND_WRITE = 69,
142 CP_EVENT_WRITE = 70,
143 CP_EVENT_WRITE_SHD = 88,
144 CP_EVENT_WRITE_CFL = 89,
145 CP_EVENT_WRITE_ZPD = 91,
146 CP_RUN_OPENCL = 49,
147 CP_DRAW_INDX = 34,
148 CP_DRAW_INDX_2 = 54,
149 CP_DRAW_INDX_BIN = 52,
150 CP_DRAW_INDX_2_BIN = 53,
151 CP_VIZ_QUERY = 35,
152 CP_SET_STATE = 37,
153 CP_SET_CONSTANT = 45,
154 CP_IM_LOAD = 39,
155 CP_IM_LOAD_IMMEDIATE = 43,
156 CP_LOAD_CONSTANT_CONTEXT = 46,
157 CP_INVALIDATE_STATE = 59,
158 CP_SET_SHADER_BASES = 74,
159 CP_SET_BIN_MASK = 80,
160 CP_SET_BIN_SELECT = 81,
161 CP_CONTEXT_UPDATE = 94,
162 CP_INTERRUPT = 64,
163 CP_IM_STORE = 44,
164 CP_SET_DRAW_INIT_FLAGS = 75,
165 CP_SET_PROTECTED_MODE = 95,
166 CP_BOOTSTRAP_UCODE = 111,
167 CP_LOAD_STATE = 48,
168 CP_COND_INDIRECT_BUFFER_PFE = 58,
169 CP_COND_INDIRECT_BUFFER_PFD = 50,
170 CP_INDIRECT_BUFFER_PFE = 63,
171 CP_SET_BIN = 76,
172 CP_TEST_TWO_MEMS = 113,
173 CP_REG_WR_NO_CTXT = 120,
174 CP_RECORD_PFP_TIMESTAMP = 17,
175 CP_SET_SECURE_MODE = 102,
176 CP_WAIT_FOR_ME = 19,
177 CP_SET_DRAW_STATE = 67,
178 CP_DRAW_INDX_OFFSET = 56,
179 CP_DRAW_INDIRECT = 40,
180 CP_DRAW_INDX_INDIRECT = 41,
181 CP_DRAW_AUTO = 36,
182 CP_UNKNOWN_19 = 25,
183 CP_UNKNOWN_1A = 26,
184 CP_UNKNOWN_4E = 78,
185 CP_WIDE_REG_WRITE = 116,
186 CP_SCRATCH_TO_REG = 77,
187 CP_REG_TO_SCRATCH = 74,
188 CP_WAIT_MEM_WRITES = 18,
189 CP_COND_REG_EXEC = 71,
190 CP_MEM_TO_REG = 66,
191 CP_EXEC_CS = 51,
192 CP_PERFCOUNTER_ACTION = 80,
193 CP_SMMU_TABLE_UPDATE = 83,
194 CP_CONTEXT_REG_BUNCH = 92,
195 CP_YIELD_ENABLE = 28,
196 CP_SKIP_IB2_ENABLE_GLOBAL = 29,
197 CP_SKIP_IB2_ENABLE_LOCAL = 35,
198 CP_SET_SUBDRAW_SIZE = 53,
199 CP_SET_VISIBILITY_OVERRIDE = 100,
200 CP_PREEMPT_ENABLE_GLOBAL = 105,
201 CP_PREEMPT_ENABLE_LOCAL = 106,
202 CP_CONTEXT_SWITCH_YIELD = 107,
203 CP_SET_RENDER_MODE = 108,
204 CP_COMPUTE_CHECKPOINT = 110,
205 CP_MEM_TO_MEM = 115,
206 CP_BLIT = 44,
207 IN_IB_PREFETCH_END = 23,
208 IN_SUBBLK_PREFETCH = 31,
209 IN_INSTR_PREFETCH = 32,
210 IN_INSTR_MATCH = 71,
211 IN_CONST_PREFETCH = 73,
212 IN_INCR_UPDT_STATE = 85,
213 IN_INCR_UPDT_CONST = 86,
214 IN_INCR_UPDT_INSTR = 87,
215 };
216
217 enum adreno_state_block {
218 SB_VERT_TEX = 0,
219 SB_VERT_MIPADDR = 1,
220 SB_FRAG_TEX = 2,
221 SB_FRAG_MIPADDR = 3,
222 SB_VERT_SHADER = 4,
223 SB_GEOM_SHADER = 5,
224 SB_FRAG_SHADER = 6,
225 SB_COMPUTE_SHADER = 7,
226 };
227
228 enum adreno_state_type {
229 ST_SHADER = 0,
230 ST_CONSTANTS = 1,
231 };
232
233 enum adreno_state_src {
234 SS_DIRECT = 0,
235 SS_INVALID_ALL_IC = 2,
236 SS_INVALID_PART_IC = 3,
237 SS_INDIRECT = 4,
238 SS_INDIRECT_TCM = 5,
239 SS_INDIRECT_STM = 6,
240 };
241
242 enum a4xx_index_size {
243 INDEX4_SIZE_8_BIT = 0,
244 INDEX4_SIZE_16_BIT = 1,
245 INDEX4_SIZE_32_BIT = 2,
246 };
247
248 enum render_mode_cmd {
249 BYPASS = 1,
250 GMEM = 3,
251 BLIT2D = 5,
252 };
253
254 enum cp_blit_cmd {
255 BLIT_OP_FILL = 0,
256 BLIT_OP_COPY = 1,
257 };
258
259 #define REG_CP_LOAD_STATE_0 0x00000000
260 #define CP_LOAD_STATE_0_DST_OFF__MASK 0x0000ffff
261 #define CP_LOAD_STATE_0_DST_OFF__SHIFT 0
262 static inline uint32_t CP_LOAD_STATE_0_DST_OFF(uint32_t val)
263 {
264 return ((val) << CP_LOAD_STATE_0_DST_OFF__SHIFT) & CP_LOAD_STATE_0_DST_OFF__MASK;
265 }
266 #define CP_LOAD_STATE_0_STATE_SRC__MASK 0x00070000
267 #define CP_LOAD_STATE_0_STATE_SRC__SHIFT 16
268 static inline uint32_t CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val)
269 {
270 return ((val) << CP_LOAD_STATE_0_STATE_SRC__SHIFT) & CP_LOAD_STATE_0_STATE_SRC__MASK;
271 }
272 #define CP_LOAD_STATE_0_STATE_BLOCK__MASK 0x00380000
273 #define CP_LOAD_STATE_0_STATE_BLOCK__SHIFT 19
274 static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val)
275 {
276 return ((val) << CP_LOAD_STATE_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE_0_STATE_BLOCK__MASK;
277 }
278 #define CP_LOAD_STATE_0_NUM_UNIT__MASK 0xffc00000
279 #define CP_LOAD_STATE_0_NUM_UNIT__SHIFT 22
280 static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val)
281 {
282 return ((val) << CP_LOAD_STATE_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE_0_NUM_UNIT__MASK;
283 }
284
285 #define REG_CP_LOAD_STATE_1 0x00000001
286 #define CP_LOAD_STATE_1_STATE_TYPE__MASK 0x00000003
287 #define CP_LOAD_STATE_1_STATE_TYPE__SHIFT 0
288 static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val)
289 {
290 return ((val) << CP_LOAD_STATE_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE_1_STATE_TYPE__MASK;
291 }
292 #define CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK 0xfffffffc
293 #define CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT 2
294 static inline uint32_t CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val)
295 {
296 assert(!(val & 0x3));
297 return ((val >> 2) << CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK;
298 }
299
300 #define REG_CP_LOAD_STATE_2 0x00000002
301 #define CP_LOAD_STATE_2_EXT_SRC_ADDR_HI__MASK 0xffffffff
302 #define CP_LOAD_STATE_2_EXT_SRC_ADDR_HI__SHIFT 0
303 static inline uint32_t CP_LOAD_STATE_2_EXT_SRC_ADDR_HI(uint32_t val)
304 {
305 return ((val) << CP_LOAD_STATE_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE_2_EXT_SRC_ADDR_HI__MASK;
306 }
307
308 #define REG_CP_DRAW_INDX_0 0x00000000
309 #define CP_DRAW_INDX_0_VIZ_QUERY__MASK 0xffffffff
310 #define CP_DRAW_INDX_0_VIZ_QUERY__SHIFT 0
311 static inline uint32_t CP_DRAW_INDX_0_VIZ_QUERY(uint32_t val)
312 {
313 return ((val) << CP_DRAW_INDX_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_0_VIZ_QUERY__MASK;
314 }
315
316 #define REG_CP_DRAW_INDX_1 0x00000001
317 #define CP_DRAW_INDX_1_PRIM_TYPE__MASK 0x0000003f
318 #define CP_DRAW_INDX_1_PRIM_TYPE__SHIFT 0
319 static inline uint32_t CP_DRAW_INDX_1_PRIM_TYPE(enum pc_di_primtype val)
320 {
321 return ((val) << CP_DRAW_INDX_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_1_PRIM_TYPE__MASK;
322 }
323 #define CP_DRAW_INDX_1_SOURCE_SELECT__MASK 0x000000c0
324 #define CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT 6
325 static inline uint32_t CP_DRAW_INDX_1_SOURCE_SELECT(enum pc_di_src_sel val)
326 {
327 return ((val) << CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_1_SOURCE_SELECT__MASK;
328 }
329 #define CP_DRAW_INDX_1_VIS_CULL__MASK 0x00000600
330 #define CP_DRAW_INDX_1_VIS_CULL__SHIFT 9
331 static inline uint32_t CP_DRAW_INDX_1_VIS_CULL(enum pc_di_vis_cull_mode val)
332 {
333 return ((val) << CP_DRAW_INDX_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_1_VIS_CULL__MASK;
334 }
335 #define CP_DRAW_INDX_1_INDEX_SIZE__MASK 0x00000800
336 #define CP_DRAW_INDX_1_INDEX_SIZE__SHIFT 11
337 static inline uint32_t CP_DRAW_INDX_1_INDEX_SIZE(enum pc_di_index_size val)
338 {
339 return ((val) << CP_DRAW_INDX_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_1_INDEX_SIZE__MASK;
340 }
341 #define CP_DRAW_INDX_1_NOT_EOP 0x00001000
342 #define CP_DRAW_INDX_1_SMALL_INDEX 0x00002000
343 #define CP_DRAW_INDX_1_PRE_DRAW_INITIATOR_ENABLE 0x00004000
344 #define CP_DRAW_INDX_1_NUM_INSTANCES__MASK 0xff000000
345 #define CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT 24
346 static inline uint32_t CP_DRAW_INDX_1_NUM_INSTANCES(uint32_t val)
347 {
348 return ((val) << CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_1_NUM_INSTANCES__MASK;
349 }
350
351 #define REG_CP_DRAW_INDX_2 0x00000002
352 #define CP_DRAW_INDX_2_NUM_INDICES__MASK 0xffffffff
353 #define CP_DRAW_INDX_2_NUM_INDICES__SHIFT 0
354 static inline uint32_t CP_DRAW_INDX_2_NUM_INDICES(uint32_t val)
355 {
356 return ((val) << CP_DRAW_INDX_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_NUM_INDICES__MASK;
357 }
358
359 #define REG_CP_DRAW_INDX_3 0x00000003
360 #define CP_DRAW_INDX_3_INDX_BASE__MASK 0xffffffff
361 #define CP_DRAW_INDX_3_INDX_BASE__SHIFT 0
362 static inline uint32_t CP_DRAW_INDX_3_INDX_BASE(uint32_t val)
363 {
364 return ((val) << CP_DRAW_INDX_3_INDX_BASE__SHIFT) & CP_DRAW_INDX_3_INDX_BASE__MASK;
365 }
366
367 #define REG_CP_DRAW_INDX_4 0x00000004
368 #define CP_DRAW_INDX_4_INDX_SIZE__MASK 0xffffffff
369 #define CP_DRAW_INDX_4_INDX_SIZE__SHIFT 0
370 static inline uint32_t CP_DRAW_INDX_4_INDX_SIZE(uint32_t val)
371 {
372 return ((val) << CP_DRAW_INDX_4_INDX_SIZE__SHIFT) & CP_DRAW_INDX_4_INDX_SIZE__MASK;
373 }
374
375 #define REG_CP_DRAW_INDX_2_0 0x00000000
376 #define CP_DRAW_INDX_2_0_VIZ_QUERY__MASK 0xffffffff
377 #define CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT 0
378 static inline uint32_t CP_DRAW_INDX_2_0_VIZ_QUERY(uint32_t val)
379 {
380 return ((val) << CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_2_0_VIZ_QUERY__MASK;
381 }
382
383 #define REG_CP_DRAW_INDX_2_1 0x00000001
384 #define CP_DRAW_INDX_2_1_PRIM_TYPE__MASK 0x0000003f
385 #define CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT 0
386 static inline uint32_t CP_DRAW_INDX_2_1_PRIM_TYPE(enum pc_di_primtype val)
387 {
388 return ((val) << CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_2_1_PRIM_TYPE__MASK;
389 }
390 #define CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK 0x000000c0
391 #define CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT 6
392 static inline uint32_t CP_DRAW_INDX_2_1_SOURCE_SELECT(enum pc_di_src_sel val)
393 {
394 return ((val) << CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK;
395 }
396 #define CP_DRAW_INDX_2_1_VIS_CULL__MASK 0x00000600
397 #define CP_DRAW_INDX_2_1_VIS_CULL__SHIFT 9
398 static inline uint32_t CP_DRAW_INDX_2_1_VIS_CULL(enum pc_di_vis_cull_mode val)
399 {
400 return ((val) << CP_DRAW_INDX_2_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_2_1_VIS_CULL__MASK;
401 }
402 #define CP_DRAW_INDX_2_1_INDEX_SIZE__MASK 0x00000800
403 #define CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT 11
404 static inline uint32_t CP_DRAW_INDX_2_1_INDEX_SIZE(enum pc_di_index_size val)
405 {
406 return ((val) << CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_2_1_INDEX_SIZE__MASK;
407 }
408 #define CP_DRAW_INDX_2_1_NOT_EOP 0x00001000
409 #define CP_DRAW_INDX_2_1_SMALL_INDEX 0x00002000
410 #define CP_DRAW_INDX_2_1_PRE_DRAW_INITIATOR_ENABLE 0x00004000
411 #define CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK 0xff000000
412 #define CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT 24
413 static inline uint32_t CP_DRAW_INDX_2_1_NUM_INSTANCES(uint32_t val)
414 {
415 return ((val) << CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK;
416 }
417
418 #define REG_CP_DRAW_INDX_2_2 0x00000002
419 #define CP_DRAW_INDX_2_2_NUM_INDICES__MASK 0xffffffff
420 #define CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT 0
421 static inline uint32_t CP_DRAW_INDX_2_2_NUM_INDICES(uint32_t val)
422 {
423 return ((val) << CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_2_NUM_INDICES__MASK;
424 }
425
426 #define REG_CP_DRAW_INDX_OFFSET_0 0x00000000
427 #define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK 0x0000003f
428 #define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT 0
429 static inline uint32_t CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(enum pc_di_primtype val)
430 {
431 return ((val) << CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK;
432 }
433 #define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK 0x000000c0
434 #define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT 6
435 static inline uint32_t CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel val)
436 {
437 return ((val) << CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK;
438 }
439 #define CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK 0x00000300
440 #define CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT 8
441 static inline uint32_t CP_DRAW_INDX_OFFSET_0_VIS_CULL(enum pc_di_vis_cull_mode val)
442 {
443 return ((val) << CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT) & CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK;
444 }
445 #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK 0x00000c00
446 #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT 10
447 static inline uint32_t CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum a4xx_index_size val)
448 {
449 return ((val) << CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK;
450 }
451 #define CP_DRAW_INDX_OFFSET_0_TESS_MODE__MASK 0x01f00000
452 #define CP_DRAW_INDX_OFFSET_0_TESS_MODE__SHIFT 20
453 static inline uint32_t CP_DRAW_INDX_OFFSET_0_TESS_MODE(uint32_t val)
454 {
455 return ((val) << CP_DRAW_INDX_OFFSET_0_TESS_MODE__SHIFT) & CP_DRAW_INDX_OFFSET_0_TESS_MODE__MASK;
456 }
457
458 #define REG_CP_DRAW_INDX_OFFSET_1 0x00000001
459 #define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK 0xffffffff
460 #define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT 0
461 static inline uint32_t CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES(uint32_t val)
462 {
463 return ((val) << CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK;
464 }
465
466 #define REG_CP_DRAW_INDX_OFFSET_2 0x00000002
467 #define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK 0xffffffff
468 #define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT 0
469 static inline uint32_t CP_DRAW_INDX_OFFSET_2_NUM_INDICES(uint32_t val)
470 {
471 return ((val) << CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK;
472 }
473
474 #define REG_CP_DRAW_INDX_OFFSET_3 0x00000003
475
476 #define REG_CP_DRAW_INDX_OFFSET_4 0x00000004
477 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK 0xffffffff
478 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT 0
479 static inline uint32_t CP_DRAW_INDX_OFFSET_4_INDX_BASE(uint32_t val)
480 {
481 return ((val) << CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT) & CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK;
482 }
483
484 #define REG_CP_DRAW_INDX_OFFSET_5 0x00000005
485 #define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK 0xffffffff
486 #define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT 0
487 static inline uint32_t CP_DRAW_INDX_OFFSET_5_INDX_SIZE(uint32_t val)
488 {
489 return ((val) << CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK;
490 }
491
492 static inline uint32_t REG_CP_SET_DRAW_STATE_(uint32_t i0) { return 0x00000000 + 0x3*i0; }
493
494 static inline uint32_t REG_CP_SET_DRAW_STATE__0(uint32_t i0) { return 0x00000000 + 0x3*i0; }
495 #define CP_SET_DRAW_STATE__0_COUNT__MASK 0x0000ffff
496 #define CP_SET_DRAW_STATE__0_COUNT__SHIFT 0
497 static inline uint32_t CP_SET_DRAW_STATE__0_COUNT(uint32_t val)
498 {
499 return ((val) << CP_SET_DRAW_STATE__0_COUNT__SHIFT) & CP_SET_DRAW_STATE__0_COUNT__MASK;
500 }
501 #define CP_SET_DRAW_STATE__0_DIRTY 0x00010000
502 #define CP_SET_DRAW_STATE__0_DISABLE 0x00020000
503 #define CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS 0x00040000
504 #define CP_SET_DRAW_STATE__0_LOAD_IMMED 0x00080000
505 #define CP_SET_DRAW_STATE__0_GROUP_ID__MASK 0x1f000000
506 #define CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT 24
507 static inline uint32_t CP_SET_DRAW_STATE__0_GROUP_ID(uint32_t val)
508 {
509 return ((val) << CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT) & CP_SET_DRAW_STATE__0_GROUP_ID__MASK;
510 }
511
512 static inline uint32_t REG_CP_SET_DRAW_STATE__1(uint32_t i0) { return 0x00000001 + 0x3*i0; }
513 #define CP_SET_DRAW_STATE__1_ADDR_LO__MASK 0xffffffff
514 #define CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT 0
515 static inline uint32_t CP_SET_DRAW_STATE__1_ADDR_LO(uint32_t val)
516 {
517 return ((val) << CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT) & CP_SET_DRAW_STATE__1_ADDR_LO__MASK;
518 }
519
520 static inline uint32_t REG_CP_SET_DRAW_STATE__2(uint32_t i0) { return 0x00000002 + 0x3*i0; }
521 #define CP_SET_DRAW_STATE__2_ADDR_HI__MASK 0xffffffff
522 #define CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT 0
523 static inline uint32_t CP_SET_DRAW_STATE__2_ADDR_HI(uint32_t val)
524 {
525 return ((val) << CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT) & CP_SET_DRAW_STATE__2_ADDR_HI__MASK;
526 }
527
528 #define REG_CP_SET_BIN_0 0x00000000
529
530 #define REG_CP_SET_BIN_1 0x00000001
531 #define CP_SET_BIN_1_X1__MASK 0x0000ffff
532 #define CP_SET_BIN_1_X1__SHIFT 0
533 static inline uint32_t CP_SET_BIN_1_X1(uint32_t val)
534 {
535 return ((val) << CP_SET_BIN_1_X1__SHIFT) & CP_SET_BIN_1_X1__MASK;
536 }
537 #define CP_SET_BIN_1_Y1__MASK 0xffff0000
538 #define CP_SET_BIN_1_Y1__SHIFT 16
539 static inline uint32_t CP_SET_BIN_1_Y1(uint32_t val)
540 {
541 return ((val) << CP_SET_BIN_1_Y1__SHIFT) & CP_SET_BIN_1_Y1__MASK;
542 }
543
544 #define REG_CP_SET_BIN_2 0x00000002
545 #define CP_SET_BIN_2_X2__MASK 0x0000ffff
546 #define CP_SET_BIN_2_X2__SHIFT 0
547 static inline uint32_t CP_SET_BIN_2_X2(uint32_t val)
548 {
549 return ((val) << CP_SET_BIN_2_X2__SHIFT) & CP_SET_BIN_2_X2__MASK;
550 }
551 #define CP_SET_BIN_2_Y2__MASK 0xffff0000
552 #define CP_SET_BIN_2_Y2__SHIFT 16
553 static inline uint32_t CP_SET_BIN_2_Y2(uint32_t val)
554 {
555 return ((val) << CP_SET_BIN_2_Y2__SHIFT) & CP_SET_BIN_2_Y2__MASK;
556 }
557
558 #define REG_CP_SET_BIN_DATA_0 0x00000000
559 #define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK 0xffffffff
560 #define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT 0
561 static inline uint32_t CP_SET_BIN_DATA_0_BIN_DATA_ADDR(uint32_t val)
562 {
563 return ((val) << CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT) & CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK;
564 }
565
566 #define REG_CP_SET_BIN_DATA_1 0x00000001
567 #define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK 0xffffffff
568 #define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT 0
569 static inline uint32_t CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS(uint32_t val)
570 {
571 return ((val) << CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT) & CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK;
572 }
573
574 #define REG_CP_REG_TO_MEM_0 0x00000000
575 #define CP_REG_TO_MEM_0_REG__MASK 0x0000ffff
576 #define CP_REG_TO_MEM_0_REG__SHIFT 0
577 static inline uint32_t CP_REG_TO_MEM_0_REG(uint32_t val)
578 {
579 return ((val) << CP_REG_TO_MEM_0_REG__SHIFT) & CP_REG_TO_MEM_0_REG__MASK;
580 }
581 #define CP_REG_TO_MEM_0_CNT__MASK 0x3ff80000
582 #define CP_REG_TO_MEM_0_CNT__SHIFT 19
583 static inline uint32_t CP_REG_TO_MEM_0_CNT(uint32_t val)
584 {
585 return ((val) << CP_REG_TO_MEM_0_CNT__SHIFT) & CP_REG_TO_MEM_0_CNT__MASK;
586 }
587 #define CP_REG_TO_MEM_0_64B 0x40000000
588 #define CP_REG_TO_MEM_0_ACCUMULATE 0x80000000
589
590 #define REG_CP_REG_TO_MEM_1 0x00000001
591 #define CP_REG_TO_MEM_1_DEST__MASK 0xffffffff
592 #define CP_REG_TO_MEM_1_DEST__SHIFT 0
593 static inline uint32_t CP_REG_TO_MEM_1_DEST(uint32_t val)
594 {
595 return ((val) << CP_REG_TO_MEM_1_DEST__SHIFT) & CP_REG_TO_MEM_1_DEST__MASK;
596 }
597
598 #define REG_CP_DISPATCH_COMPUTE_0 0x00000000
599
600 #define REG_CP_DISPATCH_COMPUTE_1 0x00000001
601 #define CP_DISPATCH_COMPUTE_1_X__MASK 0xffffffff
602 #define CP_DISPATCH_COMPUTE_1_X__SHIFT 0
603 static inline uint32_t CP_DISPATCH_COMPUTE_1_X(uint32_t val)
604 {
605 return ((val) << CP_DISPATCH_COMPUTE_1_X__SHIFT) & CP_DISPATCH_COMPUTE_1_X__MASK;
606 }
607
608 #define REG_CP_DISPATCH_COMPUTE_2 0x00000002
609 #define CP_DISPATCH_COMPUTE_2_Y__MASK 0xffffffff
610 #define CP_DISPATCH_COMPUTE_2_Y__SHIFT 0
611 static inline uint32_t CP_DISPATCH_COMPUTE_2_Y(uint32_t val)
612 {
613 return ((val) << CP_DISPATCH_COMPUTE_2_Y__SHIFT) & CP_DISPATCH_COMPUTE_2_Y__MASK;
614 }
615
616 #define REG_CP_DISPATCH_COMPUTE_3 0x00000003
617 #define CP_DISPATCH_COMPUTE_3_Z__MASK 0xffffffff
618 #define CP_DISPATCH_COMPUTE_3_Z__SHIFT 0
619 static inline uint32_t CP_DISPATCH_COMPUTE_3_Z(uint32_t val)
620 {
621 return ((val) << CP_DISPATCH_COMPUTE_3_Z__SHIFT) & CP_DISPATCH_COMPUTE_3_Z__MASK;
622 }
623
624 #define REG_CP_SET_RENDER_MODE_0 0x00000000
625 #define CP_SET_RENDER_MODE_0_MODE__MASK 0x000001ff
626 #define CP_SET_RENDER_MODE_0_MODE__SHIFT 0
627 static inline uint32_t CP_SET_RENDER_MODE_0_MODE(enum render_mode_cmd val)
628 {
629 return ((val) << CP_SET_RENDER_MODE_0_MODE__SHIFT) & CP_SET_RENDER_MODE_0_MODE__MASK;
630 }
631
632 #define REG_CP_SET_RENDER_MODE_1 0x00000001
633 #define CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK 0xffffffff
634 #define CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT 0
635 static inline uint32_t CP_SET_RENDER_MODE_1_ADDR_0_LO(uint32_t val)
636 {
637 return ((val) << CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT) & CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK;
638 }
639
640 #define REG_CP_SET_RENDER_MODE_2 0x00000002
641 #define CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK 0xffffffff
642 #define CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT 0
643 static inline uint32_t CP_SET_RENDER_MODE_2_ADDR_0_HI(uint32_t val)
644 {
645 return ((val) << CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT) & CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK;
646 }
647
648 #define REG_CP_SET_RENDER_MODE_3 0x00000003
649 #define CP_SET_RENDER_MODE_3_GMEM_ENABLE 0x00000010
650
651 #define REG_CP_SET_RENDER_MODE_4 0x00000004
652
653 #define REG_CP_SET_RENDER_MODE_5 0x00000005
654 #define CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK 0xffffffff
655 #define CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT 0
656 static inline uint32_t CP_SET_RENDER_MODE_5_ADDR_1_LEN(uint32_t val)
657 {
658 return ((val) << CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT) & CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK;
659 }
660
661 #define REG_CP_SET_RENDER_MODE_6 0x00000006
662 #define CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK 0xffffffff
663 #define CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT 0
664 static inline uint32_t CP_SET_RENDER_MODE_6_ADDR_1_LO(uint32_t val)
665 {
666 return ((val) << CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT) & CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK;
667 }
668
669 #define REG_CP_SET_RENDER_MODE_7 0x00000007
670 #define CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK 0xffffffff
671 #define CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT 0
672 static inline uint32_t CP_SET_RENDER_MODE_7_ADDR_1_HI(uint32_t val)
673 {
674 return ((val) << CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT) & CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK;
675 }
676
677 #define REG_CP_PERFCOUNTER_ACTION_0 0x00000000
678
679 #define REG_CP_PERFCOUNTER_ACTION_1 0x00000001
680 #define CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK 0xffffffff
681 #define CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT 0
682 static inline uint32_t CP_PERFCOUNTER_ACTION_1_ADDR_0_LO(uint32_t val)
683 {
684 return ((val) << CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT) & CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK;
685 }
686
687 #define REG_CP_PERFCOUNTER_ACTION_2 0x00000002
688 #define CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK 0xffffffff
689 #define CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT 0
690 static inline uint32_t CP_PERFCOUNTER_ACTION_2_ADDR_0_HI(uint32_t val)
691 {
692 return ((val) << CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT) & CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK;
693 }
694
695 #define REG_CP_EVENT_WRITE_0 0x00000000
696 #define CP_EVENT_WRITE_0_EVENT__MASK 0x000000ff
697 #define CP_EVENT_WRITE_0_EVENT__SHIFT 0
698 static inline uint32_t CP_EVENT_WRITE_0_EVENT(enum vgt_event_type val)
699 {
700 return ((val) << CP_EVENT_WRITE_0_EVENT__SHIFT) & CP_EVENT_WRITE_0_EVENT__MASK;
701 }
702
703 #define REG_CP_EVENT_WRITE_1 0x00000001
704 #define CP_EVENT_WRITE_1_ADDR_0_LO__MASK 0xffffffff
705 #define CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT 0
706 static inline uint32_t CP_EVENT_WRITE_1_ADDR_0_LO(uint32_t val)
707 {
708 return ((val) << CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT) & CP_EVENT_WRITE_1_ADDR_0_LO__MASK;
709 }
710
711 #define REG_CP_EVENT_WRITE_2 0x00000002
712 #define CP_EVENT_WRITE_2_ADDR_0_HI__MASK 0xffffffff
713 #define CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT 0
714 static inline uint32_t CP_EVENT_WRITE_2_ADDR_0_HI(uint32_t val)
715 {
716 return ((val) << CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT) & CP_EVENT_WRITE_2_ADDR_0_HI__MASK;
717 }
718
719 #define REG_CP_EVENT_WRITE_3 0x00000003
720
721 #define REG_CP_BLIT_0 0x00000000
722 #define CP_BLIT_0_OP__MASK 0x0000000f
723 #define CP_BLIT_0_OP__SHIFT 0
724 static inline uint32_t CP_BLIT_0_OP(enum cp_blit_cmd val)
725 {
726 return ((val) << CP_BLIT_0_OP__SHIFT) & CP_BLIT_0_OP__MASK;
727 }
728
729 #define REG_CP_BLIT_1 0x00000001
730 #define CP_BLIT_1_SRC_X1__MASK 0x0000ffff
731 #define CP_BLIT_1_SRC_X1__SHIFT 0
732 static inline uint32_t CP_BLIT_1_SRC_X1(uint32_t val)
733 {
734 return ((val) << CP_BLIT_1_SRC_X1__SHIFT) & CP_BLIT_1_SRC_X1__MASK;
735 }
736 #define CP_BLIT_1_SRC_Y1__MASK 0xffff0000
737 #define CP_BLIT_1_SRC_Y1__SHIFT 16
738 static inline uint32_t CP_BLIT_1_SRC_Y1(uint32_t val)
739 {
740 return ((val) << CP_BLIT_1_SRC_Y1__SHIFT) & CP_BLIT_1_SRC_Y1__MASK;
741 }
742
743 #define REG_CP_BLIT_2 0x00000002
744 #define CP_BLIT_2_SRC_X2__MASK 0x0000ffff
745 #define CP_BLIT_2_SRC_X2__SHIFT 0
746 static inline uint32_t CP_BLIT_2_SRC_X2(uint32_t val)
747 {
748 return ((val) << CP_BLIT_2_SRC_X2__SHIFT) & CP_BLIT_2_SRC_X2__MASK;
749 }
750 #define CP_BLIT_2_SRC_Y2__MASK 0xffff0000
751 #define CP_BLIT_2_SRC_Y2__SHIFT 16
752 static inline uint32_t CP_BLIT_2_SRC_Y2(uint32_t val)
753 {
754 return ((val) << CP_BLIT_2_SRC_Y2__SHIFT) & CP_BLIT_2_SRC_Y2__MASK;
755 }
756
757 #define REG_CP_BLIT_3 0x00000003
758 #define CP_BLIT_3_DST_X1__MASK 0x0000ffff
759 #define CP_BLIT_3_DST_X1__SHIFT 0
760 static inline uint32_t CP_BLIT_3_DST_X1(uint32_t val)
761 {
762 return ((val) << CP_BLIT_3_DST_X1__SHIFT) & CP_BLIT_3_DST_X1__MASK;
763 }
764 #define CP_BLIT_3_DST_Y1__MASK 0xffff0000
765 #define CP_BLIT_3_DST_Y1__SHIFT 16
766 static inline uint32_t CP_BLIT_3_DST_Y1(uint32_t val)
767 {
768 return ((val) << CP_BLIT_3_DST_Y1__SHIFT) & CP_BLIT_3_DST_Y1__MASK;
769 }
770
771 #define REG_CP_BLIT_4 0x00000004
772 #define CP_BLIT_4_DST_X2__MASK 0x0000ffff
773 #define CP_BLIT_4_DST_X2__SHIFT 0
774 static inline uint32_t CP_BLIT_4_DST_X2(uint32_t val)
775 {
776 return ((val) << CP_BLIT_4_DST_X2__SHIFT) & CP_BLIT_4_DST_X2__MASK;
777 }
778 #define CP_BLIT_4_DST_Y2__MASK 0xffff0000
779 #define CP_BLIT_4_DST_Y2__SHIFT 16
780 static inline uint32_t CP_BLIT_4_DST_Y2(uint32_t val)
781 {
782 return ((val) << CP_BLIT_4_DST_Y2__SHIFT) & CP_BLIT_4_DST_Y2__MASK;
783 }
784
785
786 #endif /* ADRENO_PM4_XML */