4 /* Autogenerated file, DO NOT EDIT manually!
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
10 The rules-ng-ng source files this header was generated from are:
11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2015-05-20 20:03:07)
12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-05-20 20:03:07)
13 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2015-05-20 20:03:14)
14 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2015-05-20 20:03:14)
15 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 14968 bytes, from 2015-05-20 20:12:27)
16 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 66709 bytes, from 2015-05-20 20:03:14)
17 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 63728 bytes, from 2015-08-05 18:07:28)
19 Copyright (C) 2013-2015 by the following authors:
20 - Rob Clark <robdclark@gmail.com> (robclark)
22 Permission is hereby granted, free of charge, to any person obtaining
23 a copy of this software and associated documentation files (the
24 "Software"), to deal in the Software without restriction, including
25 without limitation the rights to use, copy, modify, merge, publish,
26 distribute, sublicense, and/or sell copies of the Software, and to
27 permit persons to whom the Software is furnished to do so, subject to
28 the following conditions:
30 The above copyright notice and this permission notice (including the
31 next paragraph) shall be included in all copies or substantial
32 portions of the Software.
34 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
36 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
37 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
38 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
39 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
40 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
59 CACHE_FLUSH_AND_INV_TS_EVENT
= 20,
61 CACHE_FLUSH_AND_INV_EVENT
= 22,
62 PERFCOUNTER_START
= 23,
63 PERFCOUNTER_STOP
= 24,
70 DI_PT_POINTLIST_PSIZE
= 1,
80 DI_PT_LINESTRIP_ADJ
= 11,
82 DI_PT_TRISTRIP_ADJ
= 13,
88 DI_SRC_SEL_IMMEDIATE
= 1,
89 DI_SRC_SEL_AUTO_INDEX
= 2,
90 DI_SRC_SEL_RESERVED
= 3,
93 enum pc_di_index_size
{
95 INDEX_SIZE_16_BIT
= 0,
96 INDEX_SIZE_32_BIT
= 1,
98 INDEX_SIZE_INVALID
= 0,
101 enum pc_di_vis_cull_mode
{
102 IGNORE_VISIBILITY
= 0,
106 enum adreno_pm4_packet_type
{
108 CP_TYPE1_PKT
= 0x40000000,
109 CP_TYPE2_PKT
= 0x80000000,
110 CP_TYPE3_PKT
= 0xc0000000,
113 enum adreno_pm4_type3_packets
{
116 CP_INDIRECT_BUFFER
= 63,
117 CP_INDIRECT_BUFFER_PFD
= 55,
118 CP_WAIT_FOR_IDLE
= 38,
119 CP_WAIT_REG_MEM
= 60,
121 CP_WAIT_REG_GTE
= 83,
122 CP_WAIT_UNTIL_READ
= 92,
123 CP_WAIT_IB_PFD_COMPLETE
= 93,
125 CP_SET_BIN_DATA
= 47,
128 CP_MEM_WRITE_CNTR
= 79,
132 CP_EVENT_WRITE_SHD
= 88,
133 CP_EVENT_WRITE_CFL
= 89,
134 CP_EVENT_WRITE_ZPD
= 91,
138 CP_DRAW_INDX_BIN
= 52,
139 CP_DRAW_INDX_2_BIN
= 53,
142 CP_SET_CONSTANT
= 45,
144 CP_IM_LOAD_IMMEDIATE
= 43,
145 CP_LOAD_CONSTANT_CONTEXT
= 46,
146 CP_INVALIDATE_STATE
= 59,
147 CP_SET_SHADER_BASES
= 74,
148 CP_SET_BIN_MASK
= 80,
149 CP_SET_BIN_SELECT
= 81,
150 CP_CONTEXT_UPDATE
= 94,
153 CP_SET_DRAW_INIT_FLAGS
= 75,
154 CP_SET_PROTECTED_MODE
= 95,
155 CP_BOOTSTRAP_UCODE
= 111,
157 CP_COND_INDIRECT_BUFFER_PFE
= 58,
158 CP_COND_INDIRECT_BUFFER_PFD
= 50,
159 CP_INDIRECT_BUFFER_PFE
= 63,
161 CP_TEST_TWO_MEMS
= 113,
162 CP_REG_WR_NO_CTXT
= 120,
163 CP_RECORD_PFP_TIMESTAMP
= 17,
165 CP_SET_DRAW_STATE
= 67,
166 CP_DRAW_INDX_OFFSET
= 56,
167 CP_DRAW_INDIRECT
= 40,
168 CP_DRAW_INDX_INDIRECT
= 41,
173 CP_WIDE_REG_WRITE
= 116,
174 IN_IB_PREFETCH_END
= 23,
175 IN_SUBBLK_PREFETCH
= 31,
176 IN_INSTR_PREFETCH
= 32,
178 IN_CONST_PREFETCH
= 73,
179 IN_INCR_UPDT_STATE
= 85,
180 IN_INCR_UPDT_CONST
= 86,
181 IN_INCR_UPDT_INSTR
= 87,
184 enum adreno_state_block
{
194 enum adreno_state_type
{
199 enum adreno_state_src
{
204 enum a4xx_index_size
{
205 INDEX4_SIZE_8_BIT
= 0,
206 INDEX4_SIZE_16_BIT
= 1,
207 INDEX4_SIZE_32_BIT
= 2,
210 #define REG_CP_LOAD_STATE_0 0x00000000
211 #define CP_LOAD_STATE_0_DST_OFF__MASK 0x0000ffff
212 #define CP_LOAD_STATE_0_DST_OFF__SHIFT 0
213 static inline uint32_t CP_LOAD_STATE_0_DST_OFF(uint32_t val
)
215 return ((val
) << CP_LOAD_STATE_0_DST_OFF__SHIFT
) & CP_LOAD_STATE_0_DST_OFF__MASK
;
217 #define CP_LOAD_STATE_0_STATE_SRC__MASK 0x00070000
218 #define CP_LOAD_STATE_0_STATE_SRC__SHIFT 16
219 static inline uint32_t CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val
)
221 return ((val
) << CP_LOAD_STATE_0_STATE_SRC__SHIFT
) & CP_LOAD_STATE_0_STATE_SRC__MASK
;
223 #define CP_LOAD_STATE_0_STATE_BLOCK__MASK 0x00380000
224 #define CP_LOAD_STATE_0_STATE_BLOCK__SHIFT 19
225 static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val
)
227 return ((val
) << CP_LOAD_STATE_0_STATE_BLOCK__SHIFT
) & CP_LOAD_STATE_0_STATE_BLOCK__MASK
;
229 #define CP_LOAD_STATE_0_NUM_UNIT__MASK 0x7fc00000
230 #define CP_LOAD_STATE_0_NUM_UNIT__SHIFT 22
231 static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val
)
233 return ((val
) << CP_LOAD_STATE_0_NUM_UNIT__SHIFT
) & CP_LOAD_STATE_0_NUM_UNIT__MASK
;
236 #define REG_CP_LOAD_STATE_1 0x00000001
237 #define CP_LOAD_STATE_1_STATE_TYPE__MASK 0x00000003
238 #define CP_LOAD_STATE_1_STATE_TYPE__SHIFT 0
239 static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val
)
241 return ((val
) << CP_LOAD_STATE_1_STATE_TYPE__SHIFT
) & CP_LOAD_STATE_1_STATE_TYPE__MASK
;
243 #define CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK 0xfffffffc
244 #define CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT 2
245 static inline uint32_t CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val
)
247 return ((val
>> 2) << CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT
) & CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK
;
250 #define REG_CP_DRAW_INDX_0 0x00000000
251 #define CP_DRAW_INDX_0_VIZ_QUERY__MASK 0xffffffff
252 #define CP_DRAW_INDX_0_VIZ_QUERY__SHIFT 0
253 static inline uint32_t CP_DRAW_INDX_0_VIZ_QUERY(uint32_t val
)
255 return ((val
) << CP_DRAW_INDX_0_VIZ_QUERY__SHIFT
) & CP_DRAW_INDX_0_VIZ_QUERY__MASK
;
258 #define REG_CP_DRAW_INDX_1 0x00000001
259 #define CP_DRAW_INDX_1_PRIM_TYPE__MASK 0x0000003f
260 #define CP_DRAW_INDX_1_PRIM_TYPE__SHIFT 0
261 static inline uint32_t CP_DRAW_INDX_1_PRIM_TYPE(enum pc_di_primtype val
)
263 return ((val
) << CP_DRAW_INDX_1_PRIM_TYPE__SHIFT
) & CP_DRAW_INDX_1_PRIM_TYPE__MASK
;
265 #define CP_DRAW_INDX_1_SOURCE_SELECT__MASK 0x000000c0
266 #define CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT 6
267 static inline uint32_t CP_DRAW_INDX_1_SOURCE_SELECT(enum pc_di_src_sel val
)
269 return ((val
) << CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT
) & CP_DRAW_INDX_1_SOURCE_SELECT__MASK
;
271 #define CP_DRAW_INDX_1_VIS_CULL__MASK 0x00000600
272 #define CP_DRAW_INDX_1_VIS_CULL__SHIFT 9
273 static inline uint32_t CP_DRAW_INDX_1_VIS_CULL(enum pc_di_vis_cull_mode val
)
275 return ((val
) << CP_DRAW_INDX_1_VIS_CULL__SHIFT
) & CP_DRAW_INDX_1_VIS_CULL__MASK
;
277 #define CP_DRAW_INDX_1_INDEX_SIZE__MASK 0x00000800
278 #define CP_DRAW_INDX_1_INDEX_SIZE__SHIFT 11
279 static inline uint32_t CP_DRAW_INDX_1_INDEX_SIZE(enum pc_di_index_size val
)
281 return ((val
) << CP_DRAW_INDX_1_INDEX_SIZE__SHIFT
) & CP_DRAW_INDX_1_INDEX_SIZE__MASK
;
283 #define CP_DRAW_INDX_1_NOT_EOP 0x00001000
284 #define CP_DRAW_INDX_1_SMALL_INDEX 0x00002000
285 #define CP_DRAW_INDX_1_PRE_DRAW_INITIATOR_ENABLE 0x00004000
286 #define CP_DRAW_INDX_1_NUM_INSTANCES__MASK 0xff000000
287 #define CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT 24
288 static inline uint32_t CP_DRAW_INDX_1_NUM_INSTANCES(uint32_t val
)
290 return ((val
) << CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT
) & CP_DRAW_INDX_1_NUM_INSTANCES__MASK
;
293 #define REG_CP_DRAW_INDX_2 0x00000002
294 #define CP_DRAW_INDX_2_NUM_INDICES__MASK 0xffffffff
295 #define CP_DRAW_INDX_2_NUM_INDICES__SHIFT 0
296 static inline uint32_t CP_DRAW_INDX_2_NUM_INDICES(uint32_t val
)
298 return ((val
) << CP_DRAW_INDX_2_NUM_INDICES__SHIFT
) & CP_DRAW_INDX_2_NUM_INDICES__MASK
;
301 #define REG_CP_DRAW_INDX_3 0x00000003
302 #define CP_DRAW_INDX_3_INDX_BASE__MASK 0xffffffff
303 #define CP_DRAW_INDX_3_INDX_BASE__SHIFT 0
304 static inline uint32_t CP_DRAW_INDX_3_INDX_BASE(uint32_t val
)
306 return ((val
) << CP_DRAW_INDX_3_INDX_BASE__SHIFT
) & CP_DRAW_INDX_3_INDX_BASE__MASK
;
309 #define REG_CP_DRAW_INDX_4 0x00000004
310 #define CP_DRAW_INDX_4_INDX_SIZE__MASK 0xffffffff
311 #define CP_DRAW_INDX_4_INDX_SIZE__SHIFT 0
312 static inline uint32_t CP_DRAW_INDX_4_INDX_SIZE(uint32_t val
)
314 return ((val
) << CP_DRAW_INDX_4_INDX_SIZE__SHIFT
) & CP_DRAW_INDX_4_INDX_SIZE__MASK
;
317 #define REG_CP_DRAW_INDX_2_0 0x00000000
318 #define CP_DRAW_INDX_2_0_VIZ_QUERY__MASK 0xffffffff
319 #define CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT 0
320 static inline uint32_t CP_DRAW_INDX_2_0_VIZ_QUERY(uint32_t val
)
322 return ((val
) << CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT
) & CP_DRAW_INDX_2_0_VIZ_QUERY__MASK
;
325 #define REG_CP_DRAW_INDX_2_1 0x00000001
326 #define CP_DRAW_INDX_2_1_PRIM_TYPE__MASK 0x0000003f
327 #define CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT 0
328 static inline uint32_t CP_DRAW_INDX_2_1_PRIM_TYPE(enum pc_di_primtype val
)
330 return ((val
) << CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT
) & CP_DRAW_INDX_2_1_PRIM_TYPE__MASK
;
332 #define CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK 0x000000c0
333 #define CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT 6
334 static inline uint32_t CP_DRAW_INDX_2_1_SOURCE_SELECT(enum pc_di_src_sel val
)
336 return ((val
) << CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT
) & CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK
;
338 #define CP_DRAW_INDX_2_1_VIS_CULL__MASK 0x00000600
339 #define CP_DRAW_INDX_2_1_VIS_CULL__SHIFT 9
340 static inline uint32_t CP_DRAW_INDX_2_1_VIS_CULL(enum pc_di_vis_cull_mode val
)
342 return ((val
) << CP_DRAW_INDX_2_1_VIS_CULL__SHIFT
) & CP_DRAW_INDX_2_1_VIS_CULL__MASK
;
344 #define CP_DRAW_INDX_2_1_INDEX_SIZE__MASK 0x00000800
345 #define CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT 11
346 static inline uint32_t CP_DRAW_INDX_2_1_INDEX_SIZE(enum pc_di_index_size val
)
348 return ((val
) << CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT
) & CP_DRAW_INDX_2_1_INDEX_SIZE__MASK
;
350 #define CP_DRAW_INDX_2_1_NOT_EOP 0x00001000
351 #define CP_DRAW_INDX_2_1_SMALL_INDEX 0x00002000
352 #define CP_DRAW_INDX_2_1_PRE_DRAW_INITIATOR_ENABLE 0x00004000
353 #define CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK 0xff000000
354 #define CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT 24
355 static inline uint32_t CP_DRAW_INDX_2_1_NUM_INSTANCES(uint32_t val
)
357 return ((val
) << CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT
) & CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK
;
360 #define REG_CP_DRAW_INDX_2_2 0x00000002
361 #define CP_DRAW_INDX_2_2_NUM_INDICES__MASK 0xffffffff
362 #define CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT 0
363 static inline uint32_t CP_DRAW_INDX_2_2_NUM_INDICES(uint32_t val
)
365 return ((val
) << CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT
) & CP_DRAW_INDX_2_2_NUM_INDICES__MASK
;
368 #define REG_CP_DRAW_INDX_OFFSET_0 0x00000000
369 #define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK 0x0000003f
370 #define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT 0
371 static inline uint32_t CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(enum pc_di_primtype val
)
373 return ((val
) << CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT
) & CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK
;
375 #define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK 0x000000c0
376 #define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT 6
377 static inline uint32_t CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel val
)
379 return ((val
) << CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT
) & CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK
;
381 #define CP_DRAW_INDX_OFFSET_0_TESSELLATE 0x00000100
382 #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK 0x00000c00
383 #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT 10
384 static inline uint32_t CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum a4xx_index_size val
)
386 return ((val
) << CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT
) & CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK
;
388 #define CP_DRAW_INDX_OFFSET_0_TESS_MODE__MASK 0x01f00000
389 #define CP_DRAW_INDX_OFFSET_0_TESS_MODE__SHIFT 20
390 static inline uint32_t CP_DRAW_INDX_OFFSET_0_TESS_MODE(uint32_t val
)
392 return ((val
) << CP_DRAW_INDX_OFFSET_0_TESS_MODE__SHIFT
) & CP_DRAW_INDX_OFFSET_0_TESS_MODE__MASK
;
395 #define REG_CP_DRAW_INDX_OFFSET_1 0x00000001
396 #define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK 0xffffffff
397 #define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT 0
398 static inline uint32_t CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES(uint32_t val
)
400 return ((val
) << CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT
) & CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK
;
403 #define REG_CP_DRAW_INDX_OFFSET_2 0x00000002
404 #define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK 0xffffffff
405 #define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT 0
406 static inline uint32_t CP_DRAW_INDX_OFFSET_2_NUM_INDICES(uint32_t val
)
408 return ((val
) << CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT
) & CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK
;
411 #define REG_CP_DRAW_INDX_OFFSET_3 0x00000003
413 #define REG_CP_DRAW_INDX_OFFSET_4 0x00000004
414 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK 0xffffffff
415 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT 0
416 static inline uint32_t CP_DRAW_INDX_OFFSET_4_INDX_BASE(uint32_t val
)
418 return ((val
) << CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT
) & CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK
;
421 #define REG_CP_DRAW_INDX_OFFSET_5 0x00000005
422 #define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK 0xffffffff
423 #define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT 0
424 static inline uint32_t CP_DRAW_INDX_OFFSET_5_INDX_SIZE(uint32_t val
)
426 return ((val
) << CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT
) & CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK
;
429 #define REG_CP_SET_DRAW_STATE_0 0x00000000
430 #define CP_SET_DRAW_STATE_0_COUNT__MASK 0x0000ffff
431 #define CP_SET_DRAW_STATE_0_COUNT__SHIFT 0
432 static inline uint32_t CP_SET_DRAW_STATE_0_COUNT(uint32_t val
)
434 return ((val
) << CP_SET_DRAW_STATE_0_COUNT__SHIFT
) & CP_SET_DRAW_STATE_0_COUNT__MASK
;
436 #define CP_SET_DRAW_STATE_0_DIRTY 0x00010000
437 #define CP_SET_DRAW_STATE_0_DISABLE 0x00020000
438 #define CP_SET_DRAW_STATE_0_DISABLE_ALL_GROUPS 0x00040000
439 #define CP_SET_DRAW_STATE_0_LOAD_IMMED 0x00080000
440 #define CP_SET_DRAW_STATE_0_GROUP_ID__MASK 0x1f000000
441 #define CP_SET_DRAW_STATE_0_GROUP_ID__SHIFT 24
442 static inline uint32_t CP_SET_DRAW_STATE_0_GROUP_ID(uint32_t val
)
444 return ((val
) << CP_SET_DRAW_STATE_0_GROUP_ID__SHIFT
) & CP_SET_DRAW_STATE_0_GROUP_ID__MASK
;
447 #define REG_CP_SET_DRAW_STATE_1 0x00000001
448 #define CP_SET_DRAW_STATE_1_ADDR__MASK 0xffffffff
449 #define CP_SET_DRAW_STATE_1_ADDR__SHIFT 0
450 static inline uint32_t CP_SET_DRAW_STATE_1_ADDR(uint32_t val
)
452 return ((val
) << CP_SET_DRAW_STATE_1_ADDR__SHIFT
) & CP_SET_DRAW_STATE_1_ADDR__MASK
;
455 #define REG_CP_SET_BIN_0 0x00000000
457 #define REG_CP_SET_BIN_1 0x00000001
458 #define CP_SET_BIN_1_X1__MASK 0x0000ffff
459 #define CP_SET_BIN_1_X1__SHIFT 0
460 static inline uint32_t CP_SET_BIN_1_X1(uint32_t val
)
462 return ((val
) << CP_SET_BIN_1_X1__SHIFT
) & CP_SET_BIN_1_X1__MASK
;
464 #define CP_SET_BIN_1_Y1__MASK 0xffff0000
465 #define CP_SET_BIN_1_Y1__SHIFT 16
466 static inline uint32_t CP_SET_BIN_1_Y1(uint32_t val
)
468 return ((val
) << CP_SET_BIN_1_Y1__SHIFT
) & CP_SET_BIN_1_Y1__MASK
;
471 #define REG_CP_SET_BIN_2 0x00000002
472 #define CP_SET_BIN_2_X2__MASK 0x0000ffff
473 #define CP_SET_BIN_2_X2__SHIFT 0
474 static inline uint32_t CP_SET_BIN_2_X2(uint32_t val
)
476 return ((val
) << CP_SET_BIN_2_X2__SHIFT
) & CP_SET_BIN_2_X2__MASK
;
478 #define CP_SET_BIN_2_Y2__MASK 0xffff0000
479 #define CP_SET_BIN_2_Y2__SHIFT 16
480 static inline uint32_t CP_SET_BIN_2_Y2(uint32_t val
)
482 return ((val
) << CP_SET_BIN_2_Y2__SHIFT
) & CP_SET_BIN_2_Y2__MASK
;
485 #define REG_CP_SET_BIN_DATA_0 0x00000000
486 #define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK 0xffffffff
487 #define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT 0
488 static inline uint32_t CP_SET_BIN_DATA_0_BIN_DATA_ADDR(uint32_t val
)
490 return ((val
) << CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT
) & CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK
;
493 #define REG_CP_SET_BIN_DATA_1 0x00000001
494 #define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK 0xffffffff
495 #define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT 0
496 static inline uint32_t CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS(uint32_t val
)
498 return ((val
) << CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT
) & CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK
;
502 #endif /* ADRENO_PM4_XML */