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[mesa.git] / src / gallium / drivers / freedreno / adreno_pm4.xml.h
1 #ifndef ADRENO_PM4_XML
2 #define ADRENO_PM4_XML
3
4 /* Autogenerated file, DO NOT EDIT manually!
5
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
9
10 The rules-ng-ng source files this header was generated from are:
11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2017-05-17 13:21:27)
12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
13 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 37162 bytes, from 2017-05-17 13:21:27)
14 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 13324 bytes, from 2017-05-17 13:21:27)
15 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 31866 bytes, from 2017-06-02 15:50:23)
16 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2017-05-17 13:21:27)
17 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 111898 bytes, from 2017-05-30 19:25:27)
18 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 142603 bytes, from 2017-06-06 17:02:32)
19 - /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2017-05-17 13:21:27)
20
21 Copyright (C) 2013-2017 by the following authors:
22 - Rob Clark <robdclark@gmail.com> (robclark)
23 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
24
25 Permission is hereby granted, free of charge, to any person obtaining
26 a copy of this software and associated documentation files (the
27 "Software"), to deal in the Software without restriction, including
28 without limitation the rights to use, copy, modify, merge, publish,
29 distribute, sublicense, and/or sell copies of the Software, and to
30 permit persons to whom the Software is furnished to do so, subject to
31 the following conditions:
32
33 The above copyright notice and this permission notice (including the
34 next paragraph) shall be included in all copies or substantial
35 portions of the Software.
36
37 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
38 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
39 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
40 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
41 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
42 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
43 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
44 */
45
46
47 enum vgt_event_type {
48 VS_DEALLOC = 0,
49 PS_DEALLOC = 1,
50 VS_DONE_TS = 2,
51 PS_DONE_TS = 3,
52 CACHE_FLUSH_TS = 4,
53 CONTEXT_DONE = 5,
54 CACHE_FLUSH = 6,
55 HLSQ_FLUSH = 7,
56 VIZQUERY_START = 7,
57 VIZQUERY_END = 8,
58 SC_WAIT_WC = 9,
59 RST_PIX_CNT = 13,
60 RST_VTX_CNT = 14,
61 TILE_FLUSH = 15,
62 STAT_EVENT = 16,
63 CACHE_FLUSH_AND_INV_TS_EVENT = 20,
64 ZPASS_DONE = 21,
65 CACHE_FLUSH_AND_INV_EVENT = 22,
66 PERFCOUNTER_START = 23,
67 PERFCOUNTER_STOP = 24,
68 VS_FETCH_DONE = 27,
69 FACENESS_FLUSH = 28,
70 FLUSH_SO_0 = 17,
71 FLUSH_SO_1 = 18,
72 FLUSH_SO_2 = 19,
73 FLUSH_SO_3 = 20,
74 UNK_19 = 25,
75 UNK_1C = 28,
76 UNK_1D = 29,
77 BLIT = 30,
78 UNK_25 = 37,
79 LRZ_FLUSH = 38,
80 UNK_2C = 44,
81 UNK_2D = 45,
82 };
83
84 enum pc_di_primtype {
85 DI_PT_NONE = 0,
86 DI_PT_POINTLIST_PSIZE = 1,
87 DI_PT_LINELIST = 2,
88 DI_PT_LINESTRIP = 3,
89 DI_PT_TRILIST = 4,
90 DI_PT_TRIFAN = 5,
91 DI_PT_TRISTRIP = 6,
92 DI_PT_LINELOOP = 7,
93 DI_PT_RECTLIST = 8,
94 DI_PT_POINTLIST = 9,
95 DI_PT_LINE_ADJ = 10,
96 DI_PT_LINESTRIP_ADJ = 11,
97 DI_PT_TRI_ADJ = 12,
98 DI_PT_TRISTRIP_ADJ = 13,
99 };
100
101 enum pc_di_src_sel {
102 DI_SRC_SEL_DMA = 0,
103 DI_SRC_SEL_IMMEDIATE = 1,
104 DI_SRC_SEL_AUTO_INDEX = 2,
105 DI_SRC_SEL_RESERVED = 3,
106 };
107
108 enum pc_di_index_size {
109 INDEX_SIZE_IGN = 0,
110 INDEX_SIZE_16_BIT = 0,
111 INDEX_SIZE_32_BIT = 1,
112 INDEX_SIZE_8_BIT = 2,
113 INDEX_SIZE_INVALID = 0,
114 };
115
116 enum pc_di_vis_cull_mode {
117 IGNORE_VISIBILITY = 0,
118 USE_VISIBILITY = 1,
119 };
120
121 enum adreno_pm4_packet_type {
122 CP_TYPE0_PKT = 0,
123 CP_TYPE1_PKT = 0x40000000,
124 CP_TYPE2_PKT = 0x80000000,
125 CP_TYPE3_PKT = 0xc0000000,
126 CP_TYPE4_PKT = 0x40000000,
127 CP_TYPE7_PKT = 0x70000000,
128 };
129
130 enum adreno_pm4_type3_packets {
131 CP_ME_INIT = 72,
132 CP_NOP = 16,
133 CP_PREEMPT_ENABLE = 28,
134 CP_PREEMPT_TOKEN = 30,
135 CP_INDIRECT_BUFFER = 63,
136 CP_INDIRECT_BUFFER_PFD = 55,
137 CP_WAIT_FOR_IDLE = 38,
138 CP_WAIT_REG_MEM = 60,
139 CP_WAIT_REG_EQ = 82,
140 CP_WAIT_REG_GTE = 83,
141 CP_WAIT_UNTIL_READ = 92,
142 CP_WAIT_IB_PFD_COMPLETE = 93,
143 CP_REG_RMW = 33,
144 CP_SET_BIN_DATA = 47,
145 CP_SET_BIN_DATA5 = 47,
146 CP_REG_TO_MEM = 62,
147 CP_MEM_WRITE = 61,
148 CP_MEM_WRITE_CNTR = 79,
149 CP_COND_EXEC = 68,
150 CP_COND_WRITE = 69,
151 CP_COND_WRITE5 = 69,
152 CP_EVENT_WRITE = 70,
153 CP_EVENT_WRITE_SHD = 88,
154 CP_EVENT_WRITE_CFL = 89,
155 CP_EVENT_WRITE_ZPD = 91,
156 CP_RUN_OPENCL = 49,
157 CP_DRAW_INDX = 34,
158 CP_DRAW_INDX_2 = 54,
159 CP_DRAW_INDX_BIN = 52,
160 CP_DRAW_INDX_2_BIN = 53,
161 CP_VIZ_QUERY = 35,
162 CP_SET_STATE = 37,
163 CP_SET_CONSTANT = 45,
164 CP_IM_LOAD = 39,
165 CP_IM_LOAD_IMMEDIATE = 43,
166 CP_LOAD_CONSTANT_CONTEXT = 46,
167 CP_INVALIDATE_STATE = 59,
168 CP_SET_SHADER_BASES = 74,
169 CP_SET_BIN_MASK = 80,
170 CP_SET_BIN_SELECT = 81,
171 CP_CONTEXT_UPDATE = 94,
172 CP_INTERRUPT = 64,
173 CP_IM_STORE = 44,
174 CP_SET_DRAW_INIT_FLAGS = 75,
175 CP_SET_PROTECTED_MODE = 95,
176 CP_BOOTSTRAP_UCODE = 111,
177 CP_LOAD_STATE = 48,
178 CP_LOAD_STATE4 = 48,
179 CP_COND_INDIRECT_BUFFER_PFE = 58,
180 CP_COND_INDIRECT_BUFFER_PFD = 50,
181 CP_INDIRECT_BUFFER_PFE = 63,
182 CP_SET_BIN = 76,
183 CP_TEST_TWO_MEMS = 113,
184 CP_REG_WR_NO_CTXT = 120,
185 CP_RECORD_PFP_TIMESTAMP = 17,
186 CP_SET_SECURE_MODE = 102,
187 CP_WAIT_FOR_ME = 19,
188 CP_SET_DRAW_STATE = 67,
189 CP_DRAW_INDX_OFFSET = 56,
190 CP_DRAW_INDIRECT = 40,
191 CP_DRAW_INDX_INDIRECT = 41,
192 CP_DRAW_AUTO = 36,
193 CP_UNKNOWN_19 = 25,
194 CP_UNKNOWN_1A = 26,
195 CP_UNKNOWN_4E = 78,
196 CP_WIDE_REG_WRITE = 116,
197 CP_SCRATCH_TO_REG = 77,
198 CP_REG_TO_SCRATCH = 74,
199 CP_WAIT_MEM_WRITES = 18,
200 CP_COND_REG_EXEC = 71,
201 CP_MEM_TO_REG = 66,
202 CP_EXEC_CS = 51,
203 CP_PERFCOUNTER_ACTION = 80,
204 CP_SMMU_TABLE_UPDATE = 83,
205 CP_CONTEXT_REG_BUNCH = 92,
206 CP_YIELD_ENABLE = 28,
207 CP_SKIP_IB2_ENABLE_GLOBAL = 29,
208 CP_SKIP_IB2_ENABLE_LOCAL = 35,
209 CP_SET_SUBDRAW_SIZE = 53,
210 CP_SET_VISIBILITY_OVERRIDE = 100,
211 CP_PREEMPT_ENABLE_GLOBAL = 105,
212 CP_PREEMPT_ENABLE_LOCAL = 106,
213 CP_CONTEXT_SWITCH_YIELD = 107,
214 CP_SET_RENDER_MODE = 108,
215 CP_COMPUTE_CHECKPOINT = 110,
216 CP_MEM_TO_MEM = 115,
217 CP_BLIT = 44,
218 CP_UNK_39 = 57,
219 IN_IB_PREFETCH_END = 23,
220 IN_SUBBLK_PREFETCH = 31,
221 IN_INSTR_PREFETCH = 32,
222 IN_INSTR_MATCH = 71,
223 IN_CONST_PREFETCH = 73,
224 IN_INCR_UPDT_STATE = 85,
225 IN_INCR_UPDT_CONST = 86,
226 IN_INCR_UPDT_INSTR = 87,
227 };
228
229 enum adreno_state_block {
230 SB_VERT_TEX = 0,
231 SB_VERT_MIPADDR = 1,
232 SB_FRAG_TEX = 2,
233 SB_FRAG_MIPADDR = 3,
234 SB_VERT_SHADER = 4,
235 SB_GEOM_SHADER = 5,
236 SB_FRAG_SHADER = 6,
237 SB_COMPUTE_SHADER = 7,
238 };
239
240 enum adreno_state_type {
241 ST_SHADER = 0,
242 ST_CONSTANTS = 1,
243 };
244
245 enum adreno_state_src {
246 SS_DIRECT = 0,
247 SS_INVALID_ALL_IC = 2,
248 SS_INVALID_PART_IC = 3,
249 SS_INDIRECT = 4,
250 SS_INDIRECT_TCM = 5,
251 SS_INDIRECT_STM = 6,
252 };
253
254 enum a4xx_state_block {
255 SB4_VS_TEX = 0,
256 SB4_HS_TEX = 1,
257 SB4_DS_TEX = 2,
258 SB4_GS_TEX = 3,
259 SB4_FS_TEX = 4,
260 SB4_CS_TEX = 5,
261 SB4_VS_SHADER = 8,
262 SB4_HS_SHADER = 9,
263 SB4_DS_SHADER = 10,
264 SB4_GS_SHADER = 11,
265 SB4_FS_SHADER = 12,
266 SB4_CS_SHADER = 13,
267 SB4_SSBO = 14,
268 SB4_CS_SSBO = 15,
269 };
270
271 enum a4xx_state_type {
272 ST4_SHADER = 0,
273 ST4_CONSTANTS = 1,
274 };
275
276 enum a4xx_state_src {
277 SS4_DIRECT = 0,
278 SS4_INDIRECT = 2,
279 };
280
281 enum a4xx_index_size {
282 INDEX4_SIZE_8_BIT = 0,
283 INDEX4_SIZE_16_BIT = 1,
284 INDEX4_SIZE_32_BIT = 2,
285 };
286
287 enum cp_cond_function {
288 WRITE_ALWAYS = 0,
289 WRITE_LT = 1,
290 WRITE_LE = 2,
291 WRITE_EQ = 3,
292 WRITE_NE = 4,
293 WRITE_GE = 5,
294 WRITE_GT = 6,
295 };
296
297 enum render_mode_cmd {
298 BYPASS = 1,
299 BINNING = 2,
300 GMEM = 3,
301 BLIT2D = 5,
302 BLIT2DSCALE = 7,
303 };
304
305 enum cp_blit_cmd {
306 BLIT_OP_FILL = 0,
307 BLIT_OP_COPY = 1,
308 BLIT_OP_SCALE = 3,
309 };
310
311 #define REG_CP_LOAD_STATE_0 0x00000000
312 #define CP_LOAD_STATE_0_DST_OFF__MASK 0x0000ffff
313 #define CP_LOAD_STATE_0_DST_OFF__SHIFT 0
314 static inline uint32_t CP_LOAD_STATE_0_DST_OFF(uint32_t val)
315 {
316 return ((val) << CP_LOAD_STATE_0_DST_OFF__SHIFT) & CP_LOAD_STATE_0_DST_OFF__MASK;
317 }
318 #define CP_LOAD_STATE_0_STATE_SRC__MASK 0x00070000
319 #define CP_LOAD_STATE_0_STATE_SRC__SHIFT 16
320 static inline uint32_t CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val)
321 {
322 return ((val) << CP_LOAD_STATE_0_STATE_SRC__SHIFT) & CP_LOAD_STATE_0_STATE_SRC__MASK;
323 }
324 #define CP_LOAD_STATE_0_STATE_BLOCK__MASK 0x00380000
325 #define CP_LOAD_STATE_0_STATE_BLOCK__SHIFT 19
326 static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val)
327 {
328 return ((val) << CP_LOAD_STATE_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE_0_STATE_BLOCK__MASK;
329 }
330 #define CP_LOAD_STATE_0_NUM_UNIT__MASK 0xffc00000
331 #define CP_LOAD_STATE_0_NUM_UNIT__SHIFT 22
332 static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val)
333 {
334 return ((val) << CP_LOAD_STATE_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE_0_NUM_UNIT__MASK;
335 }
336
337 #define REG_CP_LOAD_STATE_1 0x00000001
338 #define CP_LOAD_STATE_1_STATE_TYPE__MASK 0x00000003
339 #define CP_LOAD_STATE_1_STATE_TYPE__SHIFT 0
340 static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val)
341 {
342 return ((val) << CP_LOAD_STATE_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE_1_STATE_TYPE__MASK;
343 }
344 #define CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK 0xfffffffc
345 #define CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT 2
346 static inline uint32_t CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val)
347 {
348 assert(!(val & 0x3));
349 return ((val >> 2) << CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK;
350 }
351
352 #define REG_CP_LOAD_STATE4_0 0x00000000
353 #define CP_LOAD_STATE4_0_DST_OFF__MASK 0x0000ffff
354 #define CP_LOAD_STATE4_0_DST_OFF__SHIFT 0
355 static inline uint32_t CP_LOAD_STATE4_0_DST_OFF(uint32_t val)
356 {
357 return ((val) << CP_LOAD_STATE4_0_DST_OFF__SHIFT) & CP_LOAD_STATE4_0_DST_OFF__MASK;
358 }
359 #define CP_LOAD_STATE4_0_STATE_SRC__MASK 0x00030000
360 #define CP_LOAD_STATE4_0_STATE_SRC__SHIFT 16
361 static inline uint32_t CP_LOAD_STATE4_0_STATE_SRC(enum a4xx_state_src val)
362 {
363 return ((val) << CP_LOAD_STATE4_0_STATE_SRC__SHIFT) & CP_LOAD_STATE4_0_STATE_SRC__MASK;
364 }
365 #define CP_LOAD_STATE4_0_STATE_BLOCK__MASK 0x003c0000
366 #define CP_LOAD_STATE4_0_STATE_BLOCK__SHIFT 18
367 static inline uint32_t CP_LOAD_STATE4_0_STATE_BLOCK(enum a4xx_state_block val)
368 {
369 return ((val) << CP_LOAD_STATE4_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE4_0_STATE_BLOCK__MASK;
370 }
371 #define CP_LOAD_STATE4_0_NUM_UNIT__MASK 0xffc00000
372 #define CP_LOAD_STATE4_0_NUM_UNIT__SHIFT 22
373 static inline uint32_t CP_LOAD_STATE4_0_NUM_UNIT(uint32_t val)
374 {
375 return ((val) << CP_LOAD_STATE4_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE4_0_NUM_UNIT__MASK;
376 }
377
378 #define REG_CP_LOAD_STATE4_1 0x00000001
379 #define CP_LOAD_STATE4_1_STATE_TYPE__MASK 0x00000003
380 #define CP_LOAD_STATE4_1_STATE_TYPE__SHIFT 0
381 static inline uint32_t CP_LOAD_STATE4_1_STATE_TYPE(enum a4xx_state_type val)
382 {
383 return ((val) << CP_LOAD_STATE4_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE4_1_STATE_TYPE__MASK;
384 }
385 #define CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK 0xfffffffc
386 #define CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT 2
387 static inline uint32_t CP_LOAD_STATE4_1_EXT_SRC_ADDR(uint32_t val)
388 {
389 assert(!(val & 0x3));
390 return ((val >> 2) << CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK;
391 }
392
393 #define REG_CP_LOAD_STATE4_2 0x00000002
394 #define CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK 0xffffffff
395 #define CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT 0
396 static inline uint32_t CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(uint32_t val)
397 {
398 return ((val) << CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK;
399 }
400
401 #define REG_CP_DRAW_INDX_0 0x00000000
402 #define CP_DRAW_INDX_0_VIZ_QUERY__MASK 0xffffffff
403 #define CP_DRAW_INDX_0_VIZ_QUERY__SHIFT 0
404 static inline uint32_t CP_DRAW_INDX_0_VIZ_QUERY(uint32_t val)
405 {
406 return ((val) << CP_DRAW_INDX_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_0_VIZ_QUERY__MASK;
407 }
408
409 #define REG_CP_DRAW_INDX_1 0x00000001
410 #define CP_DRAW_INDX_1_PRIM_TYPE__MASK 0x0000003f
411 #define CP_DRAW_INDX_1_PRIM_TYPE__SHIFT 0
412 static inline uint32_t CP_DRAW_INDX_1_PRIM_TYPE(enum pc_di_primtype val)
413 {
414 return ((val) << CP_DRAW_INDX_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_1_PRIM_TYPE__MASK;
415 }
416 #define CP_DRAW_INDX_1_SOURCE_SELECT__MASK 0x000000c0
417 #define CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT 6
418 static inline uint32_t CP_DRAW_INDX_1_SOURCE_SELECT(enum pc_di_src_sel val)
419 {
420 return ((val) << CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_1_SOURCE_SELECT__MASK;
421 }
422 #define CP_DRAW_INDX_1_VIS_CULL__MASK 0x00000600
423 #define CP_DRAW_INDX_1_VIS_CULL__SHIFT 9
424 static inline uint32_t CP_DRAW_INDX_1_VIS_CULL(enum pc_di_vis_cull_mode val)
425 {
426 return ((val) << CP_DRAW_INDX_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_1_VIS_CULL__MASK;
427 }
428 #define CP_DRAW_INDX_1_INDEX_SIZE__MASK 0x00000800
429 #define CP_DRAW_INDX_1_INDEX_SIZE__SHIFT 11
430 static inline uint32_t CP_DRAW_INDX_1_INDEX_SIZE(enum pc_di_index_size val)
431 {
432 return ((val) << CP_DRAW_INDX_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_1_INDEX_SIZE__MASK;
433 }
434 #define CP_DRAW_INDX_1_NOT_EOP 0x00001000
435 #define CP_DRAW_INDX_1_SMALL_INDEX 0x00002000
436 #define CP_DRAW_INDX_1_PRE_DRAW_INITIATOR_ENABLE 0x00004000
437 #define CP_DRAW_INDX_1_NUM_INSTANCES__MASK 0xff000000
438 #define CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT 24
439 static inline uint32_t CP_DRAW_INDX_1_NUM_INSTANCES(uint32_t val)
440 {
441 return ((val) << CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_1_NUM_INSTANCES__MASK;
442 }
443
444 #define REG_CP_DRAW_INDX_2 0x00000002
445 #define CP_DRAW_INDX_2_NUM_INDICES__MASK 0xffffffff
446 #define CP_DRAW_INDX_2_NUM_INDICES__SHIFT 0
447 static inline uint32_t CP_DRAW_INDX_2_NUM_INDICES(uint32_t val)
448 {
449 return ((val) << CP_DRAW_INDX_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_NUM_INDICES__MASK;
450 }
451
452 #define REG_CP_DRAW_INDX_3 0x00000003
453 #define CP_DRAW_INDX_3_INDX_BASE__MASK 0xffffffff
454 #define CP_DRAW_INDX_3_INDX_BASE__SHIFT 0
455 static inline uint32_t CP_DRAW_INDX_3_INDX_BASE(uint32_t val)
456 {
457 return ((val) << CP_DRAW_INDX_3_INDX_BASE__SHIFT) & CP_DRAW_INDX_3_INDX_BASE__MASK;
458 }
459
460 #define REG_CP_DRAW_INDX_4 0x00000004
461 #define CP_DRAW_INDX_4_INDX_SIZE__MASK 0xffffffff
462 #define CP_DRAW_INDX_4_INDX_SIZE__SHIFT 0
463 static inline uint32_t CP_DRAW_INDX_4_INDX_SIZE(uint32_t val)
464 {
465 return ((val) << CP_DRAW_INDX_4_INDX_SIZE__SHIFT) & CP_DRAW_INDX_4_INDX_SIZE__MASK;
466 }
467
468 #define REG_CP_DRAW_INDX_2_0 0x00000000
469 #define CP_DRAW_INDX_2_0_VIZ_QUERY__MASK 0xffffffff
470 #define CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT 0
471 static inline uint32_t CP_DRAW_INDX_2_0_VIZ_QUERY(uint32_t val)
472 {
473 return ((val) << CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_2_0_VIZ_QUERY__MASK;
474 }
475
476 #define REG_CP_DRAW_INDX_2_1 0x00000001
477 #define CP_DRAW_INDX_2_1_PRIM_TYPE__MASK 0x0000003f
478 #define CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT 0
479 static inline uint32_t CP_DRAW_INDX_2_1_PRIM_TYPE(enum pc_di_primtype val)
480 {
481 return ((val) << CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_2_1_PRIM_TYPE__MASK;
482 }
483 #define CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK 0x000000c0
484 #define CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT 6
485 static inline uint32_t CP_DRAW_INDX_2_1_SOURCE_SELECT(enum pc_di_src_sel val)
486 {
487 return ((val) << CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK;
488 }
489 #define CP_DRAW_INDX_2_1_VIS_CULL__MASK 0x00000600
490 #define CP_DRAW_INDX_2_1_VIS_CULL__SHIFT 9
491 static inline uint32_t CP_DRAW_INDX_2_1_VIS_CULL(enum pc_di_vis_cull_mode val)
492 {
493 return ((val) << CP_DRAW_INDX_2_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_2_1_VIS_CULL__MASK;
494 }
495 #define CP_DRAW_INDX_2_1_INDEX_SIZE__MASK 0x00000800
496 #define CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT 11
497 static inline uint32_t CP_DRAW_INDX_2_1_INDEX_SIZE(enum pc_di_index_size val)
498 {
499 return ((val) << CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_2_1_INDEX_SIZE__MASK;
500 }
501 #define CP_DRAW_INDX_2_1_NOT_EOP 0x00001000
502 #define CP_DRAW_INDX_2_1_SMALL_INDEX 0x00002000
503 #define CP_DRAW_INDX_2_1_PRE_DRAW_INITIATOR_ENABLE 0x00004000
504 #define CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK 0xff000000
505 #define CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT 24
506 static inline uint32_t CP_DRAW_INDX_2_1_NUM_INSTANCES(uint32_t val)
507 {
508 return ((val) << CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK;
509 }
510
511 #define REG_CP_DRAW_INDX_2_2 0x00000002
512 #define CP_DRAW_INDX_2_2_NUM_INDICES__MASK 0xffffffff
513 #define CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT 0
514 static inline uint32_t CP_DRAW_INDX_2_2_NUM_INDICES(uint32_t val)
515 {
516 return ((val) << CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_2_NUM_INDICES__MASK;
517 }
518
519 #define REG_CP_DRAW_INDX_OFFSET_0 0x00000000
520 #define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK 0x0000003f
521 #define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT 0
522 static inline uint32_t CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(enum pc_di_primtype val)
523 {
524 return ((val) << CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK;
525 }
526 #define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK 0x000000c0
527 #define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT 6
528 static inline uint32_t CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel val)
529 {
530 return ((val) << CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK;
531 }
532 #define CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK 0x00000300
533 #define CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT 8
534 static inline uint32_t CP_DRAW_INDX_OFFSET_0_VIS_CULL(enum pc_di_vis_cull_mode val)
535 {
536 return ((val) << CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT) & CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK;
537 }
538 #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK 0x00000c00
539 #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT 10
540 static inline uint32_t CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum a4xx_index_size val)
541 {
542 return ((val) << CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK;
543 }
544 #define CP_DRAW_INDX_OFFSET_0_TESS_MODE__MASK 0x01f00000
545 #define CP_DRAW_INDX_OFFSET_0_TESS_MODE__SHIFT 20
546 static inline uint32_t CP_DRAW_INDX_OFFSET_0_TESS_MODE(uint32_t val)
547 {
548 return ((val) << CP_DRAW_INDX_OFFSET_0_TESS_MODE__SHIFT) & CP_DRAW_INDX_OFFSET_0_TESS_MODE__MASK;
549 }
550
551 #define REG_CP_DRAW_INDX_OFFSET_1 0x00000001
552 #define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK 0xffffffff
553 #define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT 0
554 static inline uint32_t CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES(uint32_t val)
555 {
556 return ((val) << CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK;
557 }
558
559 #define REG_CP_DRAW_INDX_OFFSET_2 0x00000002
560 #define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK 0xffffffff
561 #define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT 0
562 static inline uint32_t CP_DRAW_INDX_OFFSET_2_NUM_INDICES(uint32_t val)
563 {
564 return ((val) << CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK;
565 }
566
567 #define REG_CP_DRAW_INDX_OFFSET_3 0x00000003
568
569 #define REG_CP_DRAW_INDX_OFFSET_4 0x00000004
570 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK 0xffffffff
571 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT 0
572 static inline uint32_t CP_DRAW_INDX_OFFSET_4_INDX_BASE(uint32_t val)
573 {
574 return ((val) << CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT) & CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK;
575 }
576
577 #define REG_CP_DRAW_INDX_OFFSET_5 0x00000005
578 #define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK 0xffffffff
579 #define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT 0
580 static inline uint32_t CP_DRAW_INDX_OFFSET_5_INDX_SIZE(uint32_t val)
581 {
582 return ((val) << CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK;
583 }
584
585 static inline uint32_t REG_CP_SET_DRAW_STATE_(uint32_t i0) { return 0x00000000 + 0x3*i0; }
586
587 static inline uint32_t REG_CP_SET_DRAW_STATE__0(uint32_t i0) { return 0x00000000 + 0x3*i0; }
588 #define CP_SET_DRAW_STATE__0_COUNT__MASK 0x0000ffff
589 #define CP_SET_DRAW_STATE__0_COUNT__SHIFT 0
590 static inline uint32_t CP_SET_DRAW_STATE__0_COUNT(uint32_t val)
591 {
592 return ((val) << CP_SET_DRAW_STATE__0_COUNT__SHIFT) & CP_SET_DRAW_STATE__0_COUNT__MASK;
593 }
594 #define CP_SET_DRAW_STATE__0_DIRTY 0x00010000
595 #define CP_SET_DRAW_STATE__0_DISABLE 0x00020000
596 #define CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS 0x00040000
597 #define CP_SET_DRAW_STATE__0_LOAD_IMMED 0x00080000
598 #define CP_SET_DRAW_STATE__0_GROUP_ID__MASK 0x1f000000
599 #define CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT 24
600 static inline uint32_t CP_SET_DRAW_STATE__0_GROUP_ID(uint32_t val)
601 {
602 return ((val) << CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT) & CP_SET_DRAW_STATE__0_GROUP_ID__MASK;
603 }
604
605 static inline uint32_t REG_CP_SET_DRAW_STATE__1(uint32_t i0) { return 0x00000001 + 0x3*i0; }
606 #define CP_SET_DRAW_STATE__1_ADDR_LO__MASK 0xffffffff
607 #define CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT 0
608 static inline uint32_t CP_SET_DRAW_STATE__1_ADDR_LO(uint32_t val)
609 {
610 return ((val) << CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT) & CP_SET_DRAW_STATE__1_ADDR_LO__MASK;
611 }
612
613 static inline uint32_t REG_CP_SET_DRAW_STATE__2(uint32_t i0) { return 0x00000002 + 0x3*i0; }
614 #define CP_SET_DRAW_STATE__2_ADDR_HI__MASK 0xffffffff
615 #define CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT 0
616 static inline uint32_t CP_SET_DRAW_STATE__2_ADDR_HI(uint32_t val)
617 {
618 return ((val) << CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT) & CP_SET_DRAW_STATE__2_ADDR_HI__MASK;
619 }
620
621 #define REG_CP_SET_BIN_0 0x00000000
622
623 #define REG_CP_SET_BIN_1 0x00000001
624 #define CP_SET_BIN_1_X1__MASK 0x0000ffff
625 #define CP_SET_BIN_1_X1__SHIFT 0
626 static inline uint32_t CP_SET_BIN_1_X1(uint32_t val)
627 {
628 return ((val) << CP_SET_BIN_1_X1__SHIFT) & CP_SET_BIN_1_X1__MASK;
629 }
630 #define CP_SET_BIN_1_Y1__MASK 0xffff0000
631 #define CP_SET_BIN_1_Y1__SHIFT 16
632 static inline uint32_t CP_SET_BIN_1_Y1(uint32_t val)
633 {
634 return ((val) << CP_SET_BIN_1_Y1__SHIFT) & CP_SET_BIN_1_Y1__MASK;
635 }
636
637 #define REG_CP_SET_BIN_2 0x00000002
638 #define CP_SET_BIN_2_X2__MASK 0x0000ffff
639 #define CP_SET_BIN_2_X2__SHIFT 0
640 static inline uint32_t CP_SET_BIN_2_X2(uint32_t val)
641 {
642 return ((val) << CP_SET_BIN_2_X2__SHIFT) & CP_SET_BIN_2_X2__MASK;
643 }
644 #define CP_SET_BIN_2_Y2__MASK 0xffff0000
645 #define CP_SET_BIN_2_Y2__SHIFT 16
646 static inline uint32_t CP_SET_BIN_2_Y2(uint32_t val)
647 {
648 return ((val) << CP_SET_BIN_2_Y2__SHIFT) & CP_SET_BIN_2_Y2__MASK;
649 }
650
651 #define REG_CP_SET_BIN_DATA_0 0x00000000
652 #define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK 0xffffffff
653 #define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT 0
654 static inline uint32_t CP_SET_BIN_DATA_0_BIN_DATA_ADDR(uint32_t val)
655 {
656 return ((val) << CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT) & CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK;
657 }
658
659 #define REG_CP_SET_BIN_DATA_1 0x00000001
660 #define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK 0xffffffff
661 #define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT 0
662 static inline uint32_t CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS(uint32_t val)
663 {
664 return ((val) << CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT) & CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK;
665 }
666
667 #define REG_CP_SET_BIN_DATA5_0 0x00000000
668 #define CP_SET_BIN_DATA5_0_VSC_SIZE__MASK 0x003f0000
669 #define CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT 16
670 static inline uint32_t CP_SET_BIN_DATA5_0_VSC_SIZE(uint32_t val)
671 {
672 return ((val) << CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT) & CP_SET_BIN_DATA5_0_VSC_SIZE__MASK;
673 }
674 #define CP_SET_BIN_DATA5_0_VSC_N__MASK 0x07c00000
675 #define CP_SET_BIN_DATA5_0_VSC_N__SHIFT 22
676 static inline uint32_t CP_SET_BIN_DATA5_0_VSC_N(uint32_t val)
677 {
678 return ((val) << CP_SET_BIN_DATA5_0_VSC_N__SHIFT) & CP_SET_BIN_DATA5_0_VSC_N__MASK;
679 }
680
681 #define REG_CP_SET_BIN_DATA5_1 0x00000001
682 #define CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK 0xffffffff
683 #define CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT 0
684 static inline uint32_t CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO(uint32_t val)
685 {
686 return ((val) << CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT) & CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK;
687 }
688
689 #define REG_CP_SET_BIN_DATA5_2 0x00000002
690 #define CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK 0xffffffff
691 #define CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT 0
692 static inline uint32_t CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI(uint32_t val)
693 {
694 return ((val) << CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT) & CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK;
695 }
696
697 #define REG_CP_SET_BIN_DATA5_3 0x00000003
698 #define CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK 0xffffffff
699 #define CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT 0
700 static inline uint32_t CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO(uint32_t val)
701 {
702 return ((val) << CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT) & CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK;
703 }
704
705 #define REG_CP_SET_BIN_DATA5_4 0x00000004
706 #define CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK 0xffffffff
707 #define CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT 0
708 static inline uint32_t CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI(uint32_t val)
709 {
710 return ((val) << CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT) & CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK;
711 }
712
713 #define REG_CP_REG_TO_MEM_0 0x00000000
714 #define CP_REG_TO_MEM_0_REG__MASK 0x0000ffff
715 #define CP_REG_TO_MEM_0_REG__SHIFT 0
716 static inline uint32_t CP_REG_TO_MEM_0_REG(uint32_t val)
717 {
718 return ((val) << CP_REG_TO_MEM_0_REG__SHIFT) & CP_REG_TO_MEM_0_REG__MASK;
719 }
720 #define CP_REG_TO_MEM_0_CNT__MASK 0x3ff80000
721 #define CP_REG_TO_MEM_0_CNT__SHIFT 19
722 static inline uint32_t CP_REG_TO_MEM_0_CNT(uint32_t val)
723 {
724 return ((val) << CP_REG_TO_MEM_0_CNT__SHIFT) & CP_REG_TO_MEM_0_CNT__MASK;
725 }
726 #define CP_REG_TO_MEM_0_64B 0x40000000
727 #define CP_REG_TO_MEM_0_ACCUMULATE 0x80000000
728
729 #define REG_CP_REG_TO_MEM_1 0x00000001
730 #define CP_REG_TO_MEM_1_DEST__MASK 0xffffffff
731 #define CP_REG_TO_MEM_1_DEST__SHIFT 0
732 static inline uint32_t CP_REG_TO_MEM_1_DEST(uint32_t val)
733 {
734 return ((val) << CP_REG_TO_MEM_1_DEST__SHIFT) & CP_REG_TO_MEM_1_DEST__MASK;
735 }
736
737 #define REG_CP_MEM_TO_MEM_0 0x00000000
738 #define CP_MEM_TO_MEM_0_NEG_A 0x00000001
739 #define CP_MEM_TO_MEM_0_NEG_B 0x00000002
740 #define CP_MEM_TO_MEM_0_NEG_C 0x00000004
741 #define CP_MEM_TO_MEM_0_DOUBLE 0x20000000
742
743 #define REG_CP_COND_WRITE_0 0x00000000
744 #define CP_COND_WRITE_0_FUNCTION__MASK 0x00000007
745 #define CP_COND_WRITE_0_FUNCTION__SHIFT 0
746 static inline uint32_t CP_COND_WRITE_0_FUNCTION(enum cp_cond_function val)
747 {
748 return ((val) << CP_COND_WRITE_0_FUNCTION__SHIFT) & CP_COND_WRITE_0_FUNCTION__MASK;
749 }
750 #define CP_COND_WRITE_0_POLL_MEMORY 0x00000010
751 #define CP_COND_WRITE_0_WRITE_MEMORY 0x00000100
752
753 #define REG_CP_COND_WRITE_1 0x00000001
754 #define CP_COND_WRITE_1_POLL_ADDR__MASK 0xffffffff
755 #define CP_COND_WRITE_1_POLL_ADDR__SHIFT 0
756 static inline uint32_t CP_COND_WRITE_1_POLL_ADDR(uint32_t val)
757 {
758 return ((val) << CP_COND_WRITE_1_POLL_ADDR__SHIFT) & CP_COND_WRITE_1_POLL_ADDR__MASK;
759 }
760
761 #define REG_CP_COND_WRITE_2 0x00000002
762 #define CP_COND_WRITE_2_REF__MASK 0xffffffff
763 #define CP_COND_WRITE_2_REF__SHIFT 0
764 static inline uint32_t CP_COND_WRITE_2_REF(uint32_t val)
765 {
766 return ((val) << CP_COND_WRITE_2_REF__SHIFT) & CP_COND_WRITE_2_REF__MASK;
767 }
768
769 #define REG_CP_COND_WRITE_3 0x00000003
770 #define CP_COND_WRITE_3_MASK__MASK 0xffffffff
771 #define CP_COND_WRITE_3_MASK__SHIFT 0
772 static inline uint32_t CP_COND_WRITE_3_MASK(uint32_t val)
773 {
774 return ((val) << CP_COND_WRITE_3_MASK__SHIFT) & CP_COND_WRITE_3_MASK__MASK;
775 }
776
777 #define REG_CP_COND_WRITE_4 0x00000004
778 #define CP_COND_WRITE_4_WRITE_ADDR__MASK 0xffffffff
779 #define CP_COND_WRITE_4_WRITE_ADDR__SHIFT 0
780 static inline uint32_t CP_COND_WRITE_4_WRITE_ADDR(uint32_t val)
781 {
782 return ((val) << CP_COND_WRITE_4_WRITE_ADDR__SHIFT) & CP_COND_WRITE_4_WRITE_ADDR__MASK;
783 }
784
785 #define REG_CP_COND_WRITE_5 0x00000005
786 #define CP_COND_WRITE_5_WRITE_DATA__MASK 0xffffffff
787 #define CP_COND_WRITE_5_WRITE_DATA__SHIFT 0
788 static inline uint32_t CP_COND_WRITE_5_WRITE_DATA(uint32_t val)
789 {
790 return ((val) << CP_COND_WRITE_5_WRITE_DATA__SHIFT) & CP_COND_WRITE_5_WRITE_DATA__MASK;
791 }
792
793 #define REG_CP_COND_WRITE5_0 0x00000000
794 #define CP_COND_WRITE5_0_FUNCTION__MASK 0x00000007
795 #define CP_COND_WRITE5_0_FUNCTION__SHIFT 0
796 static inline uint32_t CP_COND_WRITE5_0_FUNCTION(enum cp_cond_function val)
797 {
798 return ((val) << CP_COND_WRITE5_0_FUNCTION__SHIFT) & CP_COND_WRITE5_0_FUNCTION__MASK;
799 }
800 #define CP_COND_WRITE5_0_POLL_MEMORY 0x00000010
801 #define CP_COND_WRITE5_0_WRITE_MEMORY 0x00000100
802
803 #define REG_CP_COND_WRITE5_1 0x00000001
804 #define CP_COND_WRITE5_1_POLL_ADDR_LO__MASK 0xffffffff
805 #define CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT 0
806 static inline uint32_t CP_COND_WRITE5_1_POLL_ADDR_LO(uint32_t val)
807 {
808 return ((val) << CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT) & CP_COND_WRITE5_1_POLL_ADDR_LO__MASK;
809 }
810
811 #define REG_CP_COND_WRITE5_2 0x00000002
812 #define CP_COND_WRITE5_2_POLL_ADDR_HI__MASK 0xffffffff
813 #define CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT 0
814 static inline uint32_t CP_COND_WRITE5_2_POLL_ADDR_HI(uint32_t val)
815 {
816 return ((val) << CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT) & CP_COND_WRITE5_2_POLL_ADDR_HI__MASK;
817 }
818
819 #define REG_CP_COND_WRITE5_3 0x00000003
820 #define CP_COND_WRITE5_3_REF__MASK 0xffffffff
821 #define CP_COND_WRITE5_3_REF__SHIFT 0
822 static inline uint32_t CP_COND_WRITE5_3_REF(uint32_t val)
823 {
824 return ((val) << CP_COND_WRITE5_3_REF__SHIFT) & CP_COND_WRITE5_3_REF__MASK;
825 }
826
827 #define REG_CP_COND_WRITE5_4 0x00000004
828 #define CP_COND_WRITE5_4_MASK__MASK 0xffffffff
829 #define CP_COND_WRITE5_4_MASK__SHIFT 0
830 static inline uint32_t CP_COND_WRITE5_4_MASK(uint32_t val)
831 {
832 return ((val) << CP_COND_WRITE5_4_MASK__SHIFT) & CP_COND_WRITE5_4_MASK__MASK;
833 }
834
835 #define REG_CP_COND_WRITE5_5 0x00000005
836 #define CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK 0xffffffff
837 #define CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT 0
838 static inline uint32_t CP_COND_WRITE5_5_WRITE_ADDR_LO(uint32_t val)
839 {
840 return ((val) << CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT) & CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK;
841 }
842
843 #define REG_CP_COND_WRITE5_6 0x00000006
844 #define CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK 0xffffffff
845 #define CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT 0
846 static inline uint32_t CP_COND_WRITE5_6_WRITE_ADDR_HI(uint32_t val)
847 {
848 return ((val) << CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT) & CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK;
849 }
850
851 #define REG_CP_COND_WRITE5_7 0x00000007
852 #define CP_COND_WRITE5_7_WRITE_DATA__MASK 0xffffffff
853 #define CP_COND_WRITE5_7_WRITE_DATA__SHIFT 0
854 static inline uint32_t CP_COND_WRITE5_7_WRITE_DATA(uint32_t val)
855 {
856 return ((val) << CP_COND_WRITE5_7_WRITE_DATA__SHIFT) & CP_COND_WRITE5_7_WRITE_DATA__MASK;
857 }
858
859 #define REG_CP_DISPATCH_COMPUTE_0 0x00000000
860
861 #define REG_CP_DISPATCH_COMPUTE_1 0x00000001
862 #define CP_DISPATCH_COMPUTE_1_X__MASK 0xffffffff
863 #define CP_DISPATCH_COMPUTE_1_X__SHIFT 0
864 static inline uint32_t CP_DISPATCH_COMPUTE_1_X(uint32_t val)
865 {
866 return ((val) << CP_DISPATCH_COMPUTE_1_X__SHIFT) & CP_DISPATCH_COMPUTE_1_X__MASK;
867 }
868
869 #define REG_CP_DISPATCH_COMPUTE_2 0x00000002
870 #define CP_DISPATCH_COMPUTE_2_Y__MASK 0xffffffff
871 #define CP_DISPATCH_COMPUTE_2_Y__SHIFT 0
872 static inline uint32_t CP_DISPATCH_COMPUTE_2_Y(uint32_t val)
873 {
874 return ((val) << CP_DISPATCH_COMPUTE_2_Y__SHIFT) & CP_DISPATCH_COMPUTE_2_Y__MASK;
875 }
876
877 #define REG_CP_DISPATCH_COMPUTE_3 0x00000003
878 #define CP_DISPATCH_COMPUTE_3_Z__MASK 0xffffffff
879 #define CP_DISPATCH_COMPUTE_3_Z__SHIFT 0
880 static inline uint32_t CP_DISPATCH_COMPUTE_3_Z(uint32_t val)
881 {
882 return ((val) << CP_DISPATCH_COMPUTE_3_Z__SHIFT) & CP_DISPATCH_COMPUTE_3_Z__MASK;
883 }
884
885 #define REG_CP_SET_RENDER_MODE_0 0x00000000
886 #define CP_SET_RENDER_MODE_0_MODE__MASK 0x000001ff
887 #define CP_SET_RENDER_MODE_0_MODE__SHIFT 0
888 static inline uint32_t CP_SET_RENDER_MODE_0_MODE(enum render_mode_cmd val)
889 {
890 return ((val) << CP_SET_RENDER_MODE_0_MODE__SHIFT) & CP_SET_RENDER_MODE_0_MODE__MASK;
891 }
892
893 #define REG_CP_SET_RENDER_MODE_1 0x00000001
894 #define CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK 0xffffffff
895 #define CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT 0
896 static inline uint32_t CP_SET_RENDER_MODE_1_ADDR_0_LO(uint32_t val)
897 {
898 return ((val) << CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT) & CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK;
899 }
900
901 #define REG_CP_SET_RENDER_MODE_2 0x00000002
902 #define CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK 0xffffffff
903 #define CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT 0
904 static inline uint32_t CP_SET_RENDER_MODE_2_ADDR_0_HI(uint32_t val)
905 {
906 return ((val) << CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT) & CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK;
907 }
908
909 #define REG_CP_SET_RENDER_MODE_3 0x00000003
910 #define CP_SET_RENDER_MODE_3_VSC_ENABLE 0x00000008
911 #define CP_SET_RENDER_MODE_3_GMEM_ENABLE 0x00000010
912
913 #define REG_CP_SET_RENDER_MODE_4 0x00000004
914
915 #define REG_CP_SET_RENDER_MODE_5 0x00000005
916 #define CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK 0xffffffff
917 #define CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT 0
918 static inline uint32_t CP_SET_RENDER_MODE_5_ADDR_1_LEN(uint32_t val)
919 {
920 return ((val) << CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT) & CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK;
921 }
922
923 #define REG_CP_SET_RENDER_MODE_6 0x00000006
924 #define CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK 0xffffffff
925 #define CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT 0
926 static inline uint32_t CP_SET_RENDER_MODE_6_ADDR_1_LO(uint32_t val)
927 {
928 return ((val) << CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT) & CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK;
929 }
930
931 #define REG_CP_SET_RENDER_MODE_7 0x00000007
932 #define CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK 0xffffffff
933 #define CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT 0
934 static inline uint32_t CP_SET_RENDER_MODE_7_ADDR_1_HI(uint32_t val)
935 {
936 return ((val) << CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT) & CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK;
937 }
938
939 #define REG_CP_COMPUTE_CHECKPOINT_0 0x00000000
940 #define CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MASK 0xffffffff
941 #define CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT 0
942 static inline uint32_t CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO(uint32_t val)
943 {
944 return ((val) << CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT) & CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MASK;
945 }
946
947 #define REG_CP_COMPUTE_CHECKPOINT_1 0x00000001
948 #define CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MASK 0xffffffff
949 #define CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT 0
950 static inline uint32_t CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI(uint32_t val)
951 {
952 return ((val) << CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT) & CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MASK;
953 }
954
955 #define REG_CP_COMPUTE_CHECKPOINT_2 0x00000002
956
957 #define REG_CP_COMPUTE_CHECKPOINT_3 0x00000003
958
959 #define REG_CP_COMPUTE_CHECKPOINT_4 0x00000004
960 #define CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__MASK 0xffffffff
961 #define CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__SHIFT 0
962 static inline uint32_t CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN(uint32_t val)
963 {
964 return ((val) << CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__SHIFT) & CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__MASK;
965 }
966
967 #define REG_CP_COMPUTE_CHECKPOINT_5 0x00000005
968 #define CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK 0xffffffff
969 #define CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT 0
970 static inline uint32_t CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO(uint32_t val)
971 {
972 return ((val) << CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT) & CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK;
973 }
974
975 #define REG_CP_COMPUTE_CHECKPOINT_6 0x00000006
976 #define CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MASK 0xffffffff
977 #define CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT 0
978 static inline uint32_t CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI(uint32_t val)
979 {
980 return ((val) << CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT) & CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MASK;
981 }
982
983 #define REG_CP_PERFCOUNTER_ACTION_0 0x00000000
984
985 #define REG_CP_PERFCOUNTER_ACTION_1 0x00000001
986 #define CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK 0xffffffff
987 #define CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT 0
988 static inline uint32_t CP_PERFCOUNTER_ACTION_1_ADDR_0_LO(uint32_t val)
989 {
990 return ((val) << CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT) & CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK;
991 }
992
993 #define REG_CP_PERFCOUNTER_ACTION_2 0x00000002
994 #define CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK 0xffffffff
995 #define CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT 0
996 static inline uint32_t CP_PERFCOUNTER_ACTION_2_ADDR_0_HI(uint32_t val)
997 {
998 return ((val) << CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT) & CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK;
999 }
1000
1001 #define REG_CP_EVENT_WRITE_0 0x00000000
1002 #define CP_EVENT_WRITE_0_EVENT__MASK 0x000000ff
1003 #define CP_EVENT_WRITE_0_EVENT__SHIFT 0
1004 static inline uint32_t CP_EVENT_WRITE_0_EVENT(enum vgt_event_type val)
1005 {
1006 return ((val) << CP_EVENT_WRITE_0_EVENT__SHIFT) & CP_EVENT_WRITE_0_EVENT__MASK;
1007 }
1008 #define CP_EVENT_WRITE_0_TIMESTAMP 0x40000000
1009
1010 #define REG_CP_EVENT_WRITE_1 0x00000001
1011 #define CP_EVENT_WRITE_1_ADDR_0_LO__MASK 0xffffffff
1012 #define CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT 0
1013 static inline uint32_t CP_EVENT_WRITE_1_ADDR_0_LO(uint32_t val)
1014 {
1015 return ((val) << CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT) & CP_EVENT_WRITE_1_ADDR_0_LO__MASK;
1016 }
1017
1018 #define REG_CP_EVENT_WRITE_2 0x00000002
1019 #define CP_EVENT_WRITE_2_ADDR_0_HI__MASK 0xffffffff
1020 #define CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT 0
1021 static inline uint32_t CP_EVENT_WRITE_2_ADDR_0_HI(uint32_t val)
1022 {
1023 return ((val) << CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT) & CP_EVENT_WRITE_2_ADDR_0_HI__MASK;
1024 }
1025
1026 #define REG_CP_EVENT_WRITE_3 0x00000003
1027
1028 #define REG_CP_BLIT_0 0x00000000
1029 #define CP_BLIT_0_OP__MASK 0x0000000f
1030 #define CP_BLIT_0_OP__SHIFT 0
1031 static inline uint32_t CP_BLIT_0_OP(enum cp_blit_cmd val)
1032 {
1033 return ((val) << CP_BLIT_0_OP__SHIFT) & CP_BLIT_0_OP__MASK;
1034 }
1035
1036 #define REG_CP_BLIT_1 0x00000001
1037 #define CP_BLIT_1_SRC_X1__MASK 0x0000ffff
1038 #define CP_BLIT_1_SRC_X1__SHIFT 0
1039 static inline uint32_t CP_BLIT_1_SRC_X1(uint32_t val)
1040 {
1041 return ((val) << CP_BLIT_1_SRC_X1__SHIFT) & CP_BLIT_1_SRC_X1__MASK;
1042 }
1043 #define CP_BLIT_1_SRC_Y1__MASK 0xffff0000
1044 #define CP_BLIT_1_SRC_Y1__SHIFT 16
1045 static inline uint32_t CP_BLIT_1_SRC_Y1(uint32_t val)
1046 {
1047 return ((val) << CP_BLIT_1_SRC_Y1__SHIFT) & CP_BLIT_1_SRC_Y1__MASK;
1048 }
1049
1050 #define REG_CP_BLIT_2 0x00000002
1051 #define CP_BLIT_2_SRC_X2__MASK 0x0000ffff
1052 #define CP_BLIT_2_SRC_X2__SHIFT 0
1053 static inline uint32_t CP_BLIT_2_SRC_X2(uint32_t val)
1054 {
1055 return ((val) << CP_BLIT_2_SRC_X2__SHIFT) & CP_BLIT_2_SRC_X2__MASK;
1056 }
1057 #define CP_BLIT_2_SRC_Y2__MASK 0xffff0000
1058 #define CP_BLIT_2_SRC_Y2__SHIFT 16
1059 static inline uint32_t CP_BLIT_2_SRC_Y2(uint32_t val)
1060 {
1061 return ((val) << CP_BLIT_2_SRC_Y2__SHIFT) & CP_BLIT_2_SRC_Y2__MASK;
1062 }
1063
1064 #define REG_CP_BLIT_3 0x00000003
1065 #define CP_BLIT_3_DST_X1__MASK 0x0000ffff
1066 #define CP_BLIT_3_DST_X1__SHIFT 0
1067 static inline uint32_t CP_BLIT_3_DST_X1(uint32_t val)
1068 {
1069 return ((val) << CP_BLIT_3_DST_X1__SHIFT) & CP_BLIT_3_DST_X1__MASK;
1070 }
1071 #define CP_BLIT_3_DST_Y1__MASK 0xffff0000
1072 #define CP_BLIT_3_DST_Y1__SHIFT 16
1073 static inline uint32_t CP_BLIT_3_DST_Y1(uint32_t val)
1074 {
1075 return ((val) << CP_BLIT_3_DST_Y1__SHIFT) & CP_BLIT_3_DST_Y1__MASK;
1076 }
1077
1078 #define REG_CP_BLIT_4 0x00000004
1079 #define CP_BLIT_4_DST_X2__MASK 0x0000ffff
1080 #define CP_BLIT_4_DST_X2__SHIFT 0
1081 static inline uint32_t CP_BLIT_4_DST_X2(uint32_t val)
1082 {
1083 return ((val) << CP_BLIT_4_DST_X2__SHIFT) & CP_BLIT_4_DST_X2__MASK;
1084 }
1085 #define CP_BLIT_4_DST_Y2__MASK 0xffff0000
1086 #define CP_BLIT_4_DST_Y2__SHIFT 16
1087 static inline uint32_t CP_BLIT_4_DST_Y2(uint32_t val)
1088 {
1089 return ((val) << CP_BLIT_4_DST_Y2__SHIFT) & CP_BLIT_4_DST_Y2__MASK;
1090 }
1091
1092 #define REG_CP_EXEC_CS_0 0x00000000
1093
1094 #define REG_CP_EXEC_CS_1 0x00000001
1095 #define CP_EXEC_CS_1_NGROUPS_X__MASK 0xffffffff
1096 #define CP_EXEC_CS_1_NGROUPS_X__SHIFT 0
1097 static inline uint32_t CP_EXEC_CS_1_NGROUPS_X(uint32_t val)
1098 {
1099 return ((val) << CP_EXEC_CS_1_NGROUPS_X__SHIFT) & CP_EXEC_CS_1_NGROUPS_X__MASK;
1100 }
1101
1102 #define REG_CP_EXEC_CS_2 0x00000002
1103 #define CP_EXEC_CS_2_NGROUPS_Y__MASK 0xffffffff
1104 #define CP_EXEC_CS_2_NGROUPS_Y__SHIFT 0
1105 static inline uint32_t CP_EXEC_CS_2_NGROUPS_Y(uint32_t val)
1106 {
1107 return ((val) << CP_EXEC_CS_2_NGROUPS_Y__SHIFT) & CP_EXEC_CS_2_NGROUPS_Y__MASK;
1108 }
1109
1110 #define REG_CP_EXEC_CS_3 0x00000003
1111 #define CP_EXEC_CS_3_NGROUPS_Z__MASK 0xffffffff
1112 #define CP_EXEC_CS_3_NGROUPS_Z__SHIFT 0
1113 static inline uint32_t CP_EXEC_CS_3_NGROUPS_Z(uint32_t val)
1114 {
1115 return ((val) << CP_EXEC_CS_3_NGROUPS_Z__SHIFT) & CP_EXEC_CS_3_NGROUPS_Z__MASK;
1116 }
1117
1118
1119 #endif /* ADRENO_PM4_XML */