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freedreno: update generated headers
[mesa.git] / src / gallium / drivers / freedreno / adreno_pm4.xml.h
1 #ifndef ADRENO_PM4_XML
2 #define ADRENO_PM4_XML
3
4 /* Autogenerated file, DO NOT EDIT manually!
5
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
9
10 The rules-ng-ng source files this header was generated from are:
11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 431 bytes, from 2017-05-17 13:21:27)
12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2017-05-17 13:21:27)
13 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 37162 bytes, from 2017-05-17 13:21:27)
14 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 13324 bytes, from 2017-05-17 13:21:27)
15 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 32453 bytes, from 2017-11-10 18:31:55)
16 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2017-05-17 13:21:27)
17 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 111898 bytes, from 2017-06-06 18:23:59)
18 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 143114 bytes, from 2017-11-10 18:31:55)
19 - /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2017-05-17 13:21:27)
20
21 Copyright (C) 2013-2017 by the following authors:
22 - Rob Clark <robdclark@gmail.com> (robclark)
23 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
24
25 Permission is hereby granted, free of charge, to any person obtaining
26 a copy of this software and associated documentation files (the
27 "Software"), to deal in the Software without restriction, including
28 without limitation the rights to use, copy, modify, merge, publish,
29 distribute, sublicense, and/or sell copies of the Software, and to
30 permit persons to whom the Software is furnished to do so, subject to
31 the following conditions:
32
33 The above copyright notice and this permission notice (including the
34 next paragraph) shall be included in all copies or substantial
35 portions of the Software.
36
37 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
38 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
39 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
40 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
41 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
42 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
43 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
44 */
45
46
47 enum vgt_event_type {
48 VS_DEALLOC = 0,
49 PS_DEALLOC = 1,
50 VS_DONE_TS = 2,
51 PS_DONE_TS = 3,
52 CACHE_FLUSH_TS = 4,
53 CONTEXT_DONE = 5,
54 CACHE_FLUSH = 6,
55 HLSQ_FLUSH = 7,
56 VIZQUERY_START = 7,
57 VIZQUERY_END = 8,
58 SC_WAIT_WC = 9,
59 RST_PIX_CNT = 13,
60 RST_VTX_CNT = 14,
61 TILE_FLUSH = 15,
62 STAT_EVENT = 16,
63 CACHE_FLUSH_AND_INV_TS_EVENT = 20,
64 ZPASS_DONE = 21,
65 CACHE_FLUSH_AND_INV_EVENT = 22,
66 PERFCOUNTER_START = 23,
67 PERFCOUNTER_STOP = 24,
68 VS_FETCH_DONE = 27,
69 FACENESS_FLUSH = 28,
70 FLUSH_SO_0 = 17,
71 FLUSH_SO_1 = 18,
72 FLUSH_SO_2 = 19,
73 FLUSH_SO_3 = 20,
74 UNK_19 = 25,
75 UNK_1C = 28,
76 UNK_1D = 29,
77 BLIT = 30,
78 UNK_25 = 37,
79 LRZ_FLUSH = 38,
80 UNK_2C = 44,
81 UNK_2D = 45,
82 };
83
84 enum pc_di_primtype {
85 DI_PT_NONE = 0,
86 DI_PT_POINTLIST_PSIZE = 1,
87 DI_PT_LINELIST = 2,
88 DI_PT_LINESTRIP = 3,
89 DI_PT_TRILIST = 4,
90 DI_PT_TRIFAN = 5,
91 DI_PT_TRISTRIP = 6,
92 DI_PT_LINELOOP = 7,
93 DI_PT_RECTLIST = 8,
94 DI_PT_POINTLIST = 9,
95 DI_PT_LINE_ADJ = 10,
96 DI_PT_LINESTRIP_ADJ = 11,
97 DI_PT_TRI_ADJ = 12,
98 DI_PT_TRISTRIP_ADJ = 13,
99 };
100
101 enum pc_di_src_sel {
102 DI_SRC_SEL_DMA = 0,
103 DI_SRC_SEL_IMMEDIATE = 1,
104 DI_SRC_SEL_AUTO_INDEX = 2,
105 DI_SRC_SEL_RESERVED = 3,
106 };
107
108 enum pc_di_index_size {
109 INDEX_SIZE_IGN = 0,
110 INDEX_SIZE_16_BIT = 0,
111 INDEX_SIZE_32_BIT = 1,
112 INDEX_SIZE_8_BIT = 2,
113 INDEX_SIZE_INVALID = 0,
114 };
115
116 enum pc_di_vis_cull_mode {
117 IGNORE_VISIBILITY = 0,
118 USE_VISIBILITY = 1,
119 };
120
121 enum adreno_pm4_packet_type {
122 CP_TYPE0_PKT = 0,
123 CP_TYPE1_PKT = 0x40000000,
124 CP_TYPE2_PKT = 0x80000000,
125 CP_TYPE3_PKT = 0xc0000000,
126 CP_TYPE4_PKT = 0x40000000,
127 CP_TYPE7_PKT = 0x70000000,
128 };
129
130 enum adreno_pm4_type3_packets {
131 CP_ME_INIT = 72,
132 CP_NOP = 16,
133 CP_PREEMPT_ENABLE = 28,
134 CP_PREEMPT_TOKEN = 30,
135 CP_INDIRECT_BUFFER = 63,
136 CP_INDIRECT_BUFFER_PFD = 55,
137 CP_WAIT_FOR_IDLE = 38,
138 CP_WAIT_REG_MEM = 60,
139 CP_WAIT_REG_EQ = 82,
140 CP_WAIT_REG_GTE = 83,
141 CP_WAIT_UNTIL_READ = 92,
142 CP_WAIT_IB_PFD_COMPLETE = 93,
143 CP_REG_RMW = 33,
144 CP_SET_BIN_DATA = 47,
145 CP_SET_BIN_DATA5 = 47,
146 CP_REG_TO_MEM = 62,
147 CP_MEM_WRITE = 61,
148 CP_MEM_WRITE_CNTR = 79,
149 CP_COND_EXEC = 68,
150 CP_COND_WRITE = 69,
151 CP_COND_WRITE5 = 69,
152 CP_EVENT_WRITE = 70,
153 CP_EVENT_WRITE_SHD = 88,
154 CP_EVENT_WRITE_CFL = 89,
155 CP_EVENT_WRITE_ZPD = 91,
156 CP_RUN_OPENCL = 49,
157 CP_DRAW_INDX = 34,
158 CP_DRAW_INDX_2 = 54,
159 CP_DRAW_INDX_BIN = 52,
160 CP_DRAW_INDX_2_BIN = 53,
161 CP_VIZ_QUERY = 35,
162 CP_SET_STATE = 37,
163 CP_SET_CONSTANT = 45,
164 CP_IM_LOAD = 39,
165 CP_IM_LOAD_IMMEDIATE = 43,
166 CP_LOAD_CONSTANT_CONTEXT = 46,
167 CP_INVALIDATE_STATE = 59,
168 CP_SET_SHADER_BASES = 74,
169 CP_SET_BIN_MASK = 80,
170 CP_SET_BIN_SELECT = 81,
171 CP_CONTEXT_UPDATE = 94,
172 CP_INTERRUPT = 64,
173 CP_IM_STORE = 44,
174 CP_SET_DRAW_INIT_FLAGS = 75,
175 CP_SET_PROTECTED_MODE = 95,
176 CP_BOOTSTRAP_UCODE = 111,
177 CP_LOAD_STATE = 48,
178 CP_LOAD_STATE4 = 48,
179 CP_COND_INDIRECT_BUFFER_PFE = 58,
180 CP_COND_INDIRECT_BUFFER_PFD = 50,
181 CP_INDIRECT_BUFFER_PFE = 63,
182 CP_SET_BIN = 76,
183 CP_TEST_TWO_MEMS = 113,
184 CP_REG_WR_NO_CTXT = 120,
185 CP_RECORD_PFP_TIMESTAMP = 17,
186 CP_SET_SECURE_MODE = 102,
187 CP_WAIT_FOR_ME = 19,
188 CP_SET_DRAW_STATE = 67,
189 CP_DRAW_INDX_OFFSET = 56,
190 CP_DRAW_INDIRECT = 40,
191 CP_DRAW_INDX_INDIRECT = 41,
192 CP_DRAW_AUTO = 36,
193 CP_UNKNOWN_19 = 25,
194 CP_UNKNOWN_1A = 26,
195 CP_UNKNOWN_4E = 78,
196 CP_WIDE_REG_WRITE = 116,
197 CP_SCRATCH_TO_REG = 77,
198 CP_REG_TO_SCRATCH = 74,
199 CP_WAIT_MEM_WRITES = 18,
200 CP_COND_REG_EXEC = 71,
201 CP_MEM_TO_REG = 66,
202 CP_EXEC_CS_INDIRECT = 65,
203 CP_EXEC_CS = 51,
204 CP_PERFCOUNTER_ACTION = 80,
205 CP_SMMU_TABLE_UPDATE = 83,
206 CP_CONTEXT_REG_BUNCH = 92,
207 CP_YIELD_ENABLE = 28,
208 CP_SKIP_IB2_ENABLE_GLOBAL = 29,
209 CP_SKIP_IB2_ENABLE_LOCAL = 35,
210 CP_SET_SUBDRAW_SIZE = 53,
211 CP_SET_VISIBILITY_OVERRIDE = 100,
212 CP_PREEMPT_ENABLE_GLOBAL = 105,
213 CP_PREEMPT_ENABLE_LOCAL = 106,
214 CP_CONTEXT_SWITCH_YIELD = 107,
215 CP_SET_RENDER_MODE = 108,
216 CP_COMPUTE_CHECKPOINT = 110,
217 CP_MEM_TO_MEM = 115,
218 CP_BLIT = 44,
219 CP_UNK_39 = 57,
220 IN_IB_PREFETCH_END = 23,
221 IN_SUBBLK_PREFETCH = 31,
222 IN_INSTR_PREFETCH = 32,
223 IN_INSTR_MATCH = 71,
224 IN_CONST_PREFETCH = 73,
225 IN_INCR_UPDT_STATE = 85,
226 IN_INCR_UPDT_CONST = 86,
227 IN_INCR_UPDT_INSTR = 87,
228 };
229
230 enum adreno_state_block {
231 SB_VERT_TEX = 0,
232 SB_VERT_MIPADDR = 1,
233 SB_FRAG_TEX = 2,
234 SB_FRAG_MIPADDR = 3,
235 SB_VERT_SHADER = 4,
236 SB_GEOM_SHADER = 5,
237 SB_FRAG_SHADER = 6,
238 SB_COMPUTE_SHADER = 7,
239 };
240
241 enum adreno_state_type {
242 ST_SHADER = 0,
243 ST_CONSTANTS = 1,
244 };
245
246 enum adreno_state_src {
247 SS_DIRECT = 0,
248 SS_INVALID_ALL_IC = 2,
249 SS_INVALID_PART_IC = 3,
250 SS_INDIRECT = 4,
251 SS_INDIRECT_TCM = 5,
252 SS_INDIRECT_STM = 6,
253 };
254
255 enum a4xx_state_block {
256 SB4_VS_TEX = 0,
257 SB4_HS_TEX = 1,
258 SB4_DS_TEX = 2,
259 SB4_GS_TEX = 3,
260 SB4_FS_TEX = 4,
261 SB4_CS_TEX = 5,
262 SB4_VS_SHADER = 8,
263 SB4_HS_SHADER = 9,
264 SB4_DS_SHADER = 10,
265 SB4_GS_SHADER = 11,
266 SB4_FS_SHADER = 12,
267 SB4_CS_SHADER = 13,
268 SB4_SSBO = 14,
269 SB4_CS_SSBO = 15,
270 };
271
272 enum a4xx_state_type {
273 ST4_SHADER = 0,
274 ST4_CONSTANTS = 1,
275 };
276
277 enum a4xx_state_src {
278 SS4_DIRECT = 0,
279 SS4_INDIRECT = 2,
280 };
281
282 enum a4xx_index_size {
283 INDEX4_SIZE_8_BIT = 0,
284 INDEX4_SIZE_16_BIT = 1,
285 INDEX4_SIZE_32_BIT = 2,
286 };
287
288 enum cp_cond_function {
289 WRITE_ALWAYS = 0,
290 WRITE_LT = 1,
291 WRITE_LE = 2,
292 WRITE_EQ = 3,
293 WRITE_NE = 4,
294 WRITE_GE = 5,
295 WRITE_GT = 6,
296 };
297
298 enum render_mode_cmd {
299 BYPASS = 1,
300 BINNING = 2,
301 GMEM = 3,
302 BLIT2D = 5,
303 BLIT2DSCALE = 7,
304 };
305
306 enum cp_blit_cmd {
307 BLIT_OP_FILL = 0,
308 BLIT_OP_COPY = 1,
309 BLIT_OP_SCALE = 3,
310 };
311
312 #define REG_CP_LOAD_STATE_0 0x00000000
313 #define CP_LOAD_STATE_0_DST_OFF__MASK 0x0000ffff
314 #define CP_LOAD_STATE_0_DST_OFF__SHIFT 0
315 static inline uint32_t CP_LOAD_STATE_0_DST_OFF(uint32_t val)
316 {
317 return ((val) << CP_LOAD_STATE_0_DST_OFF__SHIFT) & CP_LOAD_STATE_0_DST_OFF__MASK;
318 }
319 #define CP_LOAD_STATE_0_STATE_SRC__MASK 0x00070000
320 #define CP_LOAD_STATE_0_STATE_SRC__SHIFT 16
321 static inline uint32_t CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val)
322 {
323 return ((val) << CP_LOAD_STATE_0_STATE_SRC__SHIFT) & CP_LOAD_STATE_0_STATE_SRC__MASK;
324 }
325 #define CP_LOAD_STATE_0_STATE_BLOCK__MASK 0x00380000
326 #define CP_LOAD_STATE_0_STATE_BLOCK__SHIFT 19
327 static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val)
328 {
329 return ((val) << CP_LOAD_STATE_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE_0_STATE_BLOCK__MASK;
330 }
331 #define CP_LOAD_STATE_0_NUM_UNIT__MASK 0xffc00000
332 #define CP_LOAD_STATE_0_NUM_UNIT__SHIFT 22
333 static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val)
334 {
335 return ((val) << CP_LOAD_STATE_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE_0_NUM_UNIT__MASK;
336 }
337
338 #define REG_CP_LOAD_STATE_1 0x00000001
339 #define CP_LOAD_STATE_1_STATE_TYPE__MASK 0x00000003
340 #define CP_LOAD_STATE_1_STATE_TYPE__SHIFT 0
341 static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val)
342 {
343 return ((val) << CP_LOAD_STATE_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE_1_STATE_TYPE__MASK;
344 }
345 #define CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK 0xfffffffc
346 #define CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT 2
347 static inline uint32_t CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val)
348 {
349 assert(!(val & 0x3));
350 return ((val >> 2) << CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK;
351 }
352
353 #define REG_CP_LOAD_STATE4_0 0x00000000
354 #define CP_LOAD_STATE4_0_DST_OFF__MASK 0x0000ffff
355 #define CP_LOAD_STATE4_0_DST_OFF__SHIFT 0
356 static inline uint32_t CP_LOAD_STATE4_0_DST_OFF(uint32_t val)
357 {
358 return ((val) << CP_LOAD_STATE4_0_DST_OFF__SHIFT) & CP_LOAD_STATE4_0_DST_OFF__MASK;
359 }
360 #define CP_LOAD_STATE4_0_STATE_SRC__MASK 0x00030000
361 #define CP_LOAD_STATE4_0_STATE_SRC__SHIFT 16
362 static inline uint32_t CP_LOAD_STATE4_0_STATE_SRC(enum a4xx_state_src val)
363 {
364 return ((val) << CP_LOAD_STATE4_0_STATE_SRC__SHIFT) & CP_LOAD_STATE4_0_STATE_SRC__MASK;
365 }
366 #define CP_LOAD_STATE4_0_STATE_BLOCK__MASK 0x003c0000
367 #define CP_LOAD_STATE4_0_STATE_BLOCK__SHIFT 18
368 static inline uint32_t CP_LOAD_STATE4_0_STATE_BLOCK(enum a4xx_state_block val)
369 {
370 return ((val) << CP_LOAD_STATE4_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE4_0_STATE_BLOCK__MASK;
371 }
372 #define CP_LOAD_STATE4_0_NUM_UNIT__MASK 0xffc00000
373 #define CP_LOAD_STATE4_0_NUM_UNIT__SHIFT 22
374 static inline uint32_t CP_LOAD_STATE4_0_NUM_UNIT(uint32_t val)
375 {
376 return ((val) << CP_LOAD_STATE4_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE4_0_NUM_UNIT__MASK;
377 }
378
379 #define REG_CP_LOAD_STATE4_1 0x00000001
380 #define CP_LOAD_STATE4_1_STATE_TYPE__MASK 0x00000003
381 #define CP_LOAD_STATE4_1_STATE_TYPE__SHIFT 0
382 static inline uint32_t CP_LOAD_STATE4_1_STATE_TYPE(enum a4xx_state_type val)
383 {
384 return ((val) << CP_LOAD_STATE4_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE4_1_STATE_TYPE__MASK;
385 }
386 #define CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK 0xfffffffc
387 #define CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT 2
388 static inline uint32_t CP_LOAD_STATE4_1_EXT_SRC_ADDR(uint32_t val)
389 {
390 assert(!(val & 0x3));
391 return ((val >> 2) << CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK;
392 }
393
394 #define REG_CP_LOAD_STATE4_2 0x00000002
395 #define CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK 0xffffffff
396 #define CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT 0
397 static inline uint32_t CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(uint32_t val)
398 {
399 return ((val) << CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK;
400 }
401
402 #define REG_CP_DRAW_INDX_0 0x00000000
403 #define CP_DRAW_INDX_0_VIZ_QUERY__MASK 0xffffffff
404 #define CP_DRAW_INDX_0_VIZ_QUERY__SHIFT 0
405 static inline uint32_t CP_DRAW_INDX_0_VIZ_QUERY(uint32_t val)
406 {
407 return ((val) << CP_DRAW_INDX_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_0_VIZ_QUERY__MASK;
408 }
409
410 #define REG_CP_DRAW_INDX_1 0x00000001
411 #define CP_DRAW_INDX_1_PRIM_TYPE__MASK 0x0000003f
412 #define CP_DRAW_INDX_1_PRIM_TYPE__SHIFT 0
413 static inline uint32_t CP_DRAW_INDX_1_PRIM_TYPE(enum pc_di_primtype val)
414 {
415 return ((val) << CP_DRAW_INDX_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_1_PRIM_TYPE__MASK;
416 }
417 #define CP_DRAW_INDX_1_SOURCE_SELECT__MASK 0x000000c0
418 #define CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT 6
419 static inline uint32_t CP_DRAW_INDX_1_SOURCE_SELECT(enum pc_di_src_sel val)
420 {
421 return ((val) << CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_1_SOURCE_SELECT__MASK;
422 }
423 #define CP_DRAW_INDX_1_VIS_CULL__MASK 0x00000600
424 #define CP_DRAW_INDX_1_VIS_CULL__SHIFT 9
425 static inline uint32_t CP_DRAW_INDX_1_VIS_CULL(enum pc_di_vis_cull_mode val)
426 {
427 return ((val) << CP_DRAW_INDX_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_1_VIS_CULL__MASK;
428 }
429 #define CP_DRAW_INDX_1_INDEX_SIZE__MASK 0x00000800
430 #define CP_DRAW_INDX_1_INDEX_SIZE__SHIFT 11
431 static inline uint32_t CP_DRAW_INDX_1_INDEX_SIZE(enum pc_di_index_size val)
432 {
433 return ((val) << CP_DRAW_INDX_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_1_INDEX_SIZE__MASK;
434 }
435 #define CP_DRAW_INDX_1_NOT_EOP 0x00001000
436 #define CP_DRAW_INDX_1_SMALL_INDEX 0x00002000
437 #define CP_DRAW_INDX_1_PRE_DRAW_INITIATOR_ENABLE 0x00004000
438 #define CP_DRAW_INDX_1_NUM_INSTANCES__MASK 0xff000000
439 #define CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT 24
440 static inline uint32_t CP_DRAW_INDX_1_NUM_INSTANCES(uint32_t val)
441 {
442 return ((val) << CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_1_NUM_INSTANCES__MASK;
443 }
444
445 #define REG_CP_DRAW_INDX_2 0x00000002
446 #define CP_DRAW_INDX_2_NUM_INDICES__MASK 0xffffffff
447 #define CP_DRAW_INDX_2_NUM_INDICES__SHIFT 0
448 static inline uint32_t CP_DRAW_INDX_2_NUM_INDICES(uint32_t val)
449 {
450 return ((val) << CP_DRAW_INDX_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_NUM_INDICES__MASK;
451 }
452
453 #define REG_CP_DRAW_INDX_3 0x00000003
454 #define CP_DRAW_INDX_3_INDX_BASE__MASK 0xffffffff
455 #define CP_DRAW_INDX_3_INDX_BASE__SHIFT 0
456 static inline uint32_t CP_DRAW_INDX_3_INDX_BASE(uint32_t val)
457 {
458 return ((val) << CP_DRAW_INDX_3_INDX_BASE__SHIFT) & CP_DRAW_INDX_3_INDX_BASE__MASK;
459 }
460
461 #define REG_CP_DRAW_INDX_4 0x00000004
462 #define CP_DRAW_INDX_4_INDX_SIZE__MASK 0xffffffff
463 #define CP_DRAW_INDX_4_INDX_SIZE__SHIFT 0
464 static inline uint32_t CP_DRAW_INDX_4_INDX_SIZE(uint32_t val)
465 {
466 return ((val) << CP_DRAW_INDX_4_INDX_SIZE__SHIFT) & CP_DRAW_INDX_4_INDX_SIZE__MASK;
467 }
468
469 #define REG_CP_DRAW_INDX_2_0 0x00000000
470 #define CP_DRAW_INDX_2_0_VIZ_QUERY__MASK 0xffffffff
471 #define CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT 0
472 static inline uint32_t CP_DRAW_INDX_2_0_VIZ_QUERY(uint32_t val)
473 {
474 return ((val) << CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_2_0_VIZ_QUERY__MASK;
475 }
476
477 #define REG_CP_DRAW_INDX_2_1 0x00000001
478 #define CP_DRAW_INDX_2_1_PRIM_TYPE__MASK 0x0000003f
479 #define CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT 0
480 static inline uint32_t CP_DRAW_INDX_2_1_PRIM_TYPE(enum pc_di_primtype val)
481 {
482 return ((val) << CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_2_1_PRIM_TYPE__MASK;
483 }
484 #define CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK 0x000000c0
485 #define CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT 6
486 static inline uint32_t CP_DRAW_INDX_2_1_SOURCE_SELECT(enum pc_di_src_sel val)
487 {
488 return ((val) << CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK;
489 }
490 #define CP_DRAW_INDX_2_1_VIS_CULL__MASK 0x00000600
491 #define CP_DRAW_INDX_2_1_VIS_CULL__SHIFT 9
492 static inline uint32_t CP_DRAW_INDX_2_1_VIS_CULL(enum pc_di_vis_cull_mode val)
493 {
494 return ((val) << CP_DRAW_INDX_2_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_2_1_VIS_CULL__MASK;
495 }
496 #define CP_DRAW_INDX_2_1_INDEX_SIZE__MASK 0x00000800
497 #define CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT 11
498 static inline uint32_t CP_DRAW_INDX_2_1_INDEX_SIZE(enum pc_di_index_size val)
499 {
500 return ((val) << CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_2_1_INDEX_SIZE__MASK;
501 }
502 #define CP_DRAW_INDX_2_1_NOT_EOP 0x00001000
503 #define CP_DRAW_INDX_2_1_SMALL_INDEX 0x00002000
504 #define CP_DRAW_INDX_2_1_PRE_DRAW_INITIATOR_ENABLE 0x00004000
505 #define CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK 0xff000000
506 #define CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT 24
507 static inline uint32_t CP_DRAW_INDX_2_1_NUM_INSTANCES(uint32_t val)
508 {
509 return ((val) << CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK;
510 }
511
512 #define REG_CP_DRAW_INDX_2_2 0x00000002
513 #define CP_DRAW_INDX_2_2_NUM_INDICES__MASK 0xffffffff
514 #define CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT 0
515 static inline uint32_t CP_DRAW_INDX_2_2_NUM_INDICES(uint32_t val)
516 {
517 return ((val) << CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_2_NUM_INDICES__MASK;
518 }
519
520 #define REG_CP_DRAW_INDX_OFFSET_0 0x00000000
521 #define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK 0x0000003f
522 #define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT 0
523 static inline uint32_t CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(enum pc_di_primtype val)
524 {
525 return ((val) << CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK;
526 }
527 #define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK 0x000000c0
528 #define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT 6
529 static inline uint32_t CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel val)
530 {
531 return ((val) << CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK;
532 }
533 #define CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK 0x00000300
534 #define CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT 8
535 static inline uint32_t CP_DRAW_INDX_OFFSET_0_VIS_CULL(enum pc_di_vis_cull_mode val)
536 {
537 return ((val) << CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT) & CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK;
538 }
539 #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK 0x00000c00
540 #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT 10
541 static inline uint32_t CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum a4xx_index_size val)
542 {
543 return ((val) << CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK;
544 }
545 #define CP_DRAW_INDX_OFFSET_0_TESS_MODE__MASK 0x01f00000
546 #define CP_DRAW_INDX_OFFSET_0_TESS_MODE__SHIFT 20
547 static inline uint32_t CP_DRAW_INDX_OFFSET_0_TESS_MODE(uint32_t val)
548 {
549 return ((val) << CP_DRAW_INDX_OFFSET_0_TESS_MODE__SHIFT) & CP_DRAW_INDX_OFFSET_0_TESS_MODE__MASK;
550 }
551
552 #define REG_CP_DRAW_INDX_OFFSET_1 0x00000001
553 #define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK 0xffffffff
554 #define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT 0
555 static inline uint32_t CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES(uint32_t val)
556 {
557 return ((val) << CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK;
558 }
559
560 #define REG_CP_DRAW_INDX_OFFSET_2 0x00000002
561 #define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK 0xffffffff
562 #define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT 0
563 static inline uint32_t CP_DRAW_INDX_OFFSET_2_NUM_INDICES(uint32_t val)
564 {
565 return ((val) << CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK;
566 }
567
568 #define REG_CP_DRAW_INDX_OFFSET_3 0x00000003
569
570 #define REG_CP_DRAW_INDX_OFFSET_4 0x00000004
571 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK 0xffffffff
572 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT 0
573 static inline uint32_t CP_DRAW_INDX_OFFSET_4_INDX_BASE(uint32_t val)
574 {
575 return ((val) << CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT) & CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK;
576 }
577
578 #define REG_CP_DRAW_INDX_OFFSET_5 0x00000005
579 #define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK 0xffffffff
580 #define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT 0
581 static inline uint32_t CP_DRAW_INDX_OFFSET_5_INDX_SIZE(uint32_t val)
582 {
583 return ((val) << CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK;
584 }
585
586 static inline uint32_t REG_CP_SET_DRAW_STATE_(uint32_t i0) { return 0x00000000 + 0x3*i0; }
587
588 static inline uint32_t REG_CP_SET_DRAW_STATE__0(uint32_t i0) { return 0x00000000 + 0x3*i0; }
589 #define CP_SET_DRAW_STATE__0_COUNT__MASK 0x0000ffff
590 #define CP_SET_DRAW_STATE__0_COUNT__SHIFT 0
591 static inline uint32_t CP_SET_DRAW_STATE__0_COUNT(uint32_t val)
592 {
593 return ((val) << CP_SET_DRAW_STATE__0_COUNT__SHIFT) & CP_SET_DRAW_STATE__0_COUNT__MASK;
594 }
595 #define CP_SET_DRAW_STATE__0_DIRTY 0x00010000
596 #define CP_SET_DRAW_STATE__0_DISABLE 0x00020000
597 #define CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS 0x00040000
598 #define CP_SET_DRAW_STATE__0_LOAD_IMMED 0x00080000
599 #define CP_SET_DRAW_STATE__0_GROUP_ID__MASK 0x1f000000
600 #define CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT 24
601 static inline uint32_t CP_SET_DRAW_STATE__0_GROUP_ID(uint32_t val)
602 {
603 return ((val) << CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT) & CP_SET_DRAW_STATE__0_GROUP_ID__MASK;
604 }
605
606 static inline uint32_t REG_CP_SET_DRAW_STATE__1(uint32_t i0) { return 0x00000001 + 0x3*i0; }
607 #define CP_SET_DRAW_STATE__1_ADDR_LO__MASK 0xffffffff
608 #define CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT 0
609 static inline uint32_t CP_SET_DRAW_STATE__1_ADDR_LO(uint32_t val)
610 {
611 return ((val) << CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT) & CP_SET_DRAW_STATE__1_ADDR_LO__MASK;
612 }
613
614 static inline uint32_t REG_CP_SET_DRAW_STATE__2(uint32_t i0) { return 0x00000002 + 0x3*i0; }
615 #define CP_SET_DRAW_STATE__2_ADDR_HI__MASK 0xffffffff
616 #define CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT 0
617 static inline uint32_t CP_SET_DRAW_STATE__2_ADDR_HI(uint32_t val)
618 {
619 return ((val) << CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT) & CP_SET_DRAW_STATE__2_ADDR_HI__MASK;
620 }
621
622 #define REG_CP_SET_BIN_0 0x00000000
623
624 #define REG_CP_SET_BIN_1 0x00000001
625 #define CP_SET_BIN_1_X1__MASK 0x0000ffff
626 #define CP_SET_BIN_1_X1__SHIFT 0
627 static inline uint32_t CP_SET_BIN_1_X1(uint32_t val)
628 {
629 return ((val) << CP_SET_BIN_1_X1__SHIFT) & CP_SET_BIN_1_X1__MASK;
630 }
631 #define CP_SET_BIN_1_Y1__MASK 0xffff0000
632 #define CP_SET_BIN_1_Y1__SHIFT 16
633 static inline uint32_t CP_SET_BIN_1_Y1(uint32_t val)
634 {
635 return ((val) << CP_SET_BIN_1_Y1__SHIFT) & CP_SET_BIN_1_Y1__MASK;
636 }
637
638 #define REG_CP_SET_BIN_2 0x00000002
639 #define CP_SET_BIN_2_X2__MASK 0x0000ffff
640 #define CP_SET_BIN_2_X2__SHIFT 0
641 static inline uint32_t CP_SET_BIN_2_X2(uint32_t val)
642 {
643 return ((val) << CP_SET_BIN_2_X2__SHIFT) & CP_SET_BIN_2_X2__MASK;
644 }
645 #define CP_SET_BIN_2_Y2__MASK 0xffff0000
646 #define CP_SET_BIN_2_Y2__SHIFT 16
647 static inline uint32_t CP_SET_BIN_2_Y2(uint32_t val)
648 {
649 return ((val) << CP_SET_BIN_2_Y2__SHIFT) & CP_SET_BIN_2_Y2__MASK;
650 }
651
652 #define REG_CP_SET_BIN_DATA_0 0x00000000
653 #define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK 0xffffffff
654 #define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT 0
655 static inline uint32_t CP_SET_BIN_DATA_0_BIN_DATA_ADDR(uint32_t val)
656 {
657 return ((val) << CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT) & CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK;
658 }
659
660 #define REG_CP_SET_BIN_DATA_1 0x00000001
661 #define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK 0xffffffff
662 #define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT 0
663 static inline uint32_t CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS(uint32_t val)
664 {
665 return ((val) << CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT) & CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK;
666 }
667
668 #define REG_CP_SET_BIN_DATA5_0 0x00000000
669 #define CP_SET_BIN_DATA5_0_VSC_SIZE__MASK 0x003f0000
670 #define CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT 16
671 static inline uint32_t CP_SET_BIN_DATA5_0_VSC_SIZE(uint32_t val)
672 {
673 return ((val) << CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT) & CP_SET_BIN_DATA5_0_VSC_SIZE__MASK;
674 }
675 #define CP_SET_BIN_DATA5_0_VSC_N__MASK 0x07c00000
676 #define CP_SET_BIN_DATA5_0_VSC_N__SHIFT 22
677 static inline uint32_t CP_SET_BIN_DATA5_0_VSC_N(uint32_t val)
678 {
679 return ((val) << CP_SET_BIN_DATA5_0_VSC_N__SHIFT) & CP_SET_BIN_DATA5_0_VSC_N__MASK;
680 }
681
682 #define REG_CP_SET_BIN_DATA5_1 0x00000001
683 #define CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK 0xffffffff
684 #define CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT 0
685 static inline uint32_t CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO(uint32_t val)
686 {
687 return ((val) << CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT) & CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK;
688 }
689
690 #define REG_CP_SET_BIN_DATA5_2 0x00000002
691 #define CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK 0xffffffff
692 #define CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT 0
693 static inline uint32_t CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI(uint32_t val)
694 {
695 return ((val) << CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT) & CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK;
696 }
697
698 #define REG_CP_SET_BIN_DATA5_3 0x00000003
699 #define CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK 0xffffffff
700 #define CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT 0
701 static inline uint32_t CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO(uint32_t val)
702 {
703 return ((val) << CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT) & CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK;
704 }
705
706 #define REG_CP_SET_BIN_DATA5_4 0x00000004
707 #define CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK 0xffffffff
708 #define CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT 0
709 static inline uint32_t CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI(uint32_t val)
710 {
711 return ((val) << CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT) & CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK;
712 }
713
714 #define REG_CP_REG_TO_MEM_0 0x00000000
715 #define CP_REG_TO_MEM_0_REG__MASK 0x0000ffff
716 #define CP_REG_TO_MEM_0_REG__SHIFT 0
717 static inline uint32_t CP_REG_TO_MEM_0_REG(uint32_t val)
718 {
719 return ((val) << CP_REG_TO_MEM_0_REG__SHIFT) & CP_REG_TO_MEM_0_REG__MASK;
720 }
721 #define CP_REG_TO_MEM_0_CNT__MASK 0x3ff80000
722 #define CP_REG_TO_MEM_0_CNT__SHIFT 19
723 static inline uint32_t CP_REG_TO_MEM_0_CNT(uint32_t val)
724 {
725 return ((val) << CP_REG_TO_MEM_0_CNT__SHIFT) & CP_REG_TO_MEM_0_CNT__MASK;
726 }
727 #define CP_REG_TO_MEM_0_64B 0x40000000
728 #define CP_REG_TO_MEM_0_ACCUMULATE 0x80000000
729
730 #define REG_CP_REG_TO_MEM_1 0x00000001
731 #define CP_REG_TO_MEM_1_DEST__MASK 0xffffffff
732 #define CP_REG_TO_MEM_1_DEST__SHIFT 0
733 static inline uint32_t CP_REG_TO_MEM_1_DEST(uint32_t val)
734 {
735 return ((val) << CP_REG_TO_MEM_1_DEST__SHIFT) & CP_REG_TO_MEM_1_DEST__MASK;
736 }
737
738 #define REG_CP_MEM_TO_MEM_0 0x00000000
739 #define CP_MEM_TO_MEM_0_NEG_A 0x00000001
740 #define CP_MEM_TO_MEM_0_NEG_B 0x00000002
741 #define CP_MEM_TO_MEM_0_NEG_C 0x00000004
742 #define CP_MEM_TO_MEM_0_DOUBLE 0x20000000
743
744 #define REG_CP_COND_WRITE_0 0x00000000
745 #define CP_COND_WRITE_0_FUNCTION__MASK 0x00000007
746 #define CP_COND_WRITE_0_FUNCTION__SHIFT 0
747 static inline uint32_t CP_COND_WRITE_0_FUNCTION(enum cp_cond_function val)
748 {
749 return ((val) << CP_COND_WRITE_0_FUNCTION__SHIFT) & CP_COND_WRITE_0_FUNCTION__MASK;
750 }
751 #define CP_COND_WRITE_0_POLL_MEMORY 0x00000010
752 #define CP_COND_WRITE_0_WRITE_MEMORY 0x00000100
753
754 #define REG_CP_COND_WRITE_1 0x00000001
755 #define CP_COND_WRITE_1_POLL_ADDR__MASK 0xffffffff
756 #define CP_COND_WRITE_1_POLL_ADDR__SHIFT 0
757 static inline uint32_t CP_COND_WRITE_1_POLL_ADDR(uint32_t val)
758 {
759 return ((val) << CP_COND_WRITE_1_POLL_ADDR__SHIFT) & CP_COND_WRITE_1_POLL_ADDR__MASK;
760 }
761
762 #define REG_CP_COND_WRITE_2 0x00000002
763 #define CP_COND_WRITE_2_REF__MASK 0xffffffff
764 #define CP_COND_WRITE_2_REF__SHIFT 0
765 static inline uint32_t CP_COND_WRITE_2_REF(uint32_t val)
766 {
767 return ((val) << CP_COND_WRITE_2_REF__SHIFT) & CP_COND_WRITE_2_REF__MASK;
768 }
769
770 #define REG_CP_COND_WRITE_3 0x00000003
771 #define CP_COND_WRITE_3_MASK__MASK 0xffffffff
772 #define CP_COND_WRITE_3_MASK__SHIFT 0
773 static inline uint32_t CP_COND_WRITE_3_MASK(uint32_t val)
774 {
775 return ((val) << CP_COND_WRITE_3_MASK__SHIFT) & CP_COND_WRITE_3_MASK__MASK;
776 }
777
778 #define REG_CP_COND_WRITE_4 0x00000004
779 #define CP_COND_WRITE_4_WRITE_ADDR__MASK 0xffffffff
780 #define CP_COND_WRITE_4_WRITE_ADDR__SHIFT 0
781 static inline uint32_t CP_COND_WRITE_4_WRITE_ADDR(uint32_t val)
782 {
783 return ((val) << CP_COND_WRITE_4_WRITE_ADDR__SHIFT) & CP_COND_WRITE_4_WRITE_ADDR__MASK;
784 }
785
786 #define REG_CP_COND_WRITE_5 0x00000005
787 #define CP_COND_WRITE_5_WRITE_DATA__MASK 0xffffffff
788 #define CP_COND_WRITE_5_WRITE_DATA__SHIFT 0
789 static inline uint32_t CP_COND_WRITE_5_WRITE_DATA(uint32_t val)
790 {
791 return ((val) << CP_COND_WRITE_5_WRITE_DATA__SHIFT) & CP_COND_WRITE_5_WRITE_DATA__MASK;
792 }
793
794 #define REG_CP_COND_WRITE5_0 0x00000000
795 #define CP_COND_WRITE5_0_FUNCTION__MASK 0x00000007
796 #define CP_COND_WRITE5_0_FUNCTION__SHIFT 0
797 static inline uint32_t CP_COND_WRITE5_0_FUNCTION(enum cp_cond_function val)
798 {
799 return ((val) << CP_COND_WRITE5_0_FUNCTION__SHIFT) & CP_COND_WRITE5_0_FUNCTION__MASK;
800 }
801 #define CP_COND_WRITE5_0_POLL_MEMORY 0x00000010
802 #define CP_COND_WRITE5_0_WRITE_MEMORY 0x00000100
803
804 #define REG_CP_COND_WRITE5_1 0x00000001
805 #define CP_COND_WRITE5_1_POLL_ADDR_LO__MASK 0xffffffff
806 #define CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT 0
807 static inline uint32_t CP_COND_WRITE5_1_POLL_ADDR_LO(uint32_t val)
808 {
809 return ((val) << CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT) & CP_COND_WRITE5_1_POLL_ADDR_LO__MASK;
810 }
811
812 #define REG_CP_COND_WRITE5_2 0x00000002
813 #define CP_COND_WRITE5_2_POLL_ADDR_HI__MASK 0xffffffff
814 #define CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT 0
815 static inline uint32_t CP_COND_WRITE5_2_POLL_ADDR_HI(uint32_t val)
816 {
817 return ((val) << CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT) & CP_COND_WRITE5_2_POLL_ADDR_HI__MASK;
818 }
819
820 #define REG_CP_COND_WRITE5_3 0x00000003
821 #define CP_COND_WRITE5_3_REF__MASK 0xffffffff
822 #define CP_COND_WRITE5_3_REF__SHIFT 0
823 static inline uint32_t CP_COND_WRITE5_3_REF(uint32_t val)
824 {
825 return ((val) << CP_COND_WRITE5_3_REF__SHIFT) & CP_COND_WRITE5_3_REF__MASK;
826 }
827
828 #define REG_CP_COND_WRITE5_4 0x00000004
829 #define CP_COND_WRITE5_4_MASK__MASK 0xffffffff
830 #define CP_COND_WRITE5_4_MASK__SHIFT 0
831 static inline uint32_t CP_COND_WRITE5_4_MASK(uint32_t val)
832 {
833 return ((val) << CP_COND_WRITE5_4_MASK__SHIFT) & CP_COND_WRITE5_4_MASK__MASK;
834 }
835
836 #define REG_CP_COND_WRITE5_5 0x00000005
837 #define CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK 0xffffffff
838 #define CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT 0
839 static inline uint32_t CP_COND_WRITE5_5_WRITE_ADDR_LO(uint32_t val)
840 {
841 return ((val) << CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT) & CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK;
842 }
843
844 #define REG_CP_COND_WRITE5_6 0x00000006
845 #define CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK 0xffffffff
846 #define CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT 0
847 static inline uint32_t CP_COND_WRITE5_6_WRITE_ADDR_HI(uint32_t val)
848 {
849 return ((val) << CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT) & CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK;
850 }
851
852 #define REG_CP_COND_WRITE5_7 0x00000007
853 #define CP_COND_WRITE5_7_WRITE_DATA__MASK 0xffffffff
854 #define CP_COND_WRITE5_7_WRITE_DATA__SHIFT 0
855 static inline uint32_t CP_COND_WRITE5_7_WRITE_DATA(uint32_t val)
856 {
857 return ((val) << CP_COND_WRITE5_7_WRITE_DATA__SHIFT) & CP_COND_WRITE5_7_WRITE_DATA__MASK;
858 }
859
860 #define REG_CP_DISPATCH_COMPUTE_0 0x00000000
861
862 #define REG_CP_DISPATCH_COMPUTE_1 0x00000001
863 #define CP_DISPATCH_COMPUTE_1_X__MASK 0xffffffff
864 #define CP_DISPATCH_COMPUTE_1_X__SHIFT 0
865 static inline uint32_t CP_DISPATCH_COMPUTE_1_X(uint32_t val)
866 {
867 return ((val) << CP_DISPATCH_COMPUTE_1_X__SHIFT) & CP_DISPATCH_COMPUTE_1_X__MASK;
868 }
869
870 #define REG_CP_DISPATCH_COMPUTE_2 0x00000002
871 #define CP_DISPATCH_COMPUTE_2_Y__MASK 0xffffffff
872 #define CP_DISPATCH_COMPUTE_2_Y__SHIFT 0
873 static inline uint32_t CP_DISPATCH_COMPUTE_2_Y(uint32_t val)
874 {
875 return ((val) << CP_DISPATCH_COMPUTE_2_Y__SHIFT) & CP_DISPATCH_COMPUTE_2_Y__MASK;
876 }
877
878 #define REG_CP_DISPATCH_COMPUTE_3 0x00000003
879 #define CP_DISPATCH_COMPUTE_3_Z__MASK 0xffffffff
880 #define CP_DISPATCH_COMPUTE_3_Z__SHIFT 0
881 static inline uint32_t CP_DISPATCH_COMPUTE_3_Z(uint32_t val)
882 {
883 return ((val) << CP_DISPATCH_COMPUTE_3_Z__SHIFT) & CP_DISPATCH_COMPUTE_3_Z__MASK;
884 }
885
886 #define REG_CP_SET_RENDER_MODE_0 0x00000000
887 #define CP_SET_RENDER_MODE_0_MODE__MASK 0x000001ff
888 #define CP_SET_RENDER_MODE_0_MODE__SHIFT 0
889 static inline uint32_t CP_SET_RENDER_MODE_0_MODE(enum render_mode_cmd val)
890 {
891 return ((val) << CP_SET_RENDER_MODE_0_MODE__SHIFT) & CP_SET_RENDER_MODE_0_MODE__MASK;
892 }
893
894 #define REG_CP_SET_RENDER_MODE_1 0x00000001
895 #define CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK 0xffffffff
896 #define CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT 0
897 static inline uint32_t CP_SET_RENDER_MODE_1_ADDR_0_LO(uint32_t val)
898 {
899 return ((val) << CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT) & CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK;
900 }
901
902 #define REG_CP_SET_RENDER_MODE_2 0x00000002
903 #define CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK 0xffffffff
904 #define CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT 0
905 static inline uint32_t CP_SET_RENDER_MODE_2_ADDR_0_HI(uint32_t val)
906 {
907 return ((val) << CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT) & CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK;
908 }
909
910 #define REG_CP_SET_RENDER_MODE_3 0x00000003
911 #define CP_SET_RENDER_MODE_3_VSC_ENABLE 0x00000008
912 #define CP_SET_RENDER_MODE_3_GMEM_ENABLE 0x00000010
913
914 #define REG_CP_SET_RENDER_MODE_4 0x00000004
915
916 #define REG_CP_SET_RENDER_MODE_5 0x00000005
917 #define CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK 0xffffffff
918 #define CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT 0
919 static inline uint32_t CP_SET_RENDER_MODE_5_ADDR_1_LEN(uint32_t val)
920 {
921 return ((val) << CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT) & CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK;
922 }
923
924 #define REG_CP_SET_RENDER_MODE_6 0x00000006
925 #define CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK 0xffffffff
926 #define CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT 0
927 static inline uint32_t CP_SET_RENDER_MODE_6_ADDR_1_LO(uint32_t val)
928 {
929 return ((val) << CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT) & CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK;
930 }
931
932 #define REG_CP_SET_RENDER_MODE_7 0x00000007
933 #define CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK 0xffffffff
934 #define CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT 0
935 static inline uint32_t CP_SET_RENDER_MODE_7_ADDR_1_HI(uint32_t val)
936 {
937 return ((val) << CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT) & CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK;
938 }
939
940 #define REG_CP_COMPUTE_CHECKPOINT_0 0x00000000
941 #define CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MASK 0xffffffff
942 #define CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT 0
943 static inline uint32_t CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO(uint32_t val)
944 {
945 return ((val) << CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT) & CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MASK;
946 }
947
948 #define REG_CP_COMPUTE_CHECKPOINT_1 0x00000001
949 #define CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MASK 0xffffffff
950 #define CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT 0
951 static inline uint32_t CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI(uint32_t val)
952 {
953 return ((val) << CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT) & CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MASK;
954 }
955
956 #define REG_CP_COMPUTE_CHECKPOINT_2 0x00000002
957
958 #define REG_CP_COMPUTE_CHECKPOINT_3 0x00000003
959
960 #define REG_CP_COMPUTE_CHECKPOINT_4 0x00000004
961 #define CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__MASK 0xffffffff
962 #define CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__SHIFT 0
963 static inline uint32_t CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN(uint32_t val)
964 {
965 return ((val) << CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__SHIFT) & CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__MASK;
966 }
967
968 #define REG_CP_COMPUTE_CHECKPOINT_5 0x00000005
969 #define CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK 0xffffffff
970 #define CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT 0
971 static inline uint32_t CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO(uint32_t val)
972 {
973 return ((val) << CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT) & CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK;
974 }
975
976 #define REG_CP_COMPUTE_CHECKPOINT_6 0x00000006
977 #define CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MASK 0xffffffff
978 #define CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT 0
979 static inline uint32_t CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI(uint32_t val)
980 {
981 return ((val) << CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT) & CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MASK;
982 }
983
984 #define REG_CP_PERFCOUNTER_ACTION_0 0x00000000
985
986 #define REG_CP_PERFCOUNTER_ACTION_1 0x00000001
987 #define CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK 0xffffffff
988 #define CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT 0
989 static inline uint32_t CP_PERFCOUNTER_ACTION_1_ADDR_0_LO(uint32_t val)
990 {
991 return ((val) << CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT) & CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK;
992 }
993
994 #define REG_CP_PERFCOUNTER_ACTION_2 0x00000002
995 #define CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK 0xffffffff
996 #define CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT 0
997 static inline uint32_t CP_PERFCOUNTER_ACTION_2_ADDR_0_HI(uint32_t val)
998 {
999 return ((val) << CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT) & CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK;
1000 }
1001
1002 #define REG_CP_EVENT_WRITE_0 0x00000000
1003 #define CP_EVENT_WRITE_0_EVENT__MASK 0x000000ff
1004 #define CP_EVENT_WRITE_0_EVENT__SHIFT 0
1005 static inline uint32_t CP_EVENT_WRITE_0_EVENT(enum vgt_event_type val)
1006 {
1007 return ((val) << CP_EVENT_WRITE_0_EVENT__SHIFT) & CP_EVENT_WRITE_0_EVENT__MASK;
1008 }
1009 #define CP_EVENT_WRITE_0_TIMESTAMP 0x40000000
1010
1011 #define REG_CP_EVENT_WRITE_1 0x00000001
1012 #define CP_EVENT_WRITE_1_ADDR_0_LO__MASK 0xffffffff
1013 #define CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT 0
1014 static inline uint32_t CP_EVENT_WRITE_1_ADDR_0_LO(uint32_t val)
1015 {
1016 return ((val) << CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT) & CP_EVENT_WRITE_1_ADDR_0_LO__MASK;
1017 }
1018
1019 #define REG_CP_EVENT_WRITE_2 0x00000002
1020 #define CP_EVENT_WRITE_2_ADDR_0_HI__MASK 0xffffffff
1021 #define CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT 0
1022 static inline uint32_t CP_EVENT_WRITE_2_ADDR_0_HI(uint32_t val)
1023 {
1024 return ((val) << CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT) & CP_EVENT_WRITE_2_ADDR_0_HI__MASK;
1025 }
1026
1027 #define REG_CP_EVENT_WRITE_3 0x00000003
1028
1029 #define REG_CP_BLIT_0 0x00000000
1030 #define CP_BLIT_0_OP__MASK 0x0000000f
1031 #define CP_BLIT_0_OP__SHIFT 0
1032 static inline uint32_t CP_BLIT_0_OP(enum cp_blit_cmd val)
1033 {
1034 return ((val) << CP_BLIT_0_OP__SHIFT) & CP_BLIT_0_OP__MASK;
1035 }
1036
1037 #define REG_CP_BLIT_1 0x00000001
1038 #define CP_BLIT_1_SRC_X1__MASK 0x0000ffff
1039 #define CP_BLIT_1_SRC_X1__SHIFT 0
1040 static inline uint32_t CP_BLIT_1_SRC_X1(uint32_t val)
1041 {
1042 return ((val) << CP_BLIT_1_SRC_X1__SHIFT) & CP_BLIT_1_SRC_X1__MASK;
1043 }
1044 #define CP_BLIT_1_SRC_Y1__MASK 0xffff0000
1045 #define CP_BLIT_1_SRC_Y1__SHIFT 16
1046 static inline uint32_t CP_BLIT_1_SRC_Y1(uint32_t val)
1047 {
1048 return ((val) << CP_BLIT_1_SRC_Y1__SHIFT) & CP_BLIT_1_SRC_Y1__MASK;
1049 }
1050
1051 #define REG_CP_BLIT_2 0x00000002
1052 #define CP_BLIT_2_SRC_X2__MASK 0x0000ffff
1053 #define CP_BLIT_2_SRC_X2__SHIFT 0
1054 static inline uint32_t CP_BLIT_2_SRC_X2(uint32_t val)
1055 {
1056 return ((val) << CP_BLIT_2_SRC_X2__SHIFT) & CP_BLIT_2_SRC_X2__MASK;
1057 }
1058 #define CP_BLIT_2_SRC_Y2__MASK 0xffff0000
1059 #define CP_BLIT_2_SRC_Y2__SHIFT 16
1060 static inline uint32_t CP_BLIT_2_SRC_Y2(uint32_t val)
1061 {
1062 return ((val) << CP_BLIT_2_SRC_Y2__SHIFT) & CP_BLIT_2_SRC_Y2__MASK;
1063 }
1064
1065 #define REG_CP_BLIT_3 0x00000003
1066 #define CP_BLIT_3_DST_X1__MASK 0x0000ffff
1067 #define CP_BLIT_3_DST_X1__SHIFT 0
1068 static inline uint32_t CP_BLIT_3_DST_X1(uint32_t val)
1069 {
1070 return ((val) << CP_BLIT_3_DST_X1__SHIFT) & CP_BLIT_3_DST_X1__MASK;
1071 }
1072 #define CP_BLIT_3_DST_Y1__MASK 0xffff0000
1073 #define CP_BLIT_3_DST_Y1__SHIFT 16
1074 static inline uint32_t CP_BLIT_3_DST_Y1(uint32_t val)
1075 {
1076 return ((val) << CP_BLIT_3_DST_Y1__SHIFT) & CP_BLIT_3_DST_Y1__MASK;
1077 }
1078
1079 #define REG_CP_BLIT_4 0x00000004
1080 #define CP_BLIT_4_DST_X2__MASK 0x0000ffff
1081 #define CP_BLIT_4_DST_X2__SHIFT 0
1082 static inline uint32_t CP_BLIT_4_DST_X2(uint32_t val)
1083 {
1084 return ((val) << CP_BLIT_4_DST_X2__SHIFT) & CP_BLIT_4_DST_X2__MASK;
1085 }
1086 #define CP_BLIT_4_DST_Y2__MASK 0xffff0000
1087 #define CP_BLIT_4_DST_Y2__SHIFT 16
1088 static inline uint32_t CP_BLIT_4_DST_Y2(uint32_t val)
1089 {
1090 return ((val) << CP_BLIT_4_DST_Y2__SHIFT) & CP_BLIT_4_DST_Y2__MASK;
1091 }
1092
1093 #define REG_CP_EXEC_CS_0 0x00000000
1094
1095 #define REG_CP_EXEC_CS_1 0x00000001
1096 #define CP_EXEC_CS_1_NGROUPS_X__MASK 0xffffffff
1097 #define CP_EXEC_CS_1_NGROUPS_X__SHIFT 0
1098 static inline uint32_t CP_EXEC_CS_1_NGROUPS_X(uint32_t val)
1099 {
1100 return ((val) << CP_EXEC_CS_1_NGROUPS_X__SHIFT) & CP_EXEC_CS_1_NGROUPS_X__MASK;
1101 }
1102
1103 #define REG_CP_EXEC_CS_2 0x00000002
1104 #define CP_EXEC_CS_2_NGROUPS_Y__MASK 0xffffffff
1105 #define CP_EXEC_CS_2_NGROUPS_Y__SHIFT 0
1106 static inline uint32_t CP_EXEC_CS_2_NGROUPS_Y(uint32_t val)
1107 {
1108 return ((val) << CP_EXEC_CS_2_NGROUPS_Y__SHIFT) & CP_EXEC_CS_2_NGROUPS_Y__MASK;
1109 }
1110
1111 #define REG_CP_EXEC_CS_3 0x00000003
1112 #define CP_EXEC_CS_3_NGROUPS_Z__MASK 0xffffffff
1113 #define CP_EXEC_CS_3_NGROUPS_Z__SHIFT 0
1114 static inline uint32_t CP_EXEC_CS_3_NGROUPS_Z(uint32_t val)
1115 {
1116 return ((val) << CP_EXEC_CS_3_NGROUPS_Z__SHIFT) & CP_EXEC_CS_3_NGROUPS_Z__MASK;
1117 }
1118
1119 #define REG_CP_EXEC_CS_INDIRECT_0 0x00000000
1120
1121 #define REG_CP_EXEC_CS_INDIRECT_1 0x00000001
1122 #define CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK 0xffffffff
1123 #define CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT 0
1124 static inline uint32_t CP_EXEC_CS_INDIRECT_1_ADDR_LO(uint32_t val)
1125 {
1126 return ((val) << CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT) & CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK;
1127 }
1128
1129 #define REG_CP_EXEC_CS_INDIRECT_2 0x00000002
1130 #define CP_EXEC_CS_INDIRECT_2_ADDR_HI__MASK 0xffffffff
1131 #define CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT 0
1132 static inline uint32_t CP_EXEC_CS_INDIRECT_2_ADDR_HI(uint32_t val)
1133 {
1134 return ((val) << CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT) & CP_EXEC_CS_INDIRECT_2_ADDR_HI__MASK;
1135 }
1136
1137 #define REG_CP_EXEC_CS_INDIRECT_3 0x00000003
1138 #define CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__MASK 0x00000ffc
1139 #define CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT 2
1140 static inline uint32_t CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(uint32_t val)
1141 {
1142 return ((val) << CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT) & CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__MASK;
1143 }
1144 #define CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__MASK 0x003ff000
1145 #define CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT 12
1146 static inline uint32_t CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(uint32_t val)
1147 {
1148 return ((val) << CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT) & CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__MASK;
1149 }
1150 #define CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK 0xffc00000
1151 #define CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT 22
1152 static inline uint32_t CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(uint32_t val)
1153 {
1154 return ((val) << CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT) & CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK;
1155 }
1156
1157
1158 #endif /* ADRENO_PM4_XML */