src/gallium/drivers/freedreno/adreno_pm4.xml.h

   1 #ifndef ADRENO_PM4_XML
   2 #define ADRENO_PM4_XML
   3
   4 /* Autogenerated file, DO NOT EDIT manually!
   5
   6 This file was generated by the rules-ng-ng headergen tool in this git repository:
   7 http://github.com/freedreno/envytools/
   8 git clone https://github.com/freedreno/envytools.git
   9
  10 The rules-ng-ng source files this header was generated from are:
  11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml               (    398 bytes, from 2015-09-24 17:25:31)
  12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml  (   1453 bytes, from 2015-05-20 20:03:07)
  13 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml          (  32901 bytes, from 2015-05-20 20:03:14)
  14 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml (  11518 bytes, from 2015-11-24 14:39:00)
  15 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml    (  15149 bytes, from 2015-11-20 16:22:25)
  16 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml          (  69600 bytes, from 2015-11-24 14:39:00)
  17 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml          (  67220 bytes, from 2015-12-13 17:58:09)
  18 - /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml         (   1773 bytes, from 2015-09-24 17:30:00)
  19
  20 Copyright (C) 2013-2015 by the following authors:
  21 - Rob Clark <robdclark@gmail.com> (robclark)
  22
  23 Permission is hereby granted, free of charge, to any person obtaining
  24 a copy of this software and associated documentation files (the
  25 "Software"), to deal in the Software without restriction, including
  26 without limitation the rights to use, copy, modify, merge, publish,
  27 distribute, sublicense, and/or sell copies of the Software, and to
  28 permit persons to whom the Software is furnished to do so, subject to
  29 the following conditions:
  30
  31 The above copyright notice and this permission notice (including the
  32 next paragraph) shall be included in all copies or substantial
  33 portions of the Software.
  34
  35 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  37 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  38 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  39 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  40 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  41 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  42 */
  43
  44
  45 enum vgt_event_type {
  46         VS_DEALLOC = 0,
  47         PS_DEALLOC = 1,
  48         VS_DONE_TS = 2,
  49         PS_DONE_TS = 3,
  50         CACHE_FLUSH_TS = 4,
  51         CONTEXT_DONE = 5,
  52         CACHE_FLUSH = 6,
  53         HLSQ_FLUSH = 7,
  54         VIZQUERY_START = 7,
  55         VIZQUERY_END = 8,
  56         SC_WAIT_WC = 9,
  57         RST_PIX_CNT = 13,
  58         RST_VTX_CNT = 14,
  59         TILE_FLUSH = 15,
  60         CACHE_FLUSH_AND_INV_TS_EVENT = 20,
  61         ZPASS_DONE = 21,
  62         CACHE_FLUSH_AND_INV_EVENT = 22,
  63         PERFCOUNTER_START = 23,
  64         PERFCOUNTER_STOP = 24,
  65         VS_FETCH_DONE = 27,
  66         FACENESS_FLUSH = 28,
  67 };
  68
  69 enum pc_di_primtype {
  70         DI_PT_NONE = 0,
  71         DI_PT_POINTLIST_PSIZE = 1,
  72         DI_PT_LINELIST = 2,
  73         DI_PT_LINESTRIP = 3,
  74         DI_PT_TRILIST = 4,
  75         DI_PT_TRIFAN = 5,
  76         DI_PT_TRISTRIP = 6,
  77         DI_PT_LINELOOP = 7,
  78         DI_PT_RECTLIST = 8,
  79         DI_PT_POINTLIST = 9,
  80         DI_PT_LINE_ADJ = 10,
  81         DI_PT_LINESTRIP_ADJ = 11,
  82         DI_PT_TRI_ADJ = 12,
  83         DI_PT_TRISTRIP_ADJ = 13,
  84         DI_PT_PATCHES = 34,
  85 };
  86
  87 enum pc_di_src_sel {
  88         DI_SRC_SEL_DMA = 0,
  89         DI_SRC_SEL_IMMEDIATE = 1,
  90         DI_SRC_SEL_AUTO_INDEX = 2,
  91         DI_SRC_SEL_RESERVED = 3,
  92 };
  93
  94 enum pc_di_index_size {
  95         INDEX_SIZE_IGN = 0,
  96         INDEX_SIZE_16_BIT = 0,
  97         INDEX_SIZE_32_BIT = 1,
  98         INDEX_SIZE_8_BIT = 2,
  99         INDEX_SIZE_INVALID = 0,
 100 };
 101
 102 enum pc_di_vis_cull_mode {
 103         IGNORE_VISIBILITY = 0,
 104         USE_VISIBILITY = 1,
 105 };
 106
 107 enum adreno_pm4_packet_type {
 108         CP_TYPE0_PKT = 0,
 109         CP_TYPE1_PKT = 0x40000000,
 110         CP_TYPE2_PKT = 0x80000000,
 111         CP_TYPE3_PKT = 0xc0000000,
 112 };
 113
 114 enum adreno_pm4_type3_packets {
 115         CP_ME_INIT = 72,
 116         CP_NOP = 16,
 117         CP_INDIRECT_BUFFER = 63,
 118         CP_INDIRECT_BUFFER_PFD = 55,
 119         CP_WAIT_FOR_IDLE = 38,
 120         CP_WAIT_REG_MEM = 60,
 121         CP_WAIT_REG_EQ = 82,
 122         CP_WAIT_REG_GTE = 83,
 123         CP_WAIT_UNTIL_READ = 92,
 124         CP_WAIT_IB_PFD_COMPLETE = 93,
 125         CP_REG_RMW = 33,
 126         CP_SET_BIN_DATA = 47,
 127         CP_REG_TO_MEM = 62,
 128         CP_MEM_WRITE = 61,
 129         CP_MEM_WRITE_CNTR = 79,
 130         CP_COND_EXEC = 68,
 131         CP_COND_WRITE = 69,
 132         CP_EVENT_WRITE = 70,
 133         CP_EVENT_WRITE_SHD = 88,
 134         CP_EVENT_WRITE_CFL = 89,
 135         CP_EVENT_WRITE_ZPD = 91,
 136         CP_RUN_OPENCL = 49,
 137         CP_DRAW_INDX = 34,
 138         CP_DRAW_INDX_2 = 54,
 139         CP_DRAW_INDX_BIN = 52,
 140         CP_DRAW_INDX_2_BIN = 53,
 141         CP_VIZ_QUERY = 35,
 142         CP_SET_STATE = 37,
 143         CP_SET_CONSTANT = 45,
 144         CP_IM_LOAD = 39,
 145         CP_IM_LOAD_IMMEDIATE = 43,
 146         CP_LOAD_CONSTANT_CONTEXT = 46,
 147         CP_INVALIDATE_STATE = 59,
 148         CP_SET_SHADER_BASES = 74,
 149         CP_SET_BIN_MASK = 80,
 150         CP_SET_BIN_SELECT = 81,
 151         CP_CONTEXT_UPDATE = 94,
 152         CP_INTERRUPT = 64,
 153         CP_IM_STORE = 44,
 154         CP_SET_DRAW_INIT_FLAGS = 75,
 155         CP_SET_PROTECTED_MODE = 95,
 156         CP_BOOTSTRAP_UCODE = 111,
 157         CP_LOAD_STATE = 48,
 158         CP_COND_INDIRECT_BUFFER_PFE = 58,
 159         CP_COND_INDIRECT_BUFFER_PFD = 50,
 160         CP_INDIRECT_BUFFER_PFE = 63,
 161         CP_SET_BIN = 76,
 162         CP_TEST_TWO_MEMS = 113,
 163         CP_REG_WR_NO_CTXT = 120,
 164         CP_RECORD_PFP_TIMESTAMP = 17,
 165         CP_WAIT_FOR_ME = 19,
 166         CP_SET_DRAW_STATE = 67,
 167         CP_DRAW_INDX_OFFSET = 56,
 168         CP_DRAW_INDIRECT = 40,
 169         CP_DRAW_INDX_INDIRECT = 41,
 170         CP_DRAW_AUTO = 36,
 171         CP_UNKNOWN_19 = 25,
 172         CP_UNKNOWN_1A = 26,
 173         CP_UNKNOWN_4E = 78,
 174         CP_WIDE_REG_WRITE = 116,
 175         IN_IB_PREFETCH_END = 23,
 176         IN_SUBBLK_PREFETCH = 31,
 177         IN_INSTR_PREFETCH = 32,
 178         IN_INSTR_MATCH = 71,
 179         IN_CONST_PREFETCH = 73,
 180         IN_INCR_UPDT_STATE = 85,
 181         IN_INCR_UPDT_CONST = 86,
 182         IN_INCR_UPDT_INSTR = 87,
 183 };
 184
 185 enum adreno_state_block {
 186         SB_VERT_TEX = 0,
 187         SB_VERT_MIPADDR = 1,
 188         SB_FRAG_TEX = 2,
 189         SB_FRAG_MIPADDR = 3,
 190         SB_VERT_SHADER = 4,
 191         SB_GEOM_SHADER = 5,
 192         SB_FRAG_SHADER = 6,
 193 };
 194
 195 enum adreno_state_type {
 196         ST_SHADER = 0,
 197         ST_CONSTANTS = 1,
 198 };
 199
 200 enum adreno_state_src {
 201         SS_DIRECT = 0,
 202         SS_INVALID_ALL_IC = 2,
 203         SS_INVALID_PART_IC = 3,
 204         SS_INDIRECT = 4,
 205         SS_INDIRECT_TCM = 5,
 206         SS_INDIRECT_STM = 6,
 207 };
 208
 209 enum a4xx_index_size {
 210         INDEX4_SIZE_8_BIT = 0,
 211         INDEX4_SIZE_16_BIT = 1,
 212         INDEX4_SIZE_32_BIT = 2,
 213 };
 214
 215 #define REG_CP_LOAD_STATE_0                                     0x00000000
 216 #define CP_LOAD_STATE_0_DST_OFF__MASK                           0x0000ffff
 217 #define CP_LOAD_STATE_0_DST_OFF__SHIFT                          0
 218 static inline uint32_t CP_LOAD_STATE_0_DST_OFF(uint32_t val)
 219 {
 220         return ((val) << CP_LOAD_STATE_0_DST_OFF__SHIFT) & CP_LOAD_STATE_0_DST_OFF__MASK;
 221 }
 222 #define CP_LOAD_STATE_0_STATE_SRC__MASK                         0x00070000
 223 #define CP_LOAD_STATE_0_STATE_SRC__SHIFT                        16
 224 static inline uint32_t CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val)
 225 {
 226         return ((val) << CP_LOAD_STATE_0_STATE_SRC__SHIFT) & CP_LOAD_STATE_0_STATE_SRC__MASK;
 227 }
 228 #define CP_LOAD_STATE_0_STATE_BLOCK__MASK                       0x00380000
 229 #define CP_LOAD_STATE_0_STATE_BLOCK__SHIFT                      19
 230 static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val)
 231 {
 232         return ((val) << CP_LOAD_STATE_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE_0_STATE_BLOCK__MASK;
 233 }
 234 #define CP_LOAD_STATE_0_NUM_UNIT__MASK                          0xffc00000
 235 #define CP_LOAD_STATE_0_NUM_UNIT__SHIFT                         22
 236 static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val)
 237 {
 238         return ((val) << CP_LOAD_STATE_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE_0_NUM_UNIT__MASK;
 239 }
 240
 241 #define REG_CP_LOAD_STATE_1                                     0x00000001
 242 #define CP_LOAD_STATE_1_STATE_TYPE__MASK                        0x00000003
 243 #define CP_LOAD_STATE_1_STATE_TYPE__SHIFT                       0
 244 static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val)
 245 {
 246         return ((val) << CP_LOAD_STATE_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE_1_STATE_TYPE__MASK;
 247 }
 248 #define CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK                      0xfffffffc
 249 #define CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT                     2
 250 static inline uint32_t CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val)
 251 {
 252         return ((val >> 2) << CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK;
 253 }
 254
 255 #define REG_CP_DRAW_INDX_0                                      0x00000000
 256 #define CP_DRAW_INDX_0_VIZ_QUERY__MASK                          0xffffffff
 257 #define CP_DRAW_INDX_0_VIZ_QUERY__SHIFT                         0
 258 static inline uint32_t CP_DRAW_INDX_0_VIZ_QUERY(uint32_t val)
 259 {
 260         return ((val) << CP_DRAW_INDX_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_0_VIZ_QUERY__MASK;
 261 }
 262
 263 #define REG_CP_DRAW_INDX_1                                      0x00000001
 264 #define CP_DRAW_INDX_1_PRIM_TYPE__MASK                          0x0000003f
 265 #define CP_DRAW_INDX_1_PRIM_TYPE__SHIFT                         0
 266 static inline uint32_t CP_DRAW_INDX_1_PRIM_TYPE(enum pc_di_primtype val)
 267 {
 268         return ((val) << CP_DRAW_INDX_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_1_PRIM_TYPE__MASK;
 269 }
 270 #define CP_DRAW_INDX_1_SOURCE_SELECT__MASK                      0x000000c0
 271 #define CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT                     6
 272 static inline uint32_t CP_DRAW_INDX_1_SOURCE_SELECT(enum pc_di_src_sel val)
 273 {
 274         return ((val) << CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_1_SOURCE_SELECT__MASK;
 275 }
 276 #define CP_DRAW_INDX_1_VIS_CULL__MASK                           0x00000600
 277 #define CP_DRAW_INDX_1_VIS_CULL__SHIFT                          9
 278 static inline uint32_t CP_DRAW_INDX_1_VIS_CULL(enum pc_di_vis_cull_mode val)
 279 {
 280         return ((val) << CP_DRAW_INDX_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_1_VIS_CULL__MASK;
 281 }
 282 #define CP_DRAW_INDX_1_INDEX_SIZE__MASK                         0x00000800
 283 #define CP_DRAW_INDX_1_INDEX_SIZE__SHIFT                        11
 284 static inline uint32_t CP_DRAW_INDX_1_INDEX_SIZE(enum pc_di_index_size val)
 285 {
 286         return ((val) << CP_DRAW_INDX_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_1_INDEX_SIZE__MASK;
 287 }
 288 #define CP_DRAW_INDX_1_NOT_EOP                                  0x00001000
 289 #define CP_DRAW_INDX_1_SMALL_INDEX                              0x00002000
 290 #define CP_DRAW_INDX_1_PRE_DRAW_INITIATOR_ENABLE                0x00004000
 291 #define CP_DRAW_INDX_1_NUM_INSTANCES__MASK                      0xff000000
 292 #define CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT                     24
 293 static inline uint32_t CP_DRAW_INDX_1_NUM_INSTANCES(uint32_t val)
 294 {
 295         return ((val) << CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_1_NUM_INSTANCES__MASK;
 296 }
 297
 298 #define REG_CP_DRAW_INDX_2                                      0x00000002
 299 #define CP_DRAW_INDX_2_NUM_INDICES__MASK                        0xffffffff
 300 #define CP_DRAW_INDX_2_NUM_INDICES__SHIFT                       0
 301 static inline uint32_t CP_DRAW_INDX_2_NUM_INDICES(uint32_t val)
 302 {
 303         return ((val) << CP_DRAW_INDX_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_NUM_INDICES__MASK;
 304 }
 305
 306 #define REG_CP_DRAW_INDX_3                                      0x00000003
 307 #define CP_DRAW_INDX_3_INDX_BASE__MASK                          0xffffffff
 308 #define CP_DRAW_INDX_3_INDX_BASE__SHIFT                         0
 309 static inline uint32_t CP_DRAW_INDX_3_INDX_BASE(uint32_t val)
 310 {
 311         return ((val) << CP_DRAW_INDX_3_INDX_BASE__SHIFT) & CP_DRAW_INDX_3_INDX_BASE__MASK;
 312 }
 313
 314 #define REG_CP_DRAW_INDX_4                                      0x00000004
 315 #define CP_DRAW_INDX_4_INDX_SIZE__MASK                          0xffffffff
 316 #define CP_DRAW_INDX_4_INDX_SIZE__SHIFT                         0
 317 static inline uint32_t CP_DRAW_INDX_4_INDX_SIZE(uint32_t val)
 318 {
 319         return ((val) << CP_DRAW_INDX_4_INDX_SIZE__SHIFT) & CP_DRAW_INDX_4_INDX_SIZE__MASK;
 320 }
 321
 322 #define REG_CP_DRAW_INDX_2_0                                    0x00000000
 323 #define CP_DRAW_INDX_2_0_VIZ_QUERY__MASK                        0xffffffff
 324 #define CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT                       0
 325 static inline uint32_t CP_DRAW_INDX_2_0_VIZ_QUERY(uint32_t val)
 326 {
 327         return ((val) << CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_2_0_VIZ_QUERY__MASK;
 328 }
 329
 330 #define REG_CP_DRAW_INDX_2_1                                    0x00000001
 331 #define CP_DRAW_INDX_2_1_PRIM_TYPE__MASK                        0x0000003f
 332 #define CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT                       0
 333 static inline uint32_t CP_DRAW_INDX_2_1_PRIM_TYPE(enum pc_di_primtype val)
 334 {
 335         return ((val) << CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_2_1_PRIM_TYPE__MASK;
 336 }
 337 #define CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK                    0x000000c0
 338 #define CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT                   6
 339 static inline uint32_t CP_DRAW_INDX_2_1_SOURCE_SELECT(enum pc_di_src_sel val)
 340 {
 341         return ((val) << CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK;
 342 }
 343 #define CP_DRAW_INDX_2_1_VIS_CULL__MASK                         0x00000600
 344 #define CP_DRAW_INDX_2_1_VIS_CULL__SHIFT                        9
 345 static inline uint32_t CP_DRAW_INDX_2_1_VIS_CULL(enum pc_di_vis_cull_mode val)
 346 {
 347         return ((val) << CP_DRAW_INDX_2_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_2_1_VIS_CULL__MASK;
 348 }
 349 #define CP_DRAW_INDX_2_1_INDEX_SIZE__MASK                       0x00000800
 350 #define CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT                      11
 351 static inline uint32_t CP_DRAW_INDX_2_1_INDEX_SIZE(enum pc_di_index_size val)
 352 {
 353         return ((val) << CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_2_1_INDEX_SIZE__MASK;
 354 }
 355 #define CP_DRAW_INDX_2_1_NOT_EOP                                0x00001000
 356 #define CP_DRAW_INDX_2_1_SMALL_INDEX                            0x00002000
 357 #define CP_DRAW_INDX_2_1_PRE_DRAW_INITIATOR_ENABLE              0x00004000
 358 #define CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK                    0xff000000
 359 #define CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT                   24
 360 static inline uint32_t CP_DRAW_INDX_2_1_NUM_INSTANCES(uint32_t val)
 361 {
 362         return ((val) << CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK;
 363 }
 364
 365 #define REG_CP_DRAW_INDX_2_2                                    0x00000002
 366 #define CP_DRAW_INDX_2_2_NUM_INDICES__MASK                      0xffffffff
 367 #define CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT                     0
 368 static inline uint32_t CP_DRAW_INDX_2_2_NUM_INDICES(uint32_t val)
 369 {
 370         return ((val) << CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_2_NUM_INDICES__MASK;
 371 }
 372
 373 #define REG_CP_DRAW_INDX_OFFSET_0                               0x00000000
 374 #define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK                   0x0000003f
 375 #define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT                  0
 376 static inline uint32_t CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(enum pc_di_primtype val)
 377 {
 378         return ((val) << CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK;
 379 }
 380 #define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK               0x000000c0
 381 #define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT              6
 382 static inline uint32_t CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel val)
 383 {
 384         return ((val) << CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK;
 385 }
 386 #define CP_DRAW_INDX_OFFSET_0_TESSELLATE                        0x00000100
 387 #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK                  0x00000c00
 388 #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT                 10
 389 static inline uint32_t CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum a4xx_index_size val)
 390 {
 391         return ((val) << CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK;
 392 }
 393 #define CP_DRAW_INDX_OFFSET_0_TESS_MODE__MASK                   0x01f00000
 394 #define CP_DRAW_INDX_OFFSET_0_TESS_MODE__SHIFT                  20
 395 static inline uint32_t CP_DRAW_INDX_OFFSET_0_TESS_MODE(uint32_t val)
 396 {
 397         return ((val) << CP_DRAW_INDX_OFFSET_0_TESS_MODE__SHIFT) & CP_DRAW_INDX_OFFSET_0_TESS_MODE__MASK;
 398 }
 399
 400 #define REG_CP_DRAW_INDX_OFFSET_1                               0x00000001
 401 #define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK               0xffffffff
 402 #define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT              0
 403 static inline uint32_t CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES(uint32_t val)
 404 {
 405         return ((val) << CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK;
 406 }
 407
 408 #define REG_CP_DRAW_INDX_OFFSET_2                               0x00000002
 409 #define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK                 0xffffffff
 410 #define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT                0
 411 static inline uint32_t CP_DRAW_INDX_OFFSET_2_NUM_INDICES(uint32_t val)
 412 {
 413         return ((val) << CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK;
 414 }
 415
 416 #define REG_CP_DRAW_INDX_OFFSET_3                               0x00000003
 417
 418 #define REG_CP_DRAW_INDX_OFFSET_4                               0x00000004
 419 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK                   0xffffffff
 420 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT                  0
 421 static inline uint32_t CP_DRAW_INDX_OFFSET_4_INDX_BASE(uint32_t val)
 422 {
 423         return ((val) << CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT) & CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK;
 424 }
 425
 426 #define REG_CP_DRAW_INDX_OFFSET_5                               0x00000005
 427 #define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK                   0xffffffff
 428 #define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT                  0
 429 static inline uint32_t CP_DRAW_INDX_OFFSET_5_INDX_SIZE(uint32_t val)
 430 {
 431         return ((val) << CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK;
 432 }
 433
 434 #define REG_CP_SET_DRAW_STATE_0                                 0x00000000
 435 #define CP_SET_DRAW_STATE_0_COUNT__MASK                         0x0000ffff
 436 #define CP_SET_DRAW_STATE_0_COUNT__SHIFT                        0
 437 static inline uint32_t CP_SET_DRAW_STATE_0_COUNT(uint32_t val)
 438 {
 439         return ((val) << CP_SET_DRAW_STATE_0_COUNT__SHIFT) & CP_SET_DRAW_STATE_0_COUNT__MASK;
 440 }
 441 #define CP_SET_DRAW_STATE_0_DIRTY                               0x00010000
 442 #define CP_SET_DRAW_STATE_0_DISABLE                             0x00020000
 443 #define CP_SET_DRAW_STATE_0_DISABLE_ALL_GROUPS                  0x00040000
 444 #define CP_SET_DRAW_STATE_0_LOAD_IMMED                          0x00080000
 445 #define CP_SET_DRAW_STATE_0_GROUP_ID__MASK                      0x1f000000
 446 #define CP_SET_DRAW_STATE_0_GROUP_ID__SHIFT                     24
 447 static inline uint32_t CP_SET_DRAW_STATE_0_GROUP_ID(uint32_t val)
 448 {
 449         return ((val) << CP_SET_DRAW_STATE_0_GROUP_ID__SHIFT) & CP_SET_DRAW_STATE_0_GROUP_ID__MASK;
 450 }
 451
 452 #define REG_CP_SET_DRAW_STATE_1                                 0x00000001
 453 #define CP_SET_DRAW_STATE_1_ADDR__MASK                          0xffffffff
 454 #define CP_SET_DRAW_STATE_1_ADDR__SHIFT                         0
 455 static inline uint32_t CP_SET_DRAW_STATE_1_ADDR(uint32_t val)
 456 {
 457         return ((val) << CP_SET_DRAW_STATE_1_ADDR__SHIFT) & CP_SET_DRAW_STATE_1_ADDR__MASK;
 458 }
 459
 460 #define REG_CP_SET_BIN_0                                        0x00000000
 461
 462 #define REG_CP_SET_BIN_1                                        0x00000001
 463 #define CP_SET_BIN_1_X1__MASK                                   0x0000ffff
 464 #define CP_SET_BIN_1_X1__SHIFT                                  0
 465 static inline uint32_t CP_SET_BIN_1_X1(uint32_t val)
 466 {
 467         return ((val) << CP_SET_BIN_1_X1__SHIFT) & CP_SET_BIN_1_X1__MASK;
 468 }
 469 #define CP_SET_BIN_1_Y1__MASK                                   0xffff0000
 470 #define CP_SET_BIN_1_Y1__SHIFT                                  16
 471 static inline uint32_t CP_SET_BIN_1_Y1(uint32_t val)
 472 {
 473         return ((val) << CP_SET_BIN_1_Y1__SHIFT) & CP_SET_BIN_1_Y1__MASK;
 474 }
 475
 476 #define REG_CP_SET_BIN_2                                        0x00000002
 477 #define CP_SET_BIN_2_X2__MASK                                   0x0000ffff
 478 #define CP_SET_BIN_2_X2__SHIFT                                  0
 479 static inline uint32_t CP_SET_BIN_2_X2(uint32_t val)
 480 {
 481         return ((val) << CP_SET_BIN_2_X2__SHIFT) & CP_SET_BIN_2_X2__MASK;
 482 }
 483 #define CP_SET_BIN_2_Y2__MASK                                   0xffff0000
 484 #define CP_SET_BIN_2_Y2__SHIFT                                  16
 485 static inline uint32_t CP_SET_BIN_2_Y2(uint32_t val)
 486 {
 487         return ((val) << CP_SET_BIN_2_Y2__SHIFT) & CP_SET_BIN_2_Y2__MASK;
 488 }
 489
 490 #define REG_CP_SET_BIN_DATA_0                                   0x00000000
 491 #define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK                   0xffffffff
 492 #define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT                  0
 493 static inline uint32_t CP_SET_BIN_DATA_0_BIN_DATA_ADDR(uint32_t val)
 494 {
 495         return ((val) << CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT) & CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK;
 496 }
 497
 498 #define REG_CP_SET_BIN_DATA_1                                   0x00000001
 499 #define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK                0xffffffff
 500 #define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT               0
 501 static inline uint32_t CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS(uint32_t val)
 502 {
 503         return ((val) << CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT) & CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK;
 504 }
 505
 506
 507 #endif /* ADRENO_PM4_XML */