projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
freedreno: update generated headers
[mesa.git] / src / gallium / drivers / freedreno / adreno_pm4.xml.h
1 #ifndef ADRENO_PM4_XML
2 #define ADRENO_PM4_XML
3
4 /* Autogenerated file, DO NOT EDIT manually!
5
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
9
10 The rules-ng-ng source files this header was generated from are:
11 - /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13)
12 - /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
13 - /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 36805 bytes, from 2018-07-03 19:37:13)
14 - /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 13634 bytes, from 2018-07-03 19:37:13)
15 - /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 42399 bytes, from 2018-09-27 19:00:01)
16 - /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-07-03 19:37:13)
17 - /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
18 - /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147240 bytes, from 2018-09-27 18:43:08)
19 - /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 139337 bytes, from 2018-09-27 19:00:01)
20 - /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07)
21 - /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
22
23 Copyright (C) 2013-2018 by the following authors:
24 - Rob Clark <robdclark@gmail.com> (robclark)
25 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
26
27 Permission is hereby granted, free of charge, to any person obtaining
28 a copy of this software and associated documentation files (the
29 "Software"), to deal in the Software without restriction, including
30 without limitation the rights to use, copy, modify, merge, publish,
31 distribute, sublicense, and/or sell copies of the Software, and to
32 permit persons to whom the Software is furnished to do so, subject to
33 the following conditions:
34
35 The above copyright notice and this permission notice (including the
36 next paragraph) shall be included in all copies or substantial
37 portions of the Software.
38
39 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
40 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
41 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
42 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
43 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
44 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
45 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
46 */
47
48
49 enum vgt_event_type {
50 VS_DEALLOC = 0,
51 PS_DEALLOC = 1,
52 VS_DONE_TS = 2,
53 PS_DONE_TS = 3,
54 CACHE_FLUSH_TS = 4,
55 CONTEXT_DONE = 5,
56 CACHE_FLUSH = 6,
57 HLSQ_FLUSH = 7,
58 VIZQUERY_START = 7,
59 VIZQUERY_END = 8,
60 SC_WAIT_WC = 9,
61 RST_PIX_CNT = 13,
62 RST_VTX_CNT = 14,
63 TILE_FLUSH = 15,
64 STAT_EVENT = 16,
65 CACHE_FLUSH_AND_INV_TS_EVENT = 20,
66 ZPASS_DONE = 21,
67 CACHE_FLUSH_AND_INV_EVENT = 22,
68 PERFCOUNTER_START = 23,
69 PERFCOUNTER_STOP = 24,
70 VS_FETCH_DONE = 27,
71 FACENESS_FLUSH = 28,
72 FLUSH_SO_0 = 17,
73 FLUSH_SO_1 = 18,
74 FLUSH_SO_2 = 19,
75 FLUSH_SO_3 = 20,
76 PC_CCU_INVALIDATE_DEPTH = 24,
77 PC_CCU_INVALIDATE_COLOR = 25,
78 UNK_1C = 28,
79 UNK_1D = 29,
80 BLIT = 30,
81 UNK_25 = 37,
82 LRZ_FLUSH = 38,
83 UNK_2C = 44,
84 UNK_2D = 45,
85 };
86
87 enum pc_di_primtype {
88 DI_PT_NONE = 0,
89 DI_PT_POINTLIST_PSIZE = 1,
90 DI_PT_LINELIST = 2,
91 DI_PT_LINESTRIP = 3,
92 DI_PT_TRILIST = 4,
93 DI_PT_TRIFAN = 5,
94 DI_PT_TRISTRIP = 6,
95 DI_PT_LINELOOP = 7,
96 DI_PT_RECTLIST = 8,
97 DI_PT_POINTLIST = 9,
98 DI_PT_LINE_ADJ = 10,
99 DI_PT_LINESTRIP_ADJ = 11,
100 DI_PT_TRI_ADJ = 12,
101 DI_PT_TRISTRIP_ADJ = 13,
102 };
103
104 enum pc_di_src_sel {
105 DI_SRC_SEL_DMA = 0,
106 DI_SRC_SEL_IMMEDIATE = 1,
107 DI_SRC_SEL_AUTO_INDEX = 2,
108 DI_SRC_SEL_RESERVED = 3,
109 };
110
111 enum pc_di_index_size {
112 INDEX_SIZE_IGN = 0,
113 INDEX_SIZE_16_BIT = 0,
114 INDEX_SIZE_32_BIT = 1,
115 INDEX_SIZE_8_BIT = 2,
116 INDEX_SIZE_INVALID = 0,
117 };
118
119 enum pc_di_vis_cull_mode {
120 IGNORE_VISIBILITY = 0,
121 USE_VISIBILITY = 1,
122 };
123
124 enum adreno_pm4_packet_type {
125 CP_TYPE0_PKT = 0,
126 CP_TYPE1_PKT = 0x40000000,
127 CP_TYPE2_PKT = 0x80000000,
128 CP_TYPE3_PKT = 0xc0000000,
129 CP_TYPE4_PKT = 0x40000000,
130 CP_TYPE7_PKT = 0x70000000,
131 };
132
133 enum adreno_pm4_type3_packets {
134 CP_ME_INIT = 72,
135 CP_NOP = 16,
136 CP_PREEMPT_ENABLE = 28,
137 CP_PREEMPT_TOKEN = 30,
138 CP_INDIRECT_BUFFER = 63,
139 CP_INDIRECT_BUFFER_PFD = 55,
140 CP_WAIT_FOR_IDLE = 38,
141 CP_WAIT_REG_MEM = 60,
142 CP_WAIT_REG_EQ = 82,
143 CP_WAIT_REG_GTE = 83,
144 CP_WAIT_UNTIL_READ = 92,
145 CP_WAIT_IB_PFD_COMPLETE = 93,
146 CP_REG_RMW = 33,
147 CP_SET_BIN_DATA = 47,
148 CP_SET_BIN_DATA5 = 47,
149 CP_REG_TO_MEM = 62,
150 CP_MEM_WRITE = 61,
151 CP_MEM_WRITE_CNTR = 79,
152 CP_COND_EXEC = 68,
153 CP_COND_WRITE = 69,
154 CP_COND_WRITE5 = 69,
155 CP_EVENT_WRITE = 70,
156 CP_EVENT_WRITE_SHD = 88,
157 CP_EVENT_WRITE_CFL = 89,
158 CP_EVENT_WRITE_ZPD = 91,
159 CP_RUN_OPENCL = 49,
160 CP_DRAW_INDX = 34,
161 CP_DRAW_INDX_2 = 54,
162 CP_DRAW_INDX_BIN = 52,
163 CP_DRAW_INDX_2_BIN = 53,
164 CP_VIZ_QUERY = 35,
165 CP_SET_STATE = 37,
166 CP_SET_CONSTANT = 45,
167 CP_IM_LOAD = 39,
168 CP_IM_LOAD_IMMEDIATE = 43,
169 CP_LOAD_CONSTANT_CONTEXT = 46,
170 CP_INVALIDATE_STATE = 59,
171 CP_SET_SHADER_BASES = 74,
172 CP_SET_BIN_MASK = 80,
173 CP_SET_BIN_SELECT = 81,
174 CP_CONTEXT_UPDATE = 94,
175 CP_INTERRUPT = 64,
176 CP_IM_STORE = 44,
177 CP_SET_DRAW_INIT_FLAGS = 75,
178 CP_SET_PROTECTED_MODE = 95,
179 CP_BOOTSTRAP_UCODE = 111,
180 CP_LOAD_STATE = 48,
181 CP_LOAD_STATE4 = 48,
182 CP_COND_INDIRECT_BUFFER_PFE = 58,
183 CP_COND_INDIRECT_BUFFER_PFD = 50,
184 CP_INDIRECT_BUFFER_PFE = 63,
185 CP_SET_BIN = 76,
186 CP_TEST_TWO_MEMS = 113,
187 CP_REG_WR_NO_CTXT = 120,
188 CP_RECORD_PFP_TIMESTAMP = 17,
189 CP_SET_SECURE_MODE = 102,
190 CP_WAIT_FOR_ME = 19,
191 CP_SET_DRAW_STATE = 67,
192 CP_DRAW_INDX_OFFSET = 56,
193 CP_DRAW_INDIRECT = 40,
194 CP_DRAW_INDX_INDIRECT = 41,
195 CP_DRAW_AUTO = 36,
196 CP_UNKNOWN_19 = 25,
197 CP_UNKNOWN_1A = 26,
198 CP_UNKNOWN_4E = 78,
199 CP_WIDE_REG_WRITE = 116,
200 CP_SCRATCH_TO_REG = 77,
201 CP_REG_TO_SCRATCH = 74,
202 CP_WAIT_MEM_WRITES = 18,
203 CP_COND_REG_EXEC = 71,
204 CP_MEM_TO_REG = 66,
205 CP_EXEC_CS_INDIRECT = 65,
206 CP_EXEC_CS = 51,
207 CP_PERFCOUNTER_ACTION = 80,
208 CP_SMMU_TABLE_UPDATE = 83,
209 CP_SET_MARKER = 101,
210 CP_SET_PSEUDO_REG = 86,
211 CP_CONTEXT_REG_BUNCH = 92,
212 CP_YIELD_ENABLE = 28,
213 CP_SKIP_IB2_ENABLE_GLOBAL = 29,
214 CP_SKIP_IB2_ENABLE_LOCAL = 35,
215 CP_SET_SUBDRAW_SIZE = 53,
216 CP_SET_VISIBILITY_OVERRIDE = 100,
217 CP_PREEMPT_ENABLE_GLOBAL = 105,
218 CP_PREEMPT_ENABLE_LOCAL = 106,
219 CP_CONTEXT_SWITCH_YIELD = 107,
220 CP_SET_RENDER_MODE = 108,
221 CP_COMPUTE_CHECKPOINT = 110,
222 CP_MEM_TO_MEM = 115,
223 CP_BLIT = 44,
224 CP_REG_TEST = 57,
225 CP_SET_MODE = 99,
226 CP_LOAD_STATE6_GEOM = 50,
227 CP_LOAD_STATE6_FRAG = 52,
228 IN_IB_PREFETCH_END = 23,
229 IN_SUBBLK_PREFETCH = 31,
230 IN_INSTR_PREFETCH = 32,
231 IN_INSTR_MATCH = 71,
232 IN_CONST_PREFETCH = 73,
233 IN_INCR_UPDT_STATE = 85,
234 IN_INCR_UPDT_CONST = 86,
235 IN_INCR_UPDT_INSTR = 87,
236 PKT4 = 4,
237 CP_UNK_A6XX_14 = 20,
238 CP_UNK_A6XX_36 = 54,
239 CP_UNK_A6XX_55 = 85,
240 UNK_A6XX_6D = 109,
241 };
242
243 enum adreno_state_block {
244 SB_VERT_TEX = 0,
245 SB_VERT_MIPADDR = 1,
246 SB_FRAG_TEX = 2,
247 SB_FRAG_MIPADDR = 3,
248 SB_VERT_SHADER = 4,
249 SB_GEOM_SHADER = 5,
250 SB_FRAG_SHADER = 6,
251 SB_COMPUTE_SHADER = 7,
252 };
253
254 enum adreno_state_type {
255 ST_SHADER = 0,
256 ST_CONSTANTS = 1,
257 };
258
259 enum adreno_state_src {
260 SS_DIRECT = 0,
261 SS_INVALID_ALL_IC = 2,
262 SS_INVALID_PART_IC = 3,
263 SS_INDIRECT = 4,
264 SS_INDIRECT_TCM = 5,
265 SS_INDIRECT_STM = 6,
266 };
267
268 enum a4xx_state_block {
269 SB4_VS_TEX = 0,
270 SB4_HS_TEX = 1,
271 SB4_DS_TEX = 2,
272 SB4_GS_TEX = 3,
273 SB4_FS_TEX = 4,
274 SB4_CS_TEX = 5,
275 SB4_VS_SHADER = 8,
276 SB4_HS_SHADER = 9,
277 SB4_DS_SHADER = 10,
278 SB4_GS_SHADER = 11,
279 SB4_FS_SHADER = 12,
280 SB4_CS_SHADER = 13,
281 SB4_SSBO = 14,
282 SB4_CS_SSBO = 15,
283 };
284
285 enum a4xx_state_type {
286 ST4_SHADER = 0,
287 ST4_CONSTANTS = 1,
288 };
289
290 enum a4xx_state_src {
291 SS4_DIRECT = 0,
292 SS4_INDIRECT = 2,
293 };
294
295 enum a6xx_state_block {
296 SB6_VS_TEX = 0,
297 SB6_HS_TEX = 1,
298 SB6_DS_TEX = 2,
299 SB6_GS_TEX = 3,
300 SB6_FS_TEX = 4,
301 SB6_CS_TEX = 5,
302 SB6_VS_SHADER = 8,
303 SB6_HS_SHADER = 9,
304 SB6_DS_SHADER = 10,
305 SB6_GS_SHADER = 11,
306 SB6_FS_SHADER = 12,
307 SB6_CS_SHADER = 13,
308 SB6_SSBO = 14,
309 SB6_CS_SSBO = 15,
310 };
311
312 enum a6xx_state_type {
313 ST6_SHADER = 0,
314 ST6_CONSTANTS = 1,
315 };
316
317 enum a6xx_state_src {
318 SS6_DIRECT = 0,
319 SS6_INDIRECT = 2,
320 };
321
322 enum a4xx_index_size {
323 INDEX4_SIZE_8_BIT = 0,
324 INDEX4_SIZE_16_BIT = 1,
325 INDEX4_SIZE_32_BIT = 2,
326 };
327
328 enum cp_cond_function {
329 WRITE_ALWAYS = 0,
330 WRITE_LT = 1,
331 WRITE_LE = 2,
332 WRITE_EQ = 3,
333 WRITE_NE = 4,
334 WRITE_GE = 5,
335 WRITE_GT = 6,
336 };
337
338 enum render_mode_cmd {
339 BYPASS = 1,
340 BINNING = 2,
341 GMEM = 3,
342 BLIT2D = 5,
343 BLIT2DSCALE = 7,
344 END2D = 8,
345 };
346
347 enum cp_blit_cmd {
348 BLIT_OP_FILL = 0,
349 BLIT_OP_COPY = 1,
350 BLIT_OP_SCALE = 3,
351 };
352
353 enum a6xx_render_mode {
354 RM6_BYPASS = 1,
355 RM6_BINNING = 2,
356 RM6_GMEM = 4,
357 RM6_BLIT2D = 5,
358 RM6_RESOLVE = 6,
359 };
360
361 enum pseudo_reg {
362 SMMU_INFO = 0,
363 NON_SECURE_SAVE_ADDR = 1,
364 SECURE_SAVE_ADDR = 2,
365 NON_PRIV_SAVE_ADDR = 3,
366 COUNTER = 4,
367 };
368
369 #define REG_CP_LOAD_STATE_0 0x00000000
370 #define CP_LOAD_STATE_0_DST_OFF__MASK 0x0000ffff
371 #define CP_LOAD_STATE_0_DST_OFF__SHIFT 0
372 static inline uint32_t CP_LOAD_STATE_0_DST_OFF(uint32_t val)
373 {
374 return ((val) << CP_LOAD_STATE_0_DST_OFF__SHIFT) & CP_LOAD_STATE_0_DST_OFF__MASK;
375 }
376 #define CP_LOAD_STATE_0_STATE_SRC__MASK 0x00070000
377 #define CP_LOAD_STATE_0_STATE_SRC__SHIFT 16
378 static inline uint32_t CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val)
379 {
380 return ((val) << CP_LOAD_STATE_0_STATE_SRC__SHIFT) & CP_LOAD_STATE_0_STATE_SRC__MASK;
381 }
382 #define CP_LOAD_STATE_0_STATE_BLOCK__MASK 0x00380000
383 #define CP_LOAD_STATE_0_STATE_BLOCK__SHIFT 19
384 static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val)
385 {
386 return ((val) << CP_LOAD_STATE_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE_0_STATE_BLOCK__MASK;
387 }
388 #define CP_LOAD_STATE_0_NUM_UNIT__MASK 0xffc00000
389 #define CP_LOAD_STATE_0_NUM_UNIT__SHIFT 22
390 static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val)
391 {
392 return ((val) << CP_LOAD_STATE_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE_0_NUM_UNIT__MASK;
393 }
394
395 #define REG_CP_LOAD_STATE_1 0x00000001
396 #define CP_LOAD_STATE_1_STATE_TYPE__MASK 0x00000003
397 #define CP_LOAD_STATE_1_STATE_TYPE__SHIFT 0
398 static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val)
399 {
400 return ((val) << CP_LOAD_STATE_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE_1_STATE_TYPE__MASK;
401 }
402 #define CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK 0xfffffffc
403 #define CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT 2
404 static inline uint32_t CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val)
405 {
406 assert(!(val & 0x3));
407 return ((val >> 2) << CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK;
408 }
409
410 #define REG_CP_LOAD_STATE4_0 0x00000000
411 #define CP_LOAD_STATE4_0_DST_OFF__MASK 0x00003fff
412 #define CP_LOAD_STATE4_0_DST_OFF__SHIFT 0
413 static inline uint32_t CP_LOAD_STATE4_0_DST_OFF(uint32_t val)
414 {
415 return ((val) << CP_LOAD_STATE4_0_DST_OFF__SHIFT) & CP_LOAD_STATE4_0_DST_OFF__MASK;
416 }
417 #define CP_LOAD_STATE4_0_STATE_SRC__MASK 0x00030000
418 #define CP_LOAD_STATE4_0_STATE_SRC__SHIFT 16
419 static inline uint32_t CP_LOAD_STATE4_0_STATE_SRC(enum a4xx_state_src val)
420 {
421 return ((val) << CP_LOAD_STATE4_0_STATE_SRC__SHIFT) & CP_LOAD_STATE4_0_STATE_SRC__MASK;
422 }
423 #define CP_LOAD_STATE4_0_STATE_BLOCK__MASK 0x003c0000
424 #define CP_LOAD_STATE4_0_STATE_BLOCK__SHIFT 18
425 static inline uint32_t CP_LOAD_STATE4_0_STATE_BLOCK(enum a4xx_state_block val)
426 {
427 return ((val) << CP_LOAD_STATE4_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE4_0_STATE_BLOCK__MASK;
428 }
429 #define CP_LOAD_STATE4_0_NUM_UNIT__MASK 0xffc00000
430 #define CP_LOAD_STATE4_0_NUM_UNIT__SHIFT 22
431 static inline uint32_t CP_LOAD_STATE4_0_NUM_UNIT(uint32_t val)
432 {
433 return ((val) << CP_LOAD_STATE4_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE4_0_NUM_UNIT__MASK;
434 }
435
436 #define REG_CP_LOAD_STATE4_1 0x00000001
437 #define CP_LOAD_STATE4_1_STATE_TYPE__MASK 0x00000003
438 #define CP_LOAD_STATE4_1_STATE_TYPE__SHIFT 0
439 static inline uint32_t CP_LOAD_STATE4_1_STATE_TYPE(enum a4xx_state_type val)
440 {
441 return ((val) << CP_LOAD_STATE4_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE4_1_STATE_TYPE__MASK;
442 }
443 #define CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK 0xfffffffc
444 #define CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT 2
445 static inline uint32_t CP_LOAD_STATE4_1_EXT_SRC_ADDR(uint32_t val)
446 {
447 assert(!(val & 0x3));
448 return ((val >> 2) << CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK;
449 }
450
451 #define REG_CP_LOAD_STATE4_2 0x00000002
452 #define CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK 0xffffffff
453 #define CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT 0
454 static inline uint32_t CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(uint32_t val)
455 {
456 return ((val) << CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK;
457 }
458
459 #define REG_CP_LOAD_STATE6_0 0x00000000
460 #define CP_LOAD_STATE6_0_DST_OFF__MASK 0x00003fff
461 #define CP_LOAD_STATE6_0_DST_OFF__SHIFT 0
462 static inline uint32_t CP_LOAD_STATE6_0_DST_OFF(uint32_t val)
463 {
464 return ((val) << CP_LOAD_STATE6_0_DST_OFF__SHIFT) & CP_LOAD_STATE6_0_DST_OFF__MASK;
465 }
466 #define CP_LOAD_STATE6_0_STATE_TYPE__MASK 0x00004000
467 #define CP_LOAD_STATE6_0_STATE_TYPE__SHIFT 14
468 static inline uint32_t CP_LOAD_STATE6_0_STATE_TYPE(enum a6xx_state_type val)
469 {
470 return ((val) << CP_LOAD_STATE6_0_STATE_TYPE__SHIFT) & CP_LOAD_STATE6_0_STATE_TYPE__MASK;
471 }
472 #define CP_LOAD_STATE6_0_STATE_SRC__MASK 0x00030000
473 #define CP_LOAD_STATE6_0_STATE_SRC__SHIFT 16
474 static inline uint32_t CP_LOAD_STATE6_0_STATE_SRC(enum a6xx_state_src val)
475 {
476 return ((val) << CP_LOAD_STATE6_0_STATE_SRC__SHIFT) & CP_LOAD_STATE6_0_STATE_SRC__MASK;
477 }
478 #define CP_LOAD_STATE6_0_STATE_BLOCK__MASK 0x003c0000
479 #define CP_LOAD_STATE6_0_STATE_BLOCK__SHIFT 18
480 static inline uint32_t CP_LOAD_STATE6_0_STATE_BLOCK(enum a6xx_state_block val)
481 {
482 return ((val) << CP_LOAD_STATE6_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE6_0_STATE_BLOCK__MASK;
483 }
484 #define CP_LOAD_STATE6_0_NUM_UNIT__MASK 0xffc00000
485 #define CP_LOAD_STATE6_0_NUM_UNIT__SHIFT 22
486 static inline uint32_t CP_LOAD_STATE6_0_NUM_UNIT(uint32_t val)
487 {
488 return ((val) << CP_LOAD_STATE6_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE6_0_NUM_UNIT__MASK;
489 }
490
491 #define REG_CP_LOAD_STATE6_1 0x00000001
492 #define CP_LOAD_STATE6_1_EXT_SRC_ADDR__MASK 0xfffffffc
493 #define CP_LOAD_STATE6_1_EXT_SRC_ADDR__SHIFT 2
494 static inline uint32_t CP_LOAD_STATE6_1_EXT_SRC_ADDR(uint32_t val)
495 {
496 assert(!(val & 0x3));
497 return ((val >> 2) << CP_LOAD_STATE6_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE6_1_EXT_SRC_ADDR__MASK;
498 }
499
500 #define REG_CP_LOAD_STATE6_2 0x00000002
501 #define CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__MASK 0xffffffff
502 #define CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__SHIFT 0
503 static inline uint32_t CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(uint32_t val)
504 {
505 return ((val) << CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI__MASK;
506 }
507
508 #define REG_CP_DRAW_INDX_0 0x00000000
509 #define CP_DRAW_INDX_0_VIZ_QUERY__MASK 0xffffffff
510 #define CP_DRAW_INDX_0_VIZ_QUERY__SHIFT 0
511 static inline uint32_t CP_DRAW_INDX_0_VIZ_QUERY(uint32_t val)
512 {
513 return ((val) << CP_DRAW_INDX_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_0_VIZ_QUERY__MASK;
514 }
515
516 #define REG_CP_DRAW_INDX_1 0x00000001
517 #define CP_DRAW_INDX_1_PRIM_TYPE__MASK 0x0000003f
518 #define CP_DRAW_INDX_1_PRIM_TYPE__SHIFT 0
519 static inline uint32_t CP_DRAW_INDX_1_PRIM_TYPE(enum pc_di_primtype val)
520 {
521 return ((val) << CP_DRAW_INDX_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_1_PRIM_TYPE__MASK;
522 }
523 #define CP_DRAW_INDX_1_SOURCE_SELECT__MASK 0x000000c0
524 #define CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT 6
525 static inline uint32_t CP_DRAW_INDX_1_SOURCE_SELECT(enum pc_di_src_sel val)
526 {
527 return ((val) << CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_1_SOURCE_SELECT__MASK;
528 }
529 #define CP_DRAW_INDX_1_VIS_CULL__MASK 0x00000600
530 #define CP_DRAW_INDX_1_VIS_CULL__SHIFT 9
531 static inline uint32_t CP_DRAW_INDX_1_VIS_CULL(enum pc_di_vis_cull_mode val)
532 {
533 return ((val) << CP_DRAW_INDX_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_1_VIS_CULL__MASK;
534 }
535 #define CP_DRAW_INDX_1_INDEX_SIZE__MASK 0x00000800
536 #define CP_DRAW_INDX_1_INDEX_SIZE__SHIFT 11
537 static inline uint32_t CP_DRAW_INDX_1_INDEX_SIZE(enum pc_di_index_size val)
538 {
539 return ((val) << CP_DRAW_INDX_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_1_INDEX_SIZE__MASK;
540 }
541 #define CP_DRAW_INDX_1_NOT_EOP 0x00001000
542 #define CP_DRAW_INDX_1_SMALL_INDEX 0x00002000
543 #define CP_DRAW_INDX_1_PRE_DRAW_INITIATOR_ENABLE 0x00004000
544 #define CP_DRAW_INDX_1_NUM_INSTANCES__MASK 0xff000000
545 #define CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT 24
546 static inline uint32_t CP_DRAW_INDX_1_NUM_INSTANCES(uint32_t val)
547 {
548 return ((val) << CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_1_NUM_INSTANCES__MASK;
549 }
550
551 #define REG_CP_DRAW_INDX_2 0x00000002
552 #define CP_DRAW_INDX_2_NUM_INDICES__MASK 0xffffffff
553 #define CP_DRAW_INDX_2_NUM_INDICES__SHIFT 0
554 static inline uint32_t CP_DRAW_INDX_2_NUM_INDICES(uint32_t val)
555 {
556 return ((val) << CP_DRAW_INDX_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_NUM_INDICES__MASK;
557 }
558
559 #define REG_CP_DRAW_INDX_3 0x00000003
560 #define CP_DRAW_INDX_3_INDX_BASE__MASK 0xffffffff
561 #define CP_DRAW_INDX_3_INDX_BASE__SHIFT 0
562 static inline uint32_t CP_DRAW_INDX_3_INDX_BASE(uint32_t val)
563 {
564 return ((val) << CP_DRAW_INDX_3_INDX_BASE__SHIFT) & CP_DRAW_INDX_3_INDX_BASE__MASK;
565 }
566
567 #define REG_CP_DRAW_INDX_4 0x00000004
568 #define CP_DRAW_INDX_4_INDX_SIZE__MASK 0xffffffff
569 #define CP_DRAW_INDX_4_INDX_SIZE__SHIFT 0
570 static inline uint32_t CP_DRAW_INDX_4_INDX_SIZE(uint32_t val)
571 {
572 return ((val) << CP_DRAW_INDX_4_INDX_SIZE__SHIFT) & CP_DRAW_INDX_4_INDX_SIZE__MASK;
573 }
574
575 #define REG_CP_DRAW_INDX_2_0 0x00000000
576 #define CP_DRAW_INDX_2_0_VIZ_QUERY__MASK 0xffffffff
577 #define CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT 0
578 static inline uint32_t CP_DRAW_INDX_2_0_VIZ_QUERY(uint32_t val)
579 {
580 return ((val) << CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_2_0_VIZ_QUERY__MASK;
581 }
582
583 #define REG_CP_DRAW_INDX_2_1 0x00000001
584 #define CP_DRAW_INDX_2_1_PRIM_TYPE__MASK 0x0000003f
585 #define CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT 0
586 static inline uint32_t CP_DRAW_INDX_2_1_PRIM_TYPE(enum pc_di_primtype val)
587 {
588 return ((val) << CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_2_1_PRIM_TYPE__MASK;
589 }
590 #define CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK 0x000000c0
591 #define CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT 6
592 static inline uint32_t CP_DRAW_INDX_2_1_SOURCE_SELECT(enum pc_di_src_sel val)
593 {
594 return ((val) << CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK;
595 }
596 #define CP_DRAW_INDX_2_1_VIS_CULL__MASK 0x00000600
597 #define CP_DRAW_INDX_2_1_VIS_CULL__SHIFT 9
598 static inline uint32_t CP_DRAW_INDX_2_1_VIS_CULL(enum pc_di_vis_cull_mode val)
599 {
600 return ((val) << CP_DRAW_INDX_2_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_2_1_VIS_CULL__MASK;
601 }
602 #define CP_DRAW_INDX_2_1_INDEX_SIZE__MASK 0x00000800
603 #define CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT 11
604 static inline uint32_t CP_DRAW_INDX_2_1_INDEX_SIZE(enum pc_di_index_size val)
605 {
606 return ((val) << CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_2_1_INDEX_SIZE__MASK;
607 }
608 #define CP_DRAW_INDX_2_1_NOT_EOP 0x00001000
609 #define CP_DRAW_INDX_2_1_SMALL_INDEX 0x00002000
610 #define CP_DRAW_INDX_2_1_PRE_DRAW_INITIATOR_ENABLE 0x00004000
611 #define CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK 0xff000000
612 #define CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT 24
613 static inline uint32_t CP_DRAW_INDX_2_1_NUM_INSTANCES(uint32_t val)
614 {
615 return ((val) << CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK;
616 }
617
618 #define REG_CP_DRAW_INDX_2_2 0x00000002
619 #define CP_DRAW_INDX_2_2_NUM_INDICES__MASK 0xffffffff
620 #define CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT 0
621 static inline uint32_t CP_DRAW_INDX_2_2_NUM_INDICES(uint32_t val)
622 {
623 return ((val) << CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_2_NUM_INDICES__MASK;
624 }
625
626 #define REG_CP_DRAW_INDX_OFFSET_0 0x00000000
627 #define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK 0x0000003f
628 #define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT 0
629 static inline uint32_t CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(enum pc_di_primtype val)
630 {
631 return ((val) << CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK;
632 }
633 #define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK 0x000000c0
634 #define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT 6
635 static inline uint32_t CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel val)
636 {
637 return ((val) << CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK;
638 }
639 #define CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK 0x00000300
640 #define CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT 8
641 static inline uint32_t CP_DRAW_INDX_OFFSET_0_VIS_CULL(enum pc_di_vis_cull_mode val)
642 {
643 return ((val) << CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT) & CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK;
644 }
645 #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK 0x00000c00
646 #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT 10
647 static inline uint32_t CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum a4xx_index_size val)
648 {
649 return ((val) << CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK;
650 }
651 #define CP_DRAW_INDX_OFFSET_0_TESS_MODE__MASK 0x01f00000
652 #define CP_DRAW_INDX_OFFSET_0_TESS_MODE__SHIFT 20
653 static inline uint32_t CP_DRAW_INDX_OFFSET_0_TESS_MODE(uint32_t val)
654 {
655 return ((val) << CP_DRAW_INDX_OFFSET_0_TESS_MODE__SHIFT) & CP_DRAW_INDX_OFFSET_0_TESS_MODE__MASK;
656 }
657
658 #define REG_CP_DRAW_INDX_OFFSET_1 0x00000001
659 #define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK 0xffffffff
660 #define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT 0
661 static inline uint32_t CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES(uint32_t val)
662 {
663 return ((val) << CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK;
664 }
665
666 #define REG_CP_DRAW_INDX_OFFSET_2 0x00000002
667 #define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK 0xffffffff
668 #define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT 0
669 static inline uint32_t CP_DRAW_INDX_OFFSET_2_NUM_INDICES(uint32_t val)
670 {
671 return ((val) << CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK;
672 }
673
674 #define REG_CP_DRAW_INDX_OFFSET_3 0x00000003
675
676 #define REG_CP_DRAW_INDX_OFFSET_4 0x00000004
677 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK 0xffffffff
678 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT 0
679 static inline uint32_t CP_DRAW_INDX_OFFSET_4_INDX_BASE(uint32_t val)
680 {
681 return ((val) << CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT) & CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK;
682 }
683
684 #define REG_CP_DRAW_INDX_OFFSET_5 0x00000005
685 #define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK 0xffffffff
686 #define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT 0
687 static inline uint32_t CP_DRAW_INDX_OFFSET_5_INDX_SIZE(uint32_t val)
688 {
689 return ((val) << CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK;
690 }
691
692 #define REG_A4XX_CP_DRAW_INDIRECT_0 0x00000000
693 #define A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__MASK 0x0000003f
694 #define A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT 0
695 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val)
696 {
697 return ((val) << A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__MASK;
698 }
699 #define A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__MASK 0x000000c0
700 #define A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__SHIFT 6
701 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val)
702 {
703 return ((val) << A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__MASK;
704 }
705 #define A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__MASK 0x00000300
706 #define A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__SHIFT 8
707 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val)
708 {
709 return ((val) << A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__MASK;
710 }
711 #define A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__MASK 0x00000c00
712 #define A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT 10
713 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val)
714 {
715 return ((val) << A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__MASK;
716 }
717 #define A4XX_CP_DRAW_INDIRECT_0_TESS_MODE__MASK 0x01f00000
718 #define A4XX_CP_DRAW_INDIRECT_0_TESS_MODE__SHIFT 20
719 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_TESS_MODE(uint32_t val)
720 {
721 return ((val) << A4XX_CP_DRAW_INDIRECT_0_TESS_MODE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_TESS_MODE__MASK;
722 }
723
724 #define REG_A4XX_CP_DRAW_INDIRECT_1 0x00000001
725 #define A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK 0xffffffff
726 #define A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT 0
727 static inline uint32_t A4XX_CP_DRAW_INDIRECT_1_INDIRECT(uint32_t val)
728 {
729 return ((val) << A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT) & A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK;
730 }
731
732
733 #define REG_A5XX_CP_DRAW_INDIRECT_2 0x00000002
734 #define A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK 0xffffffff
735 #define A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT 0
736 static inline uint32_t A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI(uint32_t val)
737 {
738 return ((val) << A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT) & A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK;
739 }
740
741 #define REG_A4XX_CP_DRAW_INDX_INDIRECT_0 0x00000000
742 #define A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__MASK 0x0000003f
743 #define A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT 0
744 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val)
745 {
746 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__MASK;
747 }
748 #define A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__MASK 0x000000c0
749 #define A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__SHIFT 6
750 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val)
751 {
752 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__MASK;
753 }
754 #define A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__MASK 0x00000300
755 #define A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__SHIFT 8
756 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val)
757 {
758 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__MASK;
759 }
760 #define A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__MASK 0x00000c00
761 #define A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT 10
762 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val)
763 {
764 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__MASK;
765 }
766 #define A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE__MASK 0x01f00000
767 #define A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE__SHIFT 20
768 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE(uint32_t val)
769 {
770 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE__MASK;
771 }
772
773
774 #define REG_A4XX_CP_DRAW_INDX_INDIRECT_1 0x00000001
775 #define A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__MASK 0xffffffff
776 #define A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__SHIFT 0
777 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE(uint32_t val)
778 {
779 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__MASK;
780 }
781
782 #define REG_A4XX_CP_DRAW_INDX_INDIRECT_2 0x00000002
783 #define A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__MASK 0xffffffff
784 #define A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__SHIFT 0
785 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE(uint32_t val)
786 {
787 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__MASK;
788 }
789
790 #define REG_A4XX_CP_DRAW_INDX_INDIRECT_3 0x00000003
791 #define A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__MASK 0xffffffff
792 #define A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__SHIFT 0
793 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT(uint32_t val)
794 {
795 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__MASK;
796 }
797
798
799 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_1 0x00000001
800 #define A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__MASK 0xffffffff
801 #define A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT 0
802 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO(uint32_t val)
803 {
804 return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__MASK;
805 }
806
807 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_2 0x00000002
808 #define A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__MASK 0xffffffff
809 #define A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT 0
810 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI(uint32_t val)
811 {
812 return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__MASK;
813 }
814
815 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_3 0x00000003
816 #define A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__MASK 0xffffffff
817 #define A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT 0
818 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(uint32_t val)
819 {
820 return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__MASK;
821 }
822
823 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_4 0x00000004
824 #define A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__MASK 0xffffffff
825 #define A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT 0
826 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO(uint32_t val)
827 {
828 return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__MASK;
829 }
830
831 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_5 0x00000005
832 #define A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__MASK 0xffffffff
833 #define A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT 0
834 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI(uint32_t val)
835 {
836 return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__MASK;
837 }
838
839 static inline uint32_t REG_CP_SET_DRAW_STATE_(uint32_t i0) { return 0x00000000 + 0x3*i0; }
840
841 static inline uint32_t REG_CP_SET_DRAW_STATE__0(uint32_t i0) { return 0x00000000 + 0x3*i0; }
842 #define CP_SET_DRAW_STATE__0_COUNT__MASK 0x0000ffff
843 #define CP_SET_DRAW_STATE__0_COUNT__SHIFT 0
844 static inline uint32_t CP_SET_DRAW_STATE__0_COUNT(uint32_t val)
845 {
846 return ((val) << CP_SET_DRAW_STATE__0_COUNT__SHIFT) & CP_SET_DRAW_STATE__0_COUNT__MASK;
847 }
848 #define CP_SET_DRAW_STATE__0_DIRTY 0x00010000
849 #define CP_SET_DRAW_STATE__0_DISABLE 0x00020000
850 #define CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS 0x00040000
851 #define CP_SET_DRAW_STATE__0_LOAD_IMMED 0x00080000
852 #define CP_SET_DRAW_STATE__0_ENABLE_MASK__MASK 0x00f00000
853 #define CP_SET_DRAW_STATE__0_ENABLE_MASK__SHIFT 20
854 static inline uint32_t CP_SET_DRAW_STATE__0_ENABLE_MASK(uint32_t val)
855 {
856 return ((val) << CP_SET_DRAW_STATE__0_ENABLE_MASK__SHIFT) & CP_SET_DRAW_STATE__0_ENABLE_MASK__MASK;
857 }
858 #define CP_SET_DRAW_STATE__0_GROUP_ID__MASK 0x1f000000
859 #define CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT 24
860 static inline uint32_t CP_SET_DRAW_STATE__0_GROUP_ID(uint32_t val)
861 {
862 return ((val) << CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT) & CP_SET_DRAW_STATE__0_GROUP_ID__MASK;
863 }
864
865 static inline uint32_t REG_CP_SET_DRAW_STATE__1(uint32_t i0) { return 0x00000001 + 0x3*i0; }
866 #define CP_SET_DRAW_STATE__1_ADDR_LO__MASK 0xffffffff
867 #define CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT 0
868 static inline uint32_t CP_SET_DRAW_STATE__1_ADDR_LO(uint32_t val)
869 {
870 return ((val) << CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT) & CP_SET_DRAW_STATE__1_ADDR_LO__MASK;
871 }
872
873 static inline uint32_t REG_CP_SET_DRAW_STATE__2(uint32_t i0) { return 0x00000002 + 0x3*i0; }
874 #define CP_SET_DRAW_STATE__2_ADDR_HI__MASK 0xffffffff
875 #define CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT 0
876 static inline uint32_t CP_SET_DRAW_STATE__2_ADDR_HI(uint32_t val)
877 {
878 return ((val) << CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT) & CP_SET_DRAW_STATE__2_ADDR_HI__MASK;
879 }
880
881 #define REG_CP_SET_BIN_0 0x00000000
882
883 #define REG_CP_SET_BIN_1 0x00000001
884 #define CP_SET_BIN_1_X1__MASK 0x0000ffff
885 #define CP_SET_BIN_1_X1__SHIFT 0
886 static inline uint32_t CP_SET_BIN_1_X1(uint32_t val)
887 {
888 return ((val) << CP_SET_BIN_1_X1__SHIFT) & CP_SET_BIN_1_X1__MASK;
889 }
890 #define CP_SET_BIN_1_Y1__MASK 0xffff0000
891 #define CP_SET_BIN_1_Y1__SHIFT 16
892 static inline uint32_t CP_SET_BIN_1_Y1(uint32_t val)
893 {
894 return ((val) << CP_SET_BIN_1_Y1__SHIFT) & CP_SET_BIN_1_Y1__MASK;
895 }
896
897 #define REG_CP_SET_BIN_2 0x00000002
898 #define CP_SET_BIN_2_X2__MASK 0x0000ffff
899 #define CP_SET_BIN_2_X2__SHIFT 0
900 static inline uint32_t CP_SET_BIN_2_X2(uint32_t val)
901 {
902 return ((val) << CP_SET_BIN_2_X2__SHIFT) & CP_SET_BIN_2_X2__MASK;
903 }
904 #define CP_SET_BIN_2_Y2__MASK 0xffff0000
905 #define CP_SET_BIN_2_Y2__SHIFT 16
906 static inline uint32_t CP_SET_BIN_2_Y2(uint32_t val)
907 {
908 return ((val) << CP_SET_BIN_2_Y2__SHIFT) & CP_SET_BIN_2_Y2__MASK;
909 }
910
911 #define REG_CP_SET_BIN_DATA_0 0x00000000
912 #define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK 0xffffffff
913 #define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT 0
914 static inline uint32_t CP_SET_BIN_DATA_0_BIN_DATA_ADDR(uint32_t val)
915 {
916 return ((val) << CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT) & CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK;
917 }
918
919 #define REG_CP_SET_BIN_DATA_1 0x00000001
920 #define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK 0xffffffff
921 #define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT 0
922 static inline uint32_t CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS(uint32_t val)
923 {
924 return ((val) << CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT) & CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK;
925 }
926
927 #define REG_CP_SET_BIN_DATA5_0 0x00000000
928 #define CP_SET_BIN_DATA5_0_VSC_SIZE__MASK 0x003f0000
929 #define CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT 16
930 static inline uint32_t CP_SET_BIN_DATA5_0_VSC_SIZE(uint32_t val)
931 {
932 return ((val) << CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT) & CP_SET_BIN_DATA5_0_VSC_SIZE__MASK;
933 }
934 #define CP_SET_BIN_DATA5_0_VSC_N__MASK 0x07c00000
935 #define CP_SET_BIN_DATA5_0_VSC_N__SHIFT 22
936 static inline uint32_t CP_SET_BIN_DATA5_0_VSC_N(uint32_t val)
937 {
938 return ((val) << CP_SET_BIN_DATA5_0_VSC_N__SHIFT) & CP_SET_BIN_DATA5_0_VSC_N__MASK;
939 }
940
941 #define REG_CP_SET_BIN_DATA5_1 0x00000001
942 #define CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK 0xffffffff
943 #define CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT 0
944 static inline uint32_t CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO(uint32_t val)
945 {
946 return ((val) << CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT) & CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK;
947 }
948
949 #define REG_CP_SET_BIN_DATA5_2 0x00000002
950 #define CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK 0xffffffff
951 #define CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT 0
952 static inline uint32_t CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI(uint32_t val)
953 {
954 return ((val) << CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT) & CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK;
955 }
956
957 #define REG_CP_SET_BIN_DATA5_3 0x00000003
958 #define CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK 0xffffffff
959 #define CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT 0
960 static inline uint32_t CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO(uint32_t val)
961 {
962 return ((val) << CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT) & CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK;
963 }
964
965 #define REG_CP_SET_BIN_DATA5_4 0x00000004
966 #define CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK 0xffffffff
967 #define CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT 0
968 static inline uint32_t CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI(uint32_t val)
969 {
970 return ((val) << CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT) & CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK;
971 }
972
973 #define REG_CP_SET_BIN_DATA5_5 0x00000005
974 #define CP_SET_BIN_DATA5_5_BIN_DATA_ADDR2_LO__MASK 0xffffffff
975 #define CP_SET_BIN_DATA5_5_BIN_DATA_ADDR2_LO__SHIFT 0
976 static inline uint32_t CP_SET_BIN_DATA5_5_BIN_DATA_ADDR2_LO(uint32_t val)
977 {
978 return ((val) << CP_SET_BIN_DATA5_5_BIN_DATA_ADDR2_LO__SHIFT) & CP_SET_BIN_DATA5_5_BIN_DATA_ADDR2_LO__MASK;
979 }
980
981 #define REG_CP_SET_BIN_DATA5_6 0x00000006
982 #define CP_SET_BIN_DATA5_6_BIN_DATA_ADDR2_LO__MASK 0xffffffff
983 #define CP_SET_BIN_DATA5_6_BIN_DATA_ADDR2_LO__SHIFT 0
984 static inline uint32_t CP_SET_BIN_DATA5_6_BIN_DATA_ADDR2_LO(uint32_t val)
985 {
986 return ((val) << CP_SET_BIN_DATA5_6_BIN_DATA_ADDR2_LO__SHIFT) & CP_SET_BIN_DATA5_6_BIN_DATA_ADDR2_LO__MASK;
987 }
988
989 #define REG_CP_REG_TO_MEM_0 0x00000000
990 #define CP_REG_TO_MEM_0_REG__MASK 0x0000ffff
991 #define CP_REG_TO_MEM_0_REG__SHIFT 0
992 static inline uint32_t CP_REG_TO_MEM_0_REG(uint32_t val)
993 {
994 return ((val) << CP_REG_TO_MEM_0_REG__SHIFT) & CP_REG_TO_MEM_0_REG__MASK;
995 }
996 #define CP_REG_TO_MEM_0_CNT__MASK 0x3ff80000
997 #define CP_REG_TO_MEM_0_CNT__SHIFT 19
998 static inline uint32_t CP_REG_TO_MEM_0_CNT(uint32_t val)
999 {
1000 return ((val) << CP_REG_TO_MEM_0_CNT__SHIFT) & CP_REG_TO_MEM_0_CNT__MASK;
1001 }
1002 #define CP_REG_TO_MEM_0_64B 0x40000000
1003 #define CP_REG_TO_MEM_0_ACCUMULATE 0x80000000
1004
1005 #define REG_CP_REG_TO_MEM_1 0x00000001
1006 #define CP_REG_TO_MEM_1_DEST__MASK 0xffffffff
1007 #define CP_REG_TO_MEM_1_DEST__SHIFT 0
1008 static inline uint32_t CP_REG_TO_MEM_1_DEST(uint32_t val)
1009 {
1010 return ((val) << CP_REG_TO_MEM_1_DEST__SHIFT) & CP_REG_TO_MEM_1_DEST__MASK;
1011 }
1012
1013 #define REG_CP_REG_TO_MEM_2 0x00000002
1014 #define CP_REG_TO_MEM_2_DEST_HI__MASK 0xffffffff
1015 #define CP_REG_TO_MEM_2_DEST_HI__SHIFT 0
1016 static inline uint32_t CP_REG_TO_MEM_2_DEST_HI(uint32_t val)
1017 {
1018 return ((val) << CP_REG_TO_MEM_2_DEST_HI__SHIFT) & CP_REG_TO_MEM_2_DEST_HI__MASK;
1019 }
1020
1021 #define REG_CP_MEM_TO_REG_0 0x00000000
1022 #define CP_MEM_TO_REG_0_REG__MASK 0x0000ffff
1023 #define CP_MEM_TO_REG_0_REG__SHIFT 0
1024 static inline uint32_t CP_MEM_TO_REG_0_REG(uint32_t val)
1025 {
1026 return ((val) << CP_MEM_TO_REG_0_REG__SHIFT) & CP_MEM_TO_REG_0_REG__MASK;
1027 }
1028 #define CP_MEM_TO_REG_0_CNT__MASK 0x3ff80000
1029 #define CP_MEM_TO_REG_0_CNT__SHIFT 19
1030 static inline uint32_t CP_MEM_TO_REG_0_CNT(uint32_t val)
1031 {
1032 return ((val) << CP_MEM_TO_REG_0_CNT__SHIFT) & CP_MEM_TO_REG_0_CNT__MASK;
1033 }
1034 #define CP_MEM_TO_REG_0_64B 0x40000000
1035 #define CP_MEM_TO_REG_0_ACCUMULATE 0x80000000
1036
1037 #define REG_CP_MEM_TO_REG_1 0x00000001
1038 #define CP_MEM_TO_REG_1_SRC__MASK 0xffffffff
1039 #define CP_MEM_TO_REG_1_SRC__SHIFT 0
1040 static inline uint32_t CP_MEM_TO_REG_1_SRC(uint32_t val)
1041 {
1042 return ((val) << CP_MEM_TO_REG_1_SRC__SHIFT) & CP_MEM_TO_REG_1_SRC__MASK;
1043 }
1044
1045 #define REG_CP_MEM_TO_REG_2 0x00000002
1046 #define CP_MEM_TO_REG_2_SRC_HI__MASK 0xffffffff
1047 #define CP_MEM_TO_REG_2_SRC_HI__SHIFT 0
1048 static inline uint32_t CP_MEM_TO_REG_2_SRC_HI(uint32_t val)
1049 {
1050 return ((val) << CP_MEM_TO_REG_2_SRC_HI__SHIFT) & CP_MEM_TO_REG_2_SRC_HI__MASK;
1051 }
1052
1053 #define REG_CP_MEM_TO_MEM_0 0x00000000
1054 #define CP_MEM_TO_MEM_0_NEG_A 0x00000001
1055 #define CP_MEM_TO_MEM_0_NEG_B 0x00000002
1056 #define CP_MEM_TO_MEM_0_NEG_C 0x00000004
1057 #define CP_MEM_TO_MEM_0_DOUBLE 0x20000000
1058
1059 #define REG_CP_COND_WRITE_0 0x00000000
1060 #define CP_COND_WRITE_0_FUNCTION__MASK 0x00000007
1061 #define CP_COND_WRITE_0_FUNCTION__SHIFT 0
1062 static inline uint32_t CP_COND_WRITE_0_FUNCTION(enum cp_cond_function val)
1063 {
1064 return ((val) << CP_COND_WRITE_0_FUNCTION__SHIFT) & CP_COND_WRITE_0_FUNCTION__MASK;
1065 }
1066 #define CP_COND_WRITE_0_POLL_MEMORY 0x00000010
1067 #define CP_COND_WRITE_0_WRITE_MEMORY 0x00000100
1068
1069 #define REG_CP_COND_WRITE_1 0x00000001
1070 #define CP_COND_WRITE_1_POLL_ADDR__MASK 0xffffffff
1071 #define CP_COND_WRITE_1_POLL_ADDR__SHIFT 0
1072 static inline uint32_t CP_COND_WRITE_1_POLL_ADDR(uint32_t val)
1073 {
1074 return ((val) << CP_COND_WRITE_1_POLL_ADDR__SHIFT) & CP_COND_WRITE_1_POLL_ADDR__MASK;
1075 }
1076
1077 #define REG_CP_COND_WRITE_2 0x00000002
1078 #define CP_COND_WRITE_2_REF__MASK 0xffffffff
1079 #define CP_COND_WRITE_2_REF__SHIFT 0
1080 static inline uint32_t CP_COND_WRITE_2_REF(uint32_t val)
1081 {
1082 return ((val) << CP_COND_WRITE_2_REF__SHIFT) & CP_COND_WRITE_2_REF__MASK;
1083 }
1084
1085 #define REG_CP_COND_WRITE_3 0x00000003
1086 #define CP_COND_WRITE_3_MASK__MASK 0xffffffff
1087 #define CP_COND_WRITE_3_MASK__SHIFT 0
1088 static inline uint32_t CP_COND_WRITE_3_MASK(uint32_t val)
1089 {
1090 return ((val) << CP_COND_WRITE_3_MASK__SHIFT) & CP_COND_WRITE_3_MASK__MASK;
1091 }
1092
1093 #define REG_CP_COND_WRITE_4 0x00000004
1094 #define CP_COND_WRITE_4_WRITE_ADDR__MASK 0xffffffff
1095 #define CP_COND_WRITE_4_WRITE_ADDR__SHIFT 0
1096 static inline uint32_t CP_COND_WRITE_4_WRITE_ADDR(uint32_t val)
1097 {
1098 return ((val) << CP_COND_WRITE_4_WRITE_ADDR__SHIFT) & CP_COND_WRITE_4_WRITE_ADDR__MASK;
1099 }
1100
1101 #define REG_CP_COND_WRITE_5 0x00000005
1102 #define CP_COND_WRITE_5_WRITE_DATA__MASK 0xffffffff
1103 #define CP_COND_WRITE_5_WRITE_DATA__SHIFT 0
1104 static inline uint32_t CP_COND_WRITE_5_WRITE_DATA(uint32_t val)
1105 {
1106 return ((val) << CP_COND_WRITE_5_WRITE_DATA__SHIFT) & CP_COND_WRITE_5_WRITE_DATA__MASK;
1107 }
1108
1109 #define REG_CP_COND_WRITE5_0 0x00000000
1110 #define CP_COND_WRITE5_0_FUNCTION__MASK 0x00000007
1111 #define CP_COND_WRITE5_0_FUNCTION__SHIFT 0
1112 static inline uint32_t CP_COND_WRITE5_0_FUNCTION(enum cp_cond_function val)
1113 {
1114 return ((val) << CP_COND_WRITE5_0_FUNCTION__SHIFT) & CP_COND_WRITE5_0_FUNCTION__MASK;
1115 }
1116 #define CP_COND_WRITE5_0_POLL_MEMORY 0x00000010
1117 #define CP_COND_WRITE5_0_WRITE_MEMORY 0x00000100
1118
1119 #define REG_CP_COND_WRITE5_1 0x00000001
1120 #define CP_COND_WRITE5_1_POLL_ADDR_LO__MASK 0xffffffff
1121 #define CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT 0
1122 static inline uint32_t CP_COND_WRITE5_1_POLL_ADDR_LO(uint32_t val)
1123 {
1124 return ((val) << CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT) & CP_COND_WRITE5_1_POLL_ADDR_LO__MASK;
1125 }
1126
1127 #define REG_CP_COND_WRITE5_2 0x00000002
1128 #define CP_COND_WRITE5_2_POLL_ADDR_HI__MASK 0xffffffff
1129 #define CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT 0
1130 static inline uint32_t CP_COND_WRITE5_2_POLL_ADDR_HI(uint32_t val)
1131 {
1132 return ((val) << CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT) & CP_COND_WRITE5_2_POLL_ADDR_HI__MASK;
1133 }
1134
1135 #define REG_CP_COND_WRITE5_3 0x00000003
1136 #define CP_COND_WRITE5_3_REF__MASK 0xffffffff
1137 #define CP_COND_WRITE5_3_REF__SHIFT 0
1138 static inline uint32_t CP_COND_WRITE5_3_REF(uint32_t val)
1139 {
1140 return ((val) << CP_COND_WRITE5_3_REF__SHIFT) & CP_COND_WRITE5_3_REF__MASK;
1141 }
1142
1143 #define REG_CP_COND_WRITE5_4 0x00000004
1144 #define CP_COND_WRITE5_4_MASK__MASK 0xffffffff
1145 #define CP_COND_WRITE5_4_MASK__SHIFT 0
1146 static inline uint32_t CP_COND_WRITE5_4_MASK(uint32_t val)
1147 {
1148 return ((val) << CP_COND_WRITE5_4_MASK__SHIFT) & CP_COND_WRITE5_4_MASK__MASK;
1149 }
1150
1151 #define REG_CP_COND_WRITE5_5 0x00000005
1152 #define CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK 0xffffffff
1153 #define CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT 0
1154 static inline uint32_t CP_COND_WRITE5_5_WRITE_ADDR_LO(uint32_t val)
1155 {
1156 return ((val) << CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT) & CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK;
1157 }
1158
1159 #define REG_CP_COND_WRITE5_6 0x00000006
1160 #define CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK 0xffffffff
1161 #define CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT 0
1162 static inline uint32_t CP_COND_WRITE5_6_WRITE_ADDR_HI(uint32_t val)
1163 {
1164 return ((val) << CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT) & CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK;
1165 }
1166
1167 #define REG_CP_COND_WRITE5_7 0x00000007
1168 #define CP_COND_WRITE5_7_WRITE_DATA__MASK 0xffffffff
1169 #define CP_COND_WRITE5_7_WRITE_DATA__SHIFT 0
1170 static inline uint32_t CP_COND_WRITE5_7_WRITE_DATA(uint32_t val)
1171 {
1172 return ((val) << CP_COND_WRITE5_7_WRITE_DATA__SHIFT) & CP_COND_WRITE5_7_WRITE_DATA__MASK;
1173 }
1174
1175 #define REG_CP_DISPATCH_COMPUTE_0 0x00000000
1176
1177 #define REG_CP_DISPATCH_COMPUTE_1 0x00000001
1178 #define CP_DISPATCH_COMPUTE_1_X__MASK 0xffffffff
1179 #define CP_DISPATCH_COMPUTE_1_X__SHIFT 0
1180 static inline uint32_t CP_DISPATCH_COMPUTE_1_X(uint32_t val)
1181 {
1182 return ((val) << CP_DISPATCH_COMPUTE_1_X__SHIFT) & CP_DISPATCH_COMPUTE_1_X__MASK;
1183 }
1184
1185 #define REG_CP_DISPATCH_COMPUTE_2 0x00000002
1186 #define CP_DISPATCH_COMPUTE_2_Y__MASK 0xffffffff
1187 #define CP_DISPATCH_COMPUTE_2_Y__SHIFT 0
1188 static inline uint32_t CP_DISPATCH_COMPUTE_2_Y(uint32_t val)
1189 {
1190 return ((val) << CP_DISPATCH_COMPUTE_2_Y__SHIFT) & CP_DISPATCH_COMPUTE_2_Y__MASK;
1191 }
1192
1193 #define REG_CP_DISPATCH_COMPUTE_3 0x00000003
1194 #define CP_DISPATCH_COMPUTE_3_Z__MASK 0xffffffff
1195 #define CP_DISPATCH_COMPUTE_3_Z__SHIFT 0
1196 static inline uint32_t CP_DISPATCH_COMPUTE_3_Z(uint32_t val)
1197 {
1198 return ((val) << CP_DISPATCH_COMPUTE_3_Z__SHIFT) & CP_DISPATCH_COMPUTE_3_Z__MASK;
1199 }
1200
1201 #define REG_CP_SET_RENDER_MODE_0 0x00000000
1202 #define CP_SET_RENDER_MODE_0_MODE__MASK 0x000001ff
1203 #define CP_SET_RENDER_MODE_0_MODE__SHIFT 0
1204 static inline uint32_t CP_SET_RENDER_MODE_0_MODE(enum render_mode_cmd val)
1205 {
1206 return ((val) << CP_SET_RENDER_MODE_0_MODE__SHIFT) & CP_SET_RENDER_MODE_0_MODE__MASK;
1207 }
1208
1209 #define REG_CP_SET_RENDER_MODE_1 0x00000001
1210 #define CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK 0xffffffff
1211 #define CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT 0
1212 static inline uint32_t CP_SET_RENDER_MODE_1_ADDR_0_LO(uint32_t val)
1213 {
1214 return ((val) << CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT) & CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK;
1215 }
1216
1217 #define REG_CP_SET_RENDER_MODE_2 0x00000002
1218 #define CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK 0xffffffff
1219 #define CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT 0
1220 static inline uint32_t CP_SET_RENDER_MODE_2_ADDR_0_HI(uint32_t val)
1221 {
1222 return ((val) << CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT) & CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK;
1223 }
1224
1225 #define REG_CP_SET_RENDER_MODE_3 0x00000003
1226 #define CP_SET_RENDER_MODE_3_VSC_ENABLE 0x00000008
1227 #define CP_SET_RENDER_MODE_3_GMEM_ENABLE 0x00000010
1228
1229 #define REG_CP_SET_RENDER_MODE_4 0x00000004
1230
1231 #define REG_CP_SET_RENDER_MODE_5 0x00000005
1232 #define CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK 0xffffffff
1233 #define CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT 0
1234 static inline uint32_t CP_SET_RENDER_MODE_5_ADDR_1_LEN(uint32_t val)
1235 {
1236 return ((val) << CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT) & CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK;
1237 }
1238
1239 #define REG_CP_SET_RENDER_MODE_6 0x00000006
1240 #define CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK 0xffffffff
1241 #define CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT 0
1242 static inline uint32_t CP_SET_RENDER_MODE_6_ADDR_1_LO(uint32_t val)
1243 {
1244 return ((val) << CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT) & CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK;
1245 }
1246
1247 #define REG_CP_SET_RENDER_MODE_7 0x00000007
1248 #define CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK 0xffffffff
1249 #define CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT 0
1250 static inline uint32_t CP_SET_RENDER_MODE_7_ADDR_1_HI(uint32_t val)
1251 {
1252 return ((val) << CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT) & CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK;
1253 }
1254
1255 #define REG_CP_COMPUTE_CHECKPOINT_0 0x00000000
1256 #define CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MASK 0xffffffff
1257 #define CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT 0
1258 static inline uint32_t CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO(uint32_t val)
1259 {
1260 return ((val) << CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT) & CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MASK;
1261 }
1262
1263 #define REG_CP_COMPUTE_CHECKPOINT_1 0x00000001
1264 #define CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MASK 0xffffffff
1265 #define CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT 0
1266 static inline uint32_t CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI(uint32_t val)
1267 {
1268 return ((val) << CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT) & CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MASK;
1269 }
1270
1271 #define REG_CP_COMPUTE_CHECKPOINT_2 0x00000002
1272
1273 #define REG_CP_COMPUTE_CHECKPOINT_3 0x00000003
1274 #define CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__MASK 0xffffffff
1275 #define CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__SHIFT 0
1276 static inline uint32_t CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN(uint32_t val)
1277 {
1278 return ((val) << CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__SHIFT) & CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__MASK;
1279 }
1280
1281 #define REG_CP_COMPUTE_CHECKPOINT_4 0x00000004
1282
1283 #define REG_CP_COMPUTE_CHECKPOINT_5 0x00000005
1284 #define CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK 0xffffffff
1285 #define CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT 0
1286 static inline uint32_t CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO(uint32_t val)
1287 {
1288 return ((val) << CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT) & CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK;
1289 }
1290
1291 #define REG_CP_COMPUTE_CHECKPOINT_6 0x00000006
1292 #define CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MASK 0xffffffff
1293 #define CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT 0
1294 static inline uint32_t CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI(uint32_t val)
1295 {
1296 return ((val) << CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT) & CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MASK;
1297 }
1298
1299 #define REG_CP_COMPUTE_CHECKPOINT_7 0x00000007
1300
1301 #define REG_CP_PERFCOUNTER_ACTION_0 0x00000000
1302
1303 #define REG_CP_PERFCOUNTER_ACTION_1 0x00000001
1304 #define CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK 0xffffffff
1305 #define CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT 0
1306 static inline uint32_t CP_PERFCOUNTER_ACTION_1_ADDR_0_LO(uint32_t val)
1307 {
1308 return ((val) << CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT) & CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK;
1309 }
1310
1311 #define REG_CP_PERFCOUNTER_ACTION_2 0x00000002
1312 #define CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK 0xffffffff
1313 #define CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT 0
1314 static inline uint32_t CP_PERFCOUNTER_ACTION_2_ADDR_0_HI(uint32_t val)
1315 {
1316 return ((val) << CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT) & CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK;
1317 }
1318
1319 #define REG_CP_EVENT_WRITE_0 0x00000000
1320 #define CP_EVENT_WRITE_0_EVENT__MASK 0x000000ff
1321 #define CP_EVENT_WRITE_0_EVENT__SHIFT 0
1322 static inline uint32_t CP_EVENT_WRITE_0_EVENT(enum vgt_event_type val)
1323 {
1324 return ((val) << CP_EVENT_WRITE_0_EVENT__SHIFT) & CP_EVENT_WRITE_0_EVENT__MASK;
1325 }
1326 #define CP_EVENT_WRITE_0_TIMESTAMP 0x40000000
1327
1328 #define REG_CP_EVENT_WRITE_1 0x00000001
1329 #define CP_EVENT_WRITE_1_ADDR_0_LO__MASK 0xffffffff
1330 #define CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT 0
1331 static inline uint32_t CP_EVENT_WRITE_1_ADDR_0_LO(uint32_t val)
1332 {
1333 return ((val) << CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT) & CP_EVENT_WRITE_1_ADDR_0_LO__MASK;
1334 }
1335
1336 #define REG_CP_EVENT_WRITE_2 0x00000002
1337 #define CP_EVENT_WRITE_2_ADDR_0_HI__MASK 0xffffffff
1338 #define CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT 0
1339 static inline uint32_t CP_EVENT_WRITE_2_ADDR_0_HI(uint32_t val)
1340 {
1341 return ((val) << CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT) & CP_EVENT_WRITE_2_ADDR_0_HI__MASK;
1342 }
1343
1344 #define REG_CP_EVENT_WRITE_3 0x00000003
1345
1346 #define REG_CP_BLIT_0 0x00000000
1347 #define CP_BLIT_0_OP__MASK 0x0000000f
1348 #define CP_BLIT_0_OP__SHIFT 0
1349 static inline uint32_t CP_BLIT_0_OP(enum cp_blit_cmd val)
1350 {
1351 return ((val) << CP_BLIT_0_OP__SHIFT) & CP_BLIT_0_OP__MASK;
1352 }
1353
1354 #define REG_CP_BLIT_1 0x00000001
1355 #define CP_BLIT_1_SRC_X1__MASK 0x00003fff
1356 #define CP_BLIT_1_SRC_X1__SHIFT 0
1357 static inline uint32_t CP_BLIT_1_SRC_X1(uint32_t val)
1358 {
1359 return ((val) << CP_BLIT_1_SRC_X1__SHIFT) & CP_BLIT_1_SRC_X1__MASK;
1360 }
1361 #define CP_BLIT_1_SRC_Y1__MASK 0x3fff0000
1362 #define CP_BLIT_1_SRC_Y1__SHIFT 16
1363 static inline uint32_t CP_BLIT_1_SRC_Y1(uint32_t val)
1364 {
1365 return ((val) << CP_BLIT_1_SRC_Y1__SHIFT) & CP_BLIT_1_SRC_Y1__MASK;
1366 }
1367
1368 #define REG_CP_BLIT_2 0x00000002
1369 #define CP_BLIT_2_SRC_X2__MASK 0x00003fff
1370 #define CP_BLIT_2_SRC_X2__SHIFT 0
1371 static inline uint32_t CP_BLIT_2_SRC_X2(uint32_t val)
1372 {
1373 return ((val) << CP_BLIT_2_SRC_X2__SHIFT) & CP_BLIT_2_SRC_X2__MASK;
1374 }
1375 #define CP_BLIT_2_SRC_Y2__MASK 0x3fff0000
1376 #define CP_BLIT_2_SRC_Y2__SHIFT 16
1377 static inline uint32_t CP_BLIT_2_SRC_Y2(uint32_t val)
1378 {
1379 return ((val) << CP_BLIT_2_SRC_Y2__SHIFT) & CP_BLIT_2_SRC_Y2__MASK;
1380 }
1381
1382 #define REG_CP_BLIT_3 0x00000003
1383 #define CP_BLIT_3_DST_X1__MASK 0x00003fff
1384 #define CP_BLIT_3_DST_X1__SHIFT 0
1385 static inline uint32_t CP_BLIT_3_DST_X1(uint32_t val)
1386 {
1387 return ((val) << CP_BLIT_3_DST_X1__SHIFT) & CP_BLIT_3_DST_X1__MASK;
1388 }
1389 #define CP_BLIT_3_DST_Y1__MASK 0x3fff0000
1390 #define CP_BLIT_3_DST_Y1__SHIFT 16
1391 static inline uint32_t CP_BLIT_3_DST_Y1(uint32_t val)
1392 {
1393 return ((val) << CP_BLIT_3_DST_Y1__SHIFT) & CP_BLIT_3_DST_Y1__MASK;
1394 }
1395
1396 #define REG_CP_BLIT_4 0x00000004
1397 #define CP_BLIT_4_DST_X2__MASK 0x00003fff
1398 #define CP_BLIT_4_DST_X2__SHIFT 0
1399 static inline uint32_t CP_BLIT_4_DST_X2(uint32_t val)
1400 {
1401 return ((val) << CP_BLIT_4_DST_X2__SHIFT) & CP_BLIT_4_DST_X2__MASK;
1402 }
1403 #define CP_BLIT_4_DST_Y2__MASK 0x3fff0000
1404 #define CP_BLIT_4_DST_Y2__SHIFT 16
1405 static inline uint32_t CP_BLIT_4_DST_Y2(uint32_t val)
1406 {
1407 return ((val) << CP_BLIT_4_DST_Y2__SHIFT) & CP_BLIT_4_DST_Y2__MASK;
1408 }
1409
1410 #define REG_CP_EXEC_CS_0 0x00000000
1411
1412 #define REG_CP_EXEC_CS_1 0x00000001
1413 #define CP_EXEC_CS_1_NGROUPS_X__MASK 0xffffffff
1414 #define CP_EXEC_CS_1_NGROUPS_X__SHIFT 0
1415 static inline uint32_t CP_EXEC_CS_1_NGROUPS_X(uint32_t val)
1416 {
1417 return ((val) << CP_EXEC_CS_1_NGROUPS_X__SHIFT) & CP_EXEC_CS_1_NGROUPS_X__MASK;
1418 }
1419
1420 #define REG_CP_EXEC_CS_2 0x00000002
1421 #define CP_EXEC_CS_2_NGROUPS_Y__MASK 0xffffffff
1422 #define CP_EXEC_CS_2_NGROUPS_Y__SHIFT 0
1423 static inline uint32_t CP_EXEC_CS_2_NGROUPS_Y(uint32_t val)
1424 {
1425 return ((val) << CP_EXEC_CS_2_NGROUPS_Y__SHIFT) & CP_EXEC_CS_2_NGROUPS_Y__MASK;
1426 }
1427
1428 #define REG_CP_EXEC_CS_3 0x00000003
1429 #define CP_EXEC_CS_3_NGROUPS_Z__MASK 0xffffffff
1430 #define CP_EXEC_CS_3_NGROUPS_Z__SHIFT 0
1431 static inline uint32_t CP_EXEC_CS_3_NGROUPS_Z(uint32_t val)
1432 {
1433 return ((val) << CP_EXEC_CS_3_NGROUPS_Z__SHIFT) & CP_EXEC_CS_3_NGROUPS_Z__MASK;
1434 }
1435
1436 #define REG_A4XX_CP_EXEC_CS_INDIRECT_0 0x00000000
1437
1438
1439 #define REG_A4XX_CP_EXEC_CS_INDIRECT_1 0x00000001
1440 #define A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__MASK 0xffffffff
1441 #define A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__SHIFT 0
1442 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_1_ADDR(uint32_t val)
1443 {
1444 return ((val) << A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__MASK;
1445 }
1446
1447 #define REG_A4XX_CP_EXEC_CS_INDIRECT_2 0x00000002
1448 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__MASK 0x00000ffc
1449 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__SHIFT 2
1450 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX(uint32_t val)
1451 {
1452 return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__MASK;
1453 }
1454 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__MASK 0x003ff000
1455 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__SHIFT 12
1456 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY(uint32_t val)
1457 {
1458 return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__MASK;
1459 }
1460 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__MASK 0xffc00000
1461 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__SHIFT 22
1462 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ(uint32_t val)
1463 {
1464 return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__MASK;
1465 }
1466
1467
1468 #define REG_A5XX_CP_EXEC_CS_INDIRECT_1 0x00000001
1469 #define A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK 0xffffffff
1470 #define A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT 0
1471 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO(uint32_t val)
1472 {
1473 return ((val) << A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK;
1474 }
1475
1476 #define REG_A5XX_CP_EXEC_CS_INDIRECT_2 0x00000002
1477 #define A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__MASK 0xffffffff
1478 #define A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT 0
1479 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI(uint32_t val)
1480 {
1481 return ((val) << A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__MASK;
1482 }
1483
1484 #define REG_A5XX_CP_EXEC_CS_INDIRECT_3 0x00000003
1485 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__MASK 0x00000ffc
1486 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT 2
1487 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(uint32_t val)
1488 {
1489 return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__MASK;
1490 }
1491 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__MASK 0x003ff000
1492 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT 12
1493 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(uint32_t val)
1494 {
1495 return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__MASK;
1496 }
1497 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK 0xffc00000
1498 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT 22
1499 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(uint32_t val)
1500 {
1501 return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK;
1502 }
1503
1504 #define REG_A2XX_CP_SET_MARKER_0 0x00000000
1505 #define A2XX_CP_SET_MARKER_0_MARKER__MASK 0x0000000f
1506 #define A2XX_CP_SET_MARKER_0_MARKER__SHIFT 0
1507 static inline uint32_t A2XX_CP_SET_MARKER_0_MARKER(uint32_t val)
1508 {
1509 return ((val) << A2XX_CP_SET_MARKER_0_MARKER__SHIFT) & A2XX_CP_SET_MARKER_0_MARKER__MASK;
1510 }
1511 #define A2XX_CP_SET_MARKER_0_MODE__MASK 0x0000000f
1512 #define A2XX_CP_SET_MARKER_0_MODE__SHIFT 0
1513 static inline uint32_t A2XX_CP_SET_MARKER_0_MODE(enum a6xx_render_mode val)
1514 {
1515 return ((val) << A2XX_CP_SET_MARKER_0_MODE__SHIFT) & A2XX_CP_SET_MARKER_0_MODE__MASK;
1516 }
1517 #define A2XX_CP_SET_MARKER_0_IFPC 0x00000100
1518
1519 static inline uint32_t REG_A2XX_CP_SET_PSEUDO_REG_(uint32_t i0) { return 0x00000000 + 0x3*i0; }
1520
1521 static inline uint32_t REG_A2XX_CP_SET_PSEUDO_REG__0(uint32_t i0) { return 0x00000000 + 0x3*i0; }
1522 #define A2XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__MASK 0x00000007
1523 #define A2XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__SHIFT 0
1524 static inline uint32_t A2XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG(enum pseudo_reg val)
1525 {
1526 return ((val) << A2XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__SHIFT) & A2XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__MASK;
1527 }
1528
1529 static inline uint32_t REG_A2XX_CP_SET_PSEUDO_REG__1(uint32_t i0) { return 0x00000001 + 0x3*i0; }
1530 #define A2XX_CP_SET_PSEUDO_REG__1_LO__MASK 0xffffffff
1531 #define A2XX_CP_SET_PSEUDO_REG__1_LO__SHIFT 0
1532 static inline uint32_t A2XX_CP_SET_PSEUDO_REG__1_LO(uint32_t val)
1533 {
1534 return ((val) << A2XX_CP_SET_PSEUDO_REG__1_LO__SHIFT) & A2XX_CP_SET_PSEUDO_REG__1_LO__MASK;
1535 }
1536
1537 static inline uint32_t REG_A2XX_CP_SET_PSEUDO_REG__2(uint32_t i0) { return 0x00000002 + 0x3*i0; }
1538 #define A2XX_CP_SET_PSEUDO_REG__2_HI__MASK 0xffffffff
1539 #define A2XX_CP_SET_PSEUDO_REG__2_HI__SHIFT 0
1540 static inline uint32_t A2XX_CP_SET_PSEUDO_REG__2_HI(uint32_t val)
1541 {
1542 return ((val) << A2XX_CP_SET_PSEUDO_REG__2_HI__SHIFT) & A2XX_CP_SET_PSEUDO_REG__2_HI__MASK;
1543 }
1544
1545 #define REG_A2XX_CP_REG_TEST_0 0x00000000
1546 #define A2XX_CP_REG_TEST_0_REG__MASK 0x00000fff
1547 #define A2XX_CP_REG_TEST_0_REG__SHIFT 0
1548 static inline uint32_t A2XX_CP_REG_TEST_0_REG(uint32_t val)
1549 {
1550 return ((val) << A2XX_CP_REG_TEST_0_REG__SHIFT) & A2XX_CP_REG_TEST_0_REG__MASK;
1551 }
1552 #define A2XX_CP_REG_TEST_0_BIT__MASK 0x01f00000
1553 #define A2XX_CP_REG_TEST_0_BIT__SHIFT 20
1554 static inline uint32_t A2XX_CP_REG_TEST_0_BIT(uint32_t val)
1555 {
1556 return ((val) << A2XX_CP_REG_TEST_0_BIT__SHIFT) & A2XX_CP_REG_TEST_0_BIT__MASK;
1557 }
1558 #define A2XX_CP_REG_TEST_0_UNK25 0x02000000
1559
1560
1561 #endif /* ADRENO_PM4_XML */