src/gallium/drivers/freedreno/adreno_pm4.xml.h

   1 #ifndef ADRENO_PM4_XML
   2 #define ADRENO_PM4_XML
   3
   4 /* Autogenerated file, DO NOT EDIT manually!
   5
   6 This file was generated by the rules-ng-ng headergen tool in this git repository:
   7 http://0x04.net/cgit/index.cgi/rules-ng-ng
   8 git clone git://0x04.net/rules-ng-ng
   9
  10 The rules-ng-ng source files this header was generated from are:
  11 - /home/robclark/src/freedreno/envytools/rnndb/a3xx.xml                (  38794 bytes, from 2013-05-05 22:47:28)
  12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml (   1453 bytes, from 2013-03-31 16:51:27)
  13 - /home/robclark/src/freedreno/envytools/rnndb/adreno_common.xml       (   3094 bytes, from 2013-05-05 18:29:22)
  14 - /home/robclark/src/freedreno/envytools/rnndb/adreno_pm4.xml          (   9712 bytes, from 2013-05-26 15:22:37)
  15
  16 Copyright (C) 2013 by the following authors:
  17 - Rob Clark <robdclark@gmail.com> (robclark)
  18
  19 Permission is hereby granted, free of charge, to any person obtaining
  20 a copy of this software and associated documentation files (the
  21 "Software"), to deal in the Software without restriction, including
  22 without limitation the rights to use, copy, modify, merge, publish,
  23 distribute, sublicense, and/or sell copies of the Software, and to
  24 permit persons to whom the Software is furnished to do so, subject to
  25 the following conditions:
  26
  27 The above copyright notice and this permission notice (including the
  28 next paragraph) shall be included in all copies or substantial
  29 portions of the Software.
  30
  31 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  32 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  33 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  34 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  35 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  36 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  37 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  38 */
  39
  40
  41 enum vgt_event_type {
  42         VS_DEALLOC = 0,
  43         PS_DEALLOC = 1,
  44         VS_DONE_TS = 2,
  45         PS_DONE_TS = 3,
  46         CACHE_FLUSH_TS = 4,
  47         CONTEXT_DONE = 5,
  48         CACHE_FLUSH = 6,
  49         HLSQ_FLUSH = 7,
  50         VIZQUERY_START = 7,
  51         VIZQUERY_END = 8,
  52         SC_WAIT_WC = 9,
  53         RST_PIX_CNT = 13,
  54         RST_VTX_CNT = 14,
  55         TILE_FLUSH = 15,
  56         CACHE_FLUSH_AND_INV_TS_EVENT = 20,
  57         ZPASS_DONE = 21,
  58         CACHE_FLUSH_AND_INV_EVENT = 22,
  59         PERFCOUNTER_START = 23,
  60         PERFCOUNTER_STOP = 24,
  61         VS_FETCH_DONE = 27,
  62         FACENESS_FLUSH = 28,
  63 };
  64
  65 enum pc_di_primtype {
  66         DI_PT_NONE = 0,
  67         DI_PT_POINTLIST = 1,
  68         DI_PT_LINELIST = 2,
  69         DI_PT_LINESTRIP = 3,
  70         DI_PT_TRILIST = 4,
  71         DI_PT_TRIFAN = 5,
  72         DI_PT_TRISTRIP = 6,
  73         DI_PT_RECTLIST = 8,
  74         DI_PT_QUADLIST = 13,
  75         DI_PT_QUADSTRIP = 14,
  76         DI_PT_POLYGON = 15,
  77         DI_PT_2D_COPY_RECT_LIST_V0 = 16,
  78         DI_PT_2D_COPY_RECT_LIST_V1 = 17,
  79         DI_PT_2D_COPY_RECT_LIST_V2 = 18,
  80         DI_PT_2D_COPY_RECT_LIST_V3 = 19,
  81         DI_PT_2D_FILL_RECT_LIST = 20,
  82         DI_PT_2D_LINE_STRIP = 21,
  83         DI_PT_2D_TRI_STRIP = 22,
  84 };
  85
  86 enum pc_di_src_sel {
  87         DI_SRC_SEL_DMA = 0,
  88         DI_SRC_SEL_IMMEDIATE = 1,
  89         DI_SRC_SEL_AUTO_INDEX = 2,
  90         DI_SRC_SEL_RESERVED = 3,
  91 };
  92
  93 enum pc_di_index_size {
  94         INDEX_SIZE_IGN = 0,
  95         INDEX_SIZE_16_BIT = 0,
  96         INDEX_SIZE_32_BIT = 1,
  97         INDEX_SIZE_8_BIT = 2,
  98         INDEX_SIZE_INVALID = 0,
  99 };
 100
 101 enum pc_di_vis_cull_mode {
 102         IGNORE_VISIBILITY = 0,
 103 };
 104
 105 enum adreno_pm4_packet_type {
 106         CP_TYPE0_PKT = 0,
 107         CP_TYPE1_PKT = 0x40000000,
 108         CP_TYPE2_PKT = 0x80000000,
 109         CP_TYPE3_PKT = 0xc0000000,
 110 };
 111
 112 enum adreno_pm4_type3_packets {
 113         CP_ME_INIT = 72,
 114         CP_NOP = 16,
 115         CP_INDIRECT_BUFFER = 63,
 116         CP_INDIRECT_BUFFER_PFD = 55,
 117         CP_WAIT_FOR_IDLE = 38,
 118         CP_WAIT_REG_MEM = 60,
 119         CP_WAIT_REG_EQ = 82,
 120         CP_WAT_REG_GTE = 83,
 121         CP_WAIT_UNTIL_READ = 92,
 122         CP_WAIT_IB_PFD_COMPLETE = 93,
 123         CP_REG_RMW = 33,
 124         CP_SET_BIN_DATA = 47,
 125         CP_REG_TO_MEM = 62,
 126         CP_MEM_WRITE = 61,
 127         CP_MEM_WRITE_CNTR = 79,
 128         CP_COND_EXEC = 68,
 129         CP_COND_WRITE = 69,
 130         CP_EVENT_WRITE = 70,
 131         CP_EVENT_WRITE_SHD = 88,
 132         CP_EVENT_WRITE_CFL = 89,
 133         CP_EVENT_WRITE_ZPD = 91,
 134         CP_RUN_OPENCL = 49,
 135         CP_DRAW_INDX = 34,
 136         CP_DRAW_INDX_2 = 54,
 137         CP_DRAW_INDX_BIN = 52,
 138         CP_DRAW_INDX_2_BIN = 53,
 139         CP_VIZ_QUERY = 35,
 140         CP_SET_STATE = 37,
 141         CP_SET_CONSTANT = 45,
 142         CP_IM_LOAD = 39,
 143         CP_IM_LOAD_IMMEDIATE = 43,
 144         CP_LOAD_CONSTANT_CONTEXT = 46,
 145         CP_INVALIDATE_STATE = 59,
 146         CP_SET_SHADER_BASES = 74,
 147         CP_SET_BIN_MASK = 80,
 148         CP_SET_BIN_SELECT = 81,
 149         CP_CONTEXT_UPDATE = 94,
 150         CP_INTERRUPT = 64,
 151         CP_IM_STORE = 44,
 152         CP_SET_BIN_BASE_OFFSET = 75,
 153         CP_SET_DRAW_INIT_FLAGS = 75,
 154         CP_SET_PROTECTED_MODE = 95,
 155         CP_LOAD_STATE = 48,
 156         CP_COND_INDIRECT_BUFFER_PFE = 58,
 157         CP_COND_INDIRECT_BUFFER_PFD = 50,
 158         CP_INDIRECT_BUFFER_PFE = 63,
 159         CP_SET_BIN = 76,
 160 };
 161
 162 enum adreno_state_block {
 163         SB_VERT_TEX = 0,
 164         SB_VERT_MIPADDR = 1,
 165         SB_FRAG_TEX = 2,
 166         SB_FRAG_MIPADDR = 3,
 167         SB_VERT_SHADER = 4,
 168         SB_FRAG_SHADER = 6,
 169 };
 170
 171 enum adreno_state_type {
 172         ST_SHADER = 0,
 173         ST_CONSTANTS = 1,
 174 };
 175
 176 enum adreno_state_src {
 177         SS_DIRECT = 0,
 178         SS_INDIRECT = 4,
 179 };
 180
 181 #define REG_CP_LOAD_STATE_0                                     0x00000000
 182 #define CP_LOAD_STATE_0_DST_OFF__MASK                           0x0000ffff
 183 #define CP_LOAD_STATE_0_DST_OFF__SHIFT                          0
 184 static inline uint32_t CP_LOAD_STATE_0_DST_OFF(uint32_t val)
 185 {
 186         return ((val) << CP_LOAD_STATE_0_DST_OFF__SHIFT) & CP_LOAD_STATE_0_DST_OFF__MASK;
 187 }
 188 #define CP_LOAD_STATE_0_STATE_SRC__MASK                         0x00070000
 189 #define CP_LOAD_STATE_0_STATE_SRC__SHIFT                        16
 190 static inline uint32_t CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val)
 191 {
 192         return ((val) << CP_LOAD_STATE_0_STATE_SRC__SHIFT) & CP_LOAD_STATE_0_STATE_SRC__MASK;
 193 }
 194 #define CP_LOAD_STATE_0_STATE_BLOCK__MASK                       0x00380000
 195 #define CP_LOAD_STATE_0_STATE_BLOCK__SHIFT                      19
 196 static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val)
 197 {
 198         return ((val) << CP_LOAD_STATE_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE_0_STATE_BLOCK__MASK;
 199 }
 200 #define CP_LOAD_STATE_0_NUM_UNIT__MASK                          0x7fc00000
 201 #define CP_LOAD_STATE_0_NUM_UNIT__SHIFT                         22
 202 static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val)
 203 {
 204         return ((val) << CP_LOAD_STATE_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE_0_NUM_UNIT__MASK;
 205 }
 206
 207 #define REG_CP_LOAD_STATE_1                                     0x00000001
 208 #define CP_LOAD_STATE_1_STATE_TYPE__MASK                        0x00000003
 209 #define CP_LOAD_STATE_1_STATE_TYPE__SHIFT                       0
 210 static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val)
 211 {
 212         return ((val) << CP_LOAD_STATE_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE_1_STATE_TYPE__MASK;
 213 }
 214 #define CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK                      0xfffffffc
 215 #define CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT                     2
 216 static inline uint32_t CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val)
 217 {
 218         return ((val >> 2) << CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK;
 219 }
 220
 221 #define REG_CP_SET_BIN_0                                        0x00000000
 222
 223 #define REG_CP_SET_BIN_1                                        0x00000001
 224 #define CP_SET_BIN_1_X1__MASK                                   0x0000ffff
 225 #define CP_SET_BIN_1_X1__SHIFT                                  0
 226 static inline uint32_t CP_SET_BIN_1_X1(uint32_t val)
 227 {
 228         return ((val) << CP_SET_BIN_1_X1__SHIFT) & CP_SET_BIN_1_X1__MASK;
 229 }
 230 #define CP_SET_BIN_1_Y1__MASK                                   0xffff0000
 231 #define CP_SET_BIN_1_Y1__SHIFT                                  16
 232 static inline uint32_t CP_SET_BIN_1_Y1(uint32_t val)
 233 {
 234         return ((val) << CP_SET_BIN_1_Y1__SHIFT) & CP_SET_BIN_1_Y1__MASK;
 235 }
 236
 237 #define REG_CP_SET_BIN_2                                        0x00000002
 238 #define CP_SET_BIN_2_X2__MASK                                   0x0000ffff
 239 #define CP_SET_BIN_2_X2__SHIFT                                  0
 240 static inline uint32_t CP_SET_BIN_2_X2(uint32_t val)
 241 {
 242         return ((val) << CP_SET_BIN_2_X2__SHIFT) & CP_SET_BIN_2_X2__MASK;
 243 }
 244 #define CP_SET_BIN_2_Y2__MASK                                   0xffff0000
 245 #define CP_SET_BIN_2_Y2__SHIFT                                  16
 246 static inline uint32_t CP_SET_BIN_2_Y2(uint32_t val)
 247 {
 248         return ((val) << CP_SET_BIN_2_Y2__SHIFT) & CP_SET_BIN_2_Y2__MASK;
 249 }
 250
 251
 252 #endif /* ADRENO_PM4_XML */