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freedreno: resync generated headers
[mesa.git] / src / gallium / drivers / freedreno / adreno_pm4.xml.h
1 #ifndef ADRENO_PM4_XML
2 #define ADRENO_PM4_XML
3
4 /* Autogenerated file, DO NOT EDIT manually!
5
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
9
10 The rules-ng-ng source files this header was generated from are:
11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 364 bytes, from 2013-11-30 14:47:15)
12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
13 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32840 bytes, from 2014-01-05 14:44:21)
14 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 8900 bytes, from 2014-01-05 14:44:21)
15 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 12362 bytes, from 2014-01-07 14:47:36)
16 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 54368 bytes, from 2014-01-05 14:44:21)
17 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 8344 bytes, from 2013-11-30 14:49:47)
18
19 Copyright (C) 2013-2014 by the following authors:
20 - Rob Clark <robdclark@gmail.com> (robclark)
21
22 Permission is hereby granted, free of charge, to any person obtaining
23 a copy of this software and associated documentation files (the
24 "Software"), to deal in the Software without restriction, including
25 without limitation the rights to use, copy, modify, merge, publish,
26 distribute, sublicense, and/or sell copies of the Software, and to
27 permit persons to whom the Software is furnished to do so, subject to
28 the following conditions:
29
30 The above copyright notice and this permission notice (including the
31 next paragraph) shall be included in all copies or substantial
32 portions of the Software.
33
34 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
35 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
36 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
37 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
38 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
39 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
40 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43
44 enum vgt_event_type {
45 VS_DEALLOC = 0,
46 PS_DEALLOC = 1,
47 VS_DONE_TS = 2,
48 PS_DONE_TS = 3,
49 CACHE_FLUSH_TS = 4,
50 CONTEXT_DONE = 5,
51 CACHE_FLUSH = 6,
52 HLSQ_FLUSH = 7,
53 VIZQUERY_START = 7,
54 VIZQUERY_END = 8,
55 SC_WAIT_WC = 9,
56 RST_PIX_CNT = 13,
57 RST_VTX_CNT = 14,
58 TILE_FLUSH = 15,
59 CACHE_FLUSH_AND_INV_TS_EVENT = 20,
60 ZPASS_DONE = 21,
61 CACHE_FLUSH_AND_INV_EVENT = 22,
62 PERFCOUNTER_START = 23,
63 PERFCOUNTER_STOP = 24,
64 VS_FETCH_DONE = 27,
65 FACENESS_FLUSH = 28,
66 };
67
68 enum pc_di_primtype {
69 DI_PT_NONE = 0,
70 DI_PT_POINTLIST_A2XX = 1,
71 DI_PT_LINELIST = 2,
72 DI_PT_LINESTRIP = 3,
73 DI_PT_TRILIST = 4,
74 DI_PT_TRIFAN = 5,
75 DI_PT_TRISTRIP = 6,
76 DI_PT_LINELOOP = 7,
77 DI_PT_RECTLIST = 8,
78 DI_PT_POINTLIST_A3XX = 9,
79 DI_PT_QUADLIST = 13,
80 DI_PT_QUADSTRIP = 14,
81 DI_PT_POLYGON = 15,
82 DI_PT_2D_COPY_RECT_LIST_V0 = 16,
83 DI_PT_2D_COPY_RECT_LIST_V1 = 17,
84 DI_PT_2D_COPY_RECT_LIST_V2 = 18,
85 DI_PT_2D_COPY_RECT_LIST_V3 = 19,
86 DI_PT_2D_FILL_RECT_LIST = 20,
87 DI_PT_2D_LINE_STRIP = 21,
88 DI_PT_2D_TRI_STRIP = 22,
89 };
90
91 enum pc_di_src_sel {
92 DI_SRC_SEL_DMA = 0,
93 DI_SRC_SEL_IMMEDIATE = 1,
94 DI_SRC_SEL_AUTO_INDEX = 2,
95 DI_SRC_SEL_RESERVED = 3,
96 };
97
98 enum pc_di_index_size {
99 INDEX_SIZE_IGN = 0,
100 INDEX_SIZE_16_BIT = 0,
101 INDEX_SIZE_32_BIT = 1,
102 INDEX_SIZE_8_BIT = 2,
103 INDEX_SIZE_INVALID = 0,
104 };
105
106 enum pc_di_vis_cull_mode {
107 IGNORE_VISIBILITY = 0,
108 USE_VISIBILITY = 1,
109 };
110
111 enum adreno_pm4_packet_type {
112 CP_TYPE0_PKT = 0,
113 CP_TYPE1_PKT = 0x40000000,
114 CP_TYPE2_PKT = 0x80000000,
115 CP_TYPE3_PKT = 0xc0000000,
116 };
117
118 enum adreno_pm4_type3_packets {
119 CP_ME_INIT = 72,
120 CP_NOP = 16,
121 CP_INDIRECT_BUFFER = 63,
122 CP_INDIRECT_BUFFER_PFD = 55,
123 CP_WAIT_FOR_IDLE = 38,
124 CP_WAIT_REG_MEM = 60,
125 CP_WAIT_REG_EQ = 82,
126 CP_WAIT_REG_GTE = 83,
127 CP_WAIT_UNTIL_READ = 92,
128 CP_WAIT_IB_PFD_COMPLETE = 93,
129 CP_REG_RMW = 33,
130 CP_SET_BIN_DATA = 47,
131 CP_REG_TO_MEM = 62,
132 CP_MEM_WRITE = 61,
133 CP_MEM_WRITE_CNTR = 79,
134 CP_COND_EXEC = 68,
135 CP_COND_WRITE = 69,
136 CP_EVENT_WRITE = 70,
137 CP_EVENT_WRITE_SHD = 88,
138 CP_EVENT_WRITE_CFL = 89,
139 CP_EVENT_WRITE_ZPD = 91,
140 CP_RUN_OPENCL = 49,
141 CP_DRAW_INDX = 34,
142 CP_DRAW_INDX_2 = 54,
143 CP_DRAW_INDX_BIN = 52,
144 CP_DRAW_INDX_2_BIN = 53,
145 CP_VIZ_QUERY = 35,
146 CP_SET_STATE = 37,
147 CP_SET_CONSTANT = 45,
148 CP_IM_LOAD = 39,
149 CP_IM_LOAD_IMMEDIATE = 43,
150 CP_LOAD_CONSTANT_CONTEXT = 46,
151 CP_INVALIDATE_STATE = 59,
152 CP_SET_SHADER_BASES = 74,
153 CP_SET_BIN_MASK = 80,
154 CP_SET_BIN_SELECT = 81,
155 CP_CONTEXT_UPDATE = 94,
156 CP_INTERRUPT = 64,
157 CP_IM_STORE = 44,
158 CP_SET_DRAW_INIT_FLAGS = 75,
159 CP_SET_PROTECTED_MODE = 95,
160 CP_LOAD_STATE = 48,
161 CP_COND_INDIRECT_BUFFER_PFE = 58,
162 CP_COND_INDIRECT_BUFFER_PFD = 50,
163 CP_INDIRECT_BUFFER_PFE = 63,
164 CP_SET_BIN = 76,
165 CP_TEST_TWO_MEMS = 113,
166 CP_WAIT_FOR_ME = 19,
167 IN_IB_PREFETCH_END = 23,
168 IN_SUBBLK_PREFETCH = 31,
169 IN_INSTR_PREFETCH = 32,
170 IN_INSTR_MATCH = 71,
171 IN_CONST_PREFETCH = 73,
172 IN_INCR_UPDT_STATE = 85,
173 IN_INCR_UPDT_CONST = 86,
174 IN_INCR_UPDT_INSTR = 87,
175 };
176
177 enum adreno_state_block {
178 SB_VERT_TEX = 0,
179 SB_VERT_MIPADDR = 1,
180 SB_FRAG_TEX = 2,
181 SB_FRAG_MIPADDR = 3,
182 SB_VERT_SHADER = 4,
183 SB_FRAG_SHADER = 6,
184 };
185
186 enum adreno_state_type {
187 ST_SHADER = 0,
188 ST_CONSTANTS = 1,
189 };
190
191 enum adreno_state_src {
192 SS_DIRECT = 0,
193 SS_INDIRECT = 4,
194 };
195
196 #define REG_CP_LOAD_STATE_0 0x00000000
197 #define CP_LOAD_STATE_0_DST_OFF__MASK 0x0000ffff
198 #define CP_LOAD_STATE_0_DST_OFF__SHIFT 0
199 static inline uint32_t CP_LOAD_STATE_0_DST_OFF(uint32_t val)
200 {
201 return ((val) << CP_LOAD_STATE_0_DST_OFF__SHIFT) & CP_LOAD_STATE_0_DST_OFF__MASK;
202 }
203 #define CP_LOAD_STATE_0_STATE_SRC__MASK 0x00070000
204 #define CP_LOAD_STATE_0_STATE_SRC__SHIFT 16
205 static inline uint32_t CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val)
206 {
207 return ((val) << CP_LOAD_STATE_0_STATE_SRC__SHIFT) & CP_LOAD_STATE_0_STATE_SRC__MASK;
208 }
209 #define CP_LOAD_STATE_0_STATE_BLOCK__MASK 0x00380000
210 #define CP_LOAD_STATE_0_STATE_BLOCK__SHIFT 19
211 static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val)
212 {
213 return ((val) << CP_LOAD_STATE_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE_0_STATE_BLOCK__MASK;
214 }
215 #define CP_LOAD_STATE_0_NUM_UNIT__MASK 0x7fc00000
216 #define CP_LOAD_STATE_0_NUM_UNIT__SHIFT 22
217 static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val)
218 {
219 return ((val) << CP_LOAD_STATE_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE_0_NUM_UNIT__MASK;
220 }
221
222 #define REG_CP_LOAD_STATE_1 0x00000001
223 #define CP_LOAD_STATE_1_STATE_TYPE__MASK 0x00000003
224 #define CP_LOAD_STATE_1_STATE_TYPE__SHIFT 0
225 static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val)
226 {
227 return ((val) << CP_LOAD_STATE_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE_1_STATE_TYPE__MASK;
228 }
229 #define CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK 0xfffffffc
230 #define CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT 2
231 static inline uint32_t CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val)
232 {
233 return ((val >> 2) << CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK;
234 }
235
236 #define REG_CP_DRAW_INDX_0 0x00000000
237 #define CP_DRAW_INDX_0_VIZ_QUERY__MASK 0xffffffff
238 #define CP_DRAW_INDX_0_VIZ_QUERY__SHIFT 0
239 static inline uint32_t CP_DRAW_INDX_0_VIZ_QUERY(uint32_t val)
240 {
241 return ((val) << CP_DRAW_INDX_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_0_VIZ_QUERY__MASK;
242 }
243
244 #define REG_CP_DRAW_INDX_1 0x00000001
245 #define CP_DRAW_INDX_1_PRIM_TYPE__MASK 0x0000003f
246 #define CP_DRAW_INDX_1_PRIM_TYPE__SHIFT 0
247 static inline uint32_t CP_DRAW_INDX_1_PRIM_TYPE(enum pc_di_primtype val)
248 {
249 return ((val) << CP_DRAW_INDX_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_1_PRIM_TYPE__MASK;
250 }
251 #define CP_DRAW_INDX_1_SOURCE_SELECT__MASK 0x000000c0
252 #define CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT 6
253 static inline uint32_t CP_DRAW_INDX_1_SOURCE_SELECT(enum pc_di_src_sel val)
254 {
255 return ((val) << CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_1_SOURCE_SELECT__MASK;
256 }
257 #define CP_DRAW_INDX_1_VIS_CULL__MASK 0x00000600
258 #define CP_DRAW_INDX_1_VIS_CULL__SHIFT 9
259 static inline uint32_t CP_DRAW_INDX_1_VIS_CULL(enum pc_di_vis_cull_mode val)
260 {
261 return ((val) << CP_DRAW_INDX_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_1_VIS_CULL__MASK;
262 }
263 #define CP_DRAW_INDX_1_INDEX_SIZE__MASK 0x00000800
264 #define CP_DRAW_INDX_1_INDEX_SIZE__SHIFT 11
265 static inline uint32_t CP_DRAW_INDX_1_INDEX_SIZE(enum pc_di_index_size val)
266 {
267 return ((val) << CP_DRAW_INDX_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_1_INDEX_SIZE__MASK;
268 }
269 #define CP_DRAW_INDX_1_NOT_EOP 0x00001000
270 #define CP_DRAW_INDX_1_SMALL_INDEX 0x00002000
271 #define CP_DRAW_INDX_1_PRE_DRAW_INITIATOR_ENABLE 0x00004000
272 #define CP_DRAW_INDX_1_NUM_INDICES__MASK 0xffff0000
273 #define CP_DRAW_INDX_1_NUM_INDICES__SHIFT 16
274 static inline uint32_t CP_DRAW_INDX_1_NUM_INDICES(uint32_t val)
275 {
276 return ((val) << CP_DRAW_INDX_1_NUM_INDICES__SHIFT) & CP_DRAW_INDX_1_NUM_INDICES__MASK;
277 }
278
279 #define REG_CP_DRAW_INDX_2 0x00000002
280 #define CP_DRAW_INDX_2_NUM_INDICES__MASK 0xffffffff
281 #define CP_DRAW_INDX_2_NUM_INDICES__SHIFT 0
282 static inline uint32_t CP_DRAW_INDX_2_NUM_INDICES(uint32_t val)
283 {
284 return ((val) << CP_DRAW_INDX_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_NUM_INDICES__MASK;
285 }
286
287 #define REG_CP_DRAW_INDX_2 0x00000002
288 #define CP_DRAW_INDX_2_INDX_BASE__MASK 0xffffffff
289 #define CP_DRAW_INDX_2_INDX_BASE__SHIFT 0
290 static inline uint32_t CP_DRAW_INDX_2_INDX_BASE(uint32_t val)
291 {
292 return ((val) << CP_DRAW_INDX_2_INDX_BASE__SHIFT) & CP_DRAW_INDX_2_INDX_BASE__MASK;
293 }
294
295 #define REG_CP_DRAW_INDX_2 0x00000002
296 #define CP_DRAW_INDX_2_INDX_SIZE__MASK 0xffffffff
297 #define CP_DRAW_INDX_2_INDX_SIZE__SHIFT 0
298 static inline uint32_t CP_DRAW_INDX_2_INDX_SIZE(uint32_t val)
299 {
300 return ((val) << CP_DRAW_INDX_2_INDX_SIZE__SHIFT) & CP_DRAW_INDX_2_INDX_SIZE__MASK;
301 }
302
303 #define REG_CP_DRAW_INDX_2_0 0x00000000
304 #define CP_DRAW_INDX_2_0_VIZ_QUERY__MASK 0xffffffff
305 #define CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT 0
306 static inline uint32_t CP_DRAW_INDX_2_0_VIZ_QUERY(uint32_t val)
307 {
308 return ((val) << CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_2_0_VIZ_QUERY__MASK;
309 }
310
311 #define REG_CP_DRAW_INDX_2_1 0x00000001
312 #define CP_DRAW_INDX_2_1_PRIM_TYPE__MASK 0x0000003f
313 #define CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT 0
314 static inline uint32_t CP_DRAW_INDX_2_1_PRIM_TYPE(enum pc_di_primtype val)
315 {
316 return ((val) << CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_2_1_PRIM_TYPE__MASK;
317 }
318 #define CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK 0x000000c0
319 #define CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT 6
320 static inline uint32_t CP_DRAW_INDX_2_1_SOURCE_SELECT(enum pc_di_src_sel val)
321 {
322 return ((val) << CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK;
323 }
324 #define CP_DRAW_INDX_2_1_VIS_CULL__MASK 0x00000600
325 #define CP_DRAW_INDX_2_1_VIS_CULL__SHIFT 9
326 static inline uint32_t CP_DRAW_INDX_2_1_VIS_CULL(enum pc_di_vis_cull_mode val)
327 {
328 return ((val) << CP_DRAW_INDX_2_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_2_1_VIS_CULL__MASK;
329 }
330 #define CP_DRAW_INDX_2_1_INDEX_SIZE__MASK 0x00000800
331 #define CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT 11
332 static inline uint32_t CP_DRAW_INDX_2_1_INDEX_SIZE(enum pc_di_index_size val)
333 {
334 return ((val) << CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_2_1_INDEX_SIZE__MASK;
335 }
336 #define CP_DRAW_INDX_2_1_NOT_EOP 0x00001000
337 #define CP_DRAW_INDX_2_1_SMALL_INDEX 0x00002000
338 #define CP_DRAW_INDX_2_1_PRE_DRAW_INITIATOR_ENABLE 0x00004000
339 #define CP_DRAW_INDX_2_1_NUM_INDICES__MASK 0xffff0000
340 #define CP_DRAW_INDX_2_1_NUM_INDICES__SHIFT 16
341 static inline uint32_t CP_DRAW_INDX_2_1_NUM_INDICES(uint32_t val)
342 {
343 return ((val) << CP_DRAW_INDX_2_1_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_1_NUM_INDICES__MASK;
344 }
345
346 #define REG_CP_DRAW_INDX_2_2 0x00000002
347 #define CP_DRAW_INDX_2_2_NUM_INDICES__MASK 0xffffffff
348 #define CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT 0
349 static inline uint32_t CP_DRAW_INDX_2_2_NUM_INDICES(uint32_t val)
350 {
351 return ((val) << CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_2_NUM_INDICES__MASK;
352 }
353
354 #define REG_CP_SET_BIN_0 0x00000000
355
356 #define REG_CP_SET_BIN_1 0x00000001
357 #define CP_SET_BIN_1_X1__MASK 0x0000ffff
358 #define CP_SET_BIN_1_X1__SHIFT 0
359 static inline uint32_t CP_SET_BIN_1_X1(uint32_t val)
360 {
361 return ((val) << CP_SET_BIN_1_X1__SHIFT) & CP_SET_BIN_1_X1__MASK;
362 }
363 #define CP_SET_BIN_1_Y1__MASK 0xffff0000
364 #define CP_SET_BIN_1_Y1__SHIFT 16
365 static inline uint32_t CP_SET_BIN_1_Y1(uint32_t val)
366 {
367 return ((val) << CP_SET_BIN_1_Y1__SHIFT) & CP_SET_BIN_1_Y1__MASK;
368 }
369
370 #define REG_CP_SET_BIN_2 0x00000002
371 #define CP_SET_BIN_2_X2__MASK 0x0000ffff
372 #define CP_SET_BIN_2_X2__SHIFT 0
373 static inline uint32_t CP_SET_BIN_2_X2(uint32_t val)
374 {
375 return ((val) << CP_SET_BIN_2_X2__SHIFT) & CP_SET_BIN_2_X2__MASK;
376 }
377 #define CP_SET_BIN_2_Y2__MASK 0xffff0000
378 #define CP_SET_BIN_2_Y2__SHIFT 16
379 static inline uint32_t CP_SET_BIN_2_Y2(uint32_t val)
380 {
381 return ((val) << CP_SET_BIN_2_Y2__SHIFT) & CP_SET_BIN_2_Y2__MASK;
382 }
383
384 #define REG_CP_SET_BIN_DATA_0 0x00000000
385 #define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK 0xffffffff
386 #define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT 0
387 static inline uint32_t CP_SET_BIN_DATA_0_BIN_DATA_ADDR(uint32_t val)
388 {
389 return ((val) << CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT) & CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK;
390 }
391
392 #define REG_CP_SET_BIN_DATA_1 0x00000001
393 #define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK 0xffffffff
394 #define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT 0
395 static inline uint32_t CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS(uint32_t val)
396 {
397 return ((val) << CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT) & CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK;
398 }
399
400
401 #endif /* ADRENO_PM4_XML */