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freedreno: update generated headers
[mesa.git] / src / gallium / drivers / freedreno / adreno_pm4.xml.h
1 #ifndef ADRENO_PM4_XML
2 #define ADRENO_PM4_XML
3
4 /* Autogenerated file, DO NOT EDIT manually!
5
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
9
10 The rules-ng-ng source files this header was generated from are:
11 - /home/robclark/src/freedreno/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-01-31 18:26:32)
12 - /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-01-08 14:56:24)
13 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 36805 bytes, from 2018-05-20 19:03:35)
14 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 13634 bytes, from 2018-06-10 17:35:36)
15 - /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 41584 bytes, from 2018-06-18 14:25:44)
16 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 83840 bytes, from 2018-01-10 16:21:40)
17 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-01-08 14:56:24)
18 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a5xx.xml ( 147158 bytes, from 2018-06-18 14:25:44)
19 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a6xx.xml ( 88437 bytes, from 2018-06-18 14:25:44)
20 - /home/robclark/src/freedreno/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-06-10 17:37:04)
21 - /home/robclark/src/freedreno/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-01-08 14:56:24)
22
23 Copyright (C) 2013-2018 by the following authors:
24 - Rob Clark <robdclark@gmail.com> (robclark)
25 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
26
27 Permission is hereby granted, free of charge, to any person obtaining
28 a copy of this software and associated documentation files (the
29 "Software"), to deal in the Software without restriction, including
30 without limitation the rights to use, copy, modify, merge, publish,
31 distribute, sublicense, and/or sell copies of the Software, and to
32 permit persons to whom the Software is furnished to do so, subject to
33 the following conditions:
34
35 The above copyright notice and this permission notice (including the
36 next paragraph) shall be included in all copies or substantial
37 portions of the Software.
38
39 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
40 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
41 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
42 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
43 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
44 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
45 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
46 */
47
48
49 enum vgt_event_type {
50 VS_DEALLOC = 0,
51 PS_DEALLOC = 1,
52 VS_DONE_TS = 2,
53 PS_DONE_TS = 3,
54 CACHE_FLUSH_TS = 4,
55 CONTEXT_DONE = 5,
56 CACHE_FLUSH = 6,
57 HLSQ_FLUSH = 7,
58 VIZQUERY_START = 7,
59 VIZQUERY_END = 8,
60 SC_WAIT_WC = 9,
61 RST_PIX_CNT = 13,
62 RST_VTX_CNT = 14,
63 TILE_FLUSH = 15,
64 STAT_EVENT = 16,
65 CACHE_FLUSH_AND_INV_TS_EVENT = 20,
66 ZPASS_DONE = 21,
67 CACHE_FLUSH_AND_INV_EVENT = 22,
68 PERFCOUNTER_START = 23,
69 PERFCOUNTER_STOP = 24,
70 VS_FETCH_DONE = 27,
71 FACENESS_FLUSH = 28,
72 FLUSH_SO_0 = 17,
73 FLUSH_SO_1 = 18,
74 FLUSH_SO_2 = 19,
75 FLUSH_SO_3 = 20,
76 PC_CCU_INVALIDATE_DEPTH = 24,
77 PC_CCU_INVALIDATE_COLOR = 25,
78 UNK_1C = 28,
79 UNK_1D = 29,
80 BLIT = 30,
81 UNK_25 = 37,
82 LRZ_FLUSH = 38,
83 UNK_2C = 44,
84 UNK_2D = 45,
85 };
86
87 enum pc_di_primtype {
88 DI_PT_NONE = 0,
89 DI_PT_POINTLIST_PSIZE = 1,
90 DI_PT_LINELIST = 2,
91 DI_PT_LINESTRIP = 3,
92 DI_PT_TRILIST = 4,
93 DI_PT_TRIFAN = 5,
94 DI_PT_TRISTRIP = 6,
95 DI_PT_LINELOOP = 7,
96 DI_PT_RECTLIST = 8,
97 DI_PT_POINTLIST = 9,
98 DI_PT_LINE_ADJ = 10,
99 DI_PT_LINESTRIP_ADJ = 11,
100 DI_PT_TRI_ADJ = 12,
101 DI_PT_TRISTRIP_ADJ = 13,
102 };
103
104 enum pc_di_src_sel {
105 DI_SRC_SEL_DMA = 0,
106 DI_SRC_SEL_IMMEDIATE = 1,
107 DI_SRC_SEL_AUTO_INDEX = 2,
108 DI_SRC_SEL_RESERVED = 3,
109 };
110
111 enum pc_di_index_size {
112 INDEX_SIZE_IGN = 0,
113 INDEX_SIZE_16_BIT = 0,
114 INDEX_SIZE_32_BIT = 1,
115 INDEX_SIZE_8_BIT = 2,
116 INDEX_SIZE_INVALID = 0,
117 };
118
119 enum pc_di_vis_cull_mode {
120 IGNORE_VISIBILITY = 0,
121 USE_VISIBILITY = 1,
122 };
123
124 enum adreno_pm4_packet_type {
125 CP_TYPE0_PKT = 0,
126 CP_TYPE1_PKT = 0x40000000,
127 CP_TYPE2_PKT = 0x80000000,
128 CP_TYPE3_PKT = 0xc0000000,
129 CP_TYPE4_PKT = 0x40000000,
130 CP_TYPE7_PKT = 0x70000000,
131 };
132
133 enum adreno_pm4_type3_packets {
134 CP_ME_INIT = 72,
135 CP_NOP = 16,
136 CP_PREEMPT_ENABLE = 28,
137 CP_PREEMPT_TOKEN = 30,
138 CP_INDIRECT_BUFFER = 63,
139 CP_INDIRECT_BUFFER_PFD = 55,
140 CP_WAIT_FOR_IDLE = 38,
141 CP_WAIT_REG_MEM = 60,
142 CP_WAIT_REG_EQ = 82,
143 CP_WAIT_REG_GTE = 83,
144 CP_WAIT_UNTIL_READ = 92,
145 CP_WAIT_IB_PFD_COMPLETE = 93,
146 CP_REG_RMW = 33,
147 CP_SET_BIN_DATA = 47,
148 CP_SET_BIN_DATA5 = 47,
149 CP_REG_TO_MEM = 62,
150 CP_MEM_WRITE = 61,
151 CP_MEM_WRITE_CNTR = 79,
152 CP_COND_EXEC = 68,
153 CP_COND_WRITE = 69,
154 CP_COND_WRITE5 = 69,
155 CP_EVENT_WRITE = 70,
156 CP_EVENT_WRITE_SHD = 88,
157 CP_EVENT_WRITE_CFL = 89,
158 CP_EVENT_WRITE_ZPD = 91,
159 CP_RUN_OPENCL = 49,
160 CP_DRAW_INDX = 34,
161 CP_DRAW_INDX_2 = 54,
162 CP_DRAW_INDX_BIN = 52,
163 CP_DRAW_INDX_2_BIN = 53,
164 CP_VIZ_QUERY = 35,
165 CP_SET_STATE = 37,
166 CP_SET_CONSTANT = 45,
167 CP_IM_LOAD = 39,
168 CP_IM_LOAD_IMMEDIATE = 43,
169 CP_LOAD_CONSTANT_CONTEXT = 46,
170 CP_INVALIDATE_STATE = 59,
171 CP_SET_SHADER_BASES = 74,
172 CP_SET_BIN_MASK = 80,
173 CP_SET_BIN_SELECT = 81,
174 CP_CONTEXT_UPDATE = 94,
175 CP_INTERRUPT = 64,
176 CP_IM_STORE = 44,
177 CP_SET_DRAW_INIT_FLAGS = 75,
178 CP_SET_PROTECTED_MODE = 95,
179 CP_BOOTSTRAP_UCODE = 111,
180 CP_LOAD_STATE = 48,
181 CP_LOAD_STATE4 = 48,
182 CP_COND_INDIRECT_BUFFER_PFE = 58,
183 CP_COND_INDIRECT_BUFFER_PFD = 50,
184 CP_INDIRECT_BUFFER_PFE = 63,
185 CP_SET_BIN = 76,
186 CP_TEST_TWO_MEMS = 113,
187 CP_REG_WR_NO_CTXT = 120,
188 CP_RECORD_PFP_TIMESTAMP = 17,
189 CP_SET_SECURE_MODE = 102,
190 CP_WAIT_FOR_ME = 19,
191 CP_SET_DRAW_STATE = 67,
192 CP_DRAW_INDX_OFFSET = 56,
193 CP_DRAW_INDIRECT = 40,
194 CP_DRAW_INDX_INDIRECT = 41,
195 CP_DRAW_AUTO = 36,
196 CP_UNKNOWN_19 = 25,
197 CP_UNKNOWN_1A = 26,
198 CP_UNKNOWN_4E = 78,
199 CP_WIDE_REG_WRITE = 116,
200 CP_SCRATCH_TO_REG = 77,
201 CP_REG_TO_SCRATCH = 74,
202 CP_WAIT_MEM_WRITES = 18,
203 CP_COND_REG_EXEC = 71,
204 CP_MEM_TO_REG = 66,
205 CP_EXEC_CS_INDIRECT = 65,
206 CP_EXEC_CS = 51,
207 CP_PERFCOUNTER_ACTION = 80,
208 CP_SMMU_TABLE_UPDATE = 83,
209 CP_SET_MARKER = 101,
210 CP_SET_PSEUDO_REG = 86,
211 CP_CONTEXT_REG_BUNCH = 92,
212 CP_YIELD_ENABLE = 28,
213 CP_SKIP_IB2_ENABLE_GLOBAL = 29,
214 CP_SKIP_IB2_ENABLE_LOCAL = 35,
215 CP_SET_SUBDRAW_SIZE = 53,
216 CP_SET_VISIBILITY_OVERRIDE = 100,
217 CP_PREEMPT_ENABLE_GLOBAL = 105,
218 CP_PREEMPT_ENABLE_LOCAL = 106,
219 CP_CONTEXT_SWITCH_YIELD = 107,
220 CP_SET_RENDER_MODE = 108,
221 CP_COMPUTE_CHECKPOINT = 110,
222 CP_MEM_TO_MEM = 115,
223 CP_BLIT = 44,
224 CP_REG_TEST = 57,
225 IN_IB_PREFETCH_END = 23,
226 IN_SUBBLK_PREFETCH = 31,
227 IN_INSTR_PREFETCH = 32,
228 IN_INSTR_MATCH = 71,
229 IN_CONST_PREFETCH = 73,
230 IN_INCR_UPDT_STATE = 85,
231 IN_INCR_UPDT_CONST = 86,
232 IN_INCR_UPDT_INSTR = 87,
233 PKT4 = 4,
234 };
235
236 enum adreno_state_block {
237 SB_VERT_TEX = 0,
238 SB_VERT_MIPADDR = 1,
239 SB_FRAG_TEX = 2,
240 SB_FRAG_MIPADDR = 3,
241 SB_VERT_SHADER = 4,
242 SB_GEOM_SHADER = 5,
243 SB_FRAG_SHADER = 6,
244 SB_COMPUTE_SHADER = 7,
245 };
246
247 enum adreno_state_type {
248 ST_SHADER = 0,
249 ST_CONSTANTS = 1,
250 };
251
252 enum adreno_state_src {
253 SS_DIRECT = 0,
254 SS_INVALID_ALL_IC = 2,
255 SS_INVALID_PART_IC = 3,
256 SS_INDIRECT = 4,
257 SS_INDIRECT_TCM = 5,
258 SS_INDIRECT_STM = 6,
259 };
260
261 enum a4xx_state_block {
262 SB4_VS_TEX = 0,
263 SB4_HS_TEX = 1,
264 SB4_DS_TEX = 2,
265 SB4_GS_TEX = 3,
266 SB4_FS_TEX = 4,
267 SB4_CS_TEX = 5,
268 SB4_VS_SHADER = 8,
269 SB4_HS_SHADER = 9,
270 SB4_DS_SHADER = 10,
271 SB4_GS_SHADER = 11,
272 SB4_FS_SHADER = 12,
273 SB4_CS_SHADER = 13,
274 SB4_SSBO = 14,
275 SB4_CS_SSBO = 15,
276 };
277
278 enum a4xx_state_type {
279 ST4_SHADER = 0,
280 ST4_CONSTANTS = 1,
281 };
282
283 enum a4xx_state_src {
284 SS4_DIRECT = 0,
285 SS4_INDIRECT = 2,
286 };
287
288 enum a4xx_index_size {
289 INDEX4_SIZE_8_BIT = 0,
290 INDEX4_SIZE_16_BIT = 1,
291 INDEX4_SIZE_32_BIT = 2,
292 };
293
294 enum cp_cond_function {
295 WRITE_ALWAYS = 0,
296 WRITE_LT = 1,
297 WRITE_LE = 2,
298 WRITE_EQ = 3,
299 WRITE_NE = 4,
300 WRITE_GE = 5,
301 WRITE_GT = 6,
302 };
303
304 enum render_mode_cmd {
305 BYPASS = 1,
306 BINNING = 2,
307 GMEM = 3,
308 BLIT2D = 5,
309 BLIT2DSCALE = 7,
310 END2D = 8,
311 };
312
313 enum cp_blit_cmd {
314 BLIT_OP_FILL = 0,
315 BLIT_OP_COPY = 1,
316 BLIT_OP_SCALE = 3,
317 };
318
319 #define REG_CP_LOAD_STATE_0 0x00000000
320 #define CP_LOAD_STATE_0_DST_OFF__MASK 0x0000ffff
321 #define CP_LOAD_STATE_0_DST_OFF__SHIFT 0
322 static inline uint32_t CP_LOAD_STATE_0_DST_OFF(uint32_t val)
323 {
324 return ((val) << CP_LOAD_STATE_0_DST_OFF__SHIFT) & CP_LOAD_STATE_0_DST_OFF__MASK;
325 }
326 #define CP_LOAD_STATE_0_STATE_SRC__MASK 0x00070000
327 #define CP_LOAD_STATE_0_STATE_SRC__SHIFT 16
328 static inline uint32_t CP_LOAD_STATE_0_STATE_SRC(enum adreno_state_src val)
329 {
330 return ((val) << CP_LOAD_STATE_0_STATE_SRC__SHIFT) & CP_LOAD_STATE_0_STATE_SRC__MASK;
331 }
332 #define CP_LOAD_STATE_0_STATE_BLOCK__MASK 0x00380000
333 #define CP_LOAD_STATE_0_STATE_BLOCK__SHIFT 19
334 static inline uint32_t CP_LOAD_STATE_0_STATE_BLOCK(enum adreno_state_block val)
335 {
336 return ((val) << CP_LOAD_STATE_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE_0_STATE_BLOCK__MASK;
337 }
338 #define CP_LOAD_STATE_0_NUM_UNIT__MASK 0xffc00000
339 #define CP_LOAD_STATE_0_NUM_UNIT__SHIFT 22
340 static inline uint32_t CP_LOAD_STATE_0_NUM_UNIT(uint32_t val)
341 {
342 return ((val) << CP_LOAD_STATE_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE_0_NUM_UNIT__MASK;
343 }
344
345 #define REG_CP_LOAD_STATE_1 0x00000001
346 #define CP_LOAD_STATE_1_STATE_TYPE__MASK 0x00000003
347 #define CP_LOAD_STATE_1_STATE_TYPE__SHIFT 0
348 static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val)
349 {
350 return ((val) << CP_LOAD_STATE_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE_1_STATE_TYPE__MASK;
351 }
352 #define CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK 0xfffffffc
353 #define CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT 2
354 static inline uint32_t CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val)
355 {
356 assert(!(val & 0x3));
357 return ((val >> 2) << CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK;
358 }
359
360 #define REG_CP_LOAD_STATE4_0 0x00000000
361 #define CP_LOAD_STATE4_0_DST_OFF__MASK 0x00003fff
362 #define CP_LOAD_STATE4_0_DST_OFF__SHIFT 0
363 static inline uint32_t CP_LOAD_STATE4_0_DST_OFF(uint32_t val)
364 {
365 return ((val) << CP_LOAD_STATE4_0_DST_OFF__SHIFT) & CP_LOAD_STATE4_0_DST_OFF__MASK;
366 }
367 #define CP_LOAD_STATE4_0_STATE_SRC__MASK 0x00030000
368 #define CP_LOAD_STATE4_0_STATE_SRC__SHIFT 16
369 static inline uint32_t CP_LOAD_STATE4_0_STATE_SRC(enum a4xx_state_src val)
370 {
371 return ((val) << CP_LOAD_STATE4_0_STATE_SRC__SHIFT) & CP_LOAD_STATE4_0_STATE_SRC__MASK;
372 }
373 #define CP_LOAD_STATE4_0_STATE_BLOCK__MASK 0x003c0000
374 #define CP_LOAD_STATE4_0_STATE_BLOCK__SHIFT 18
375 static inline uint32_t CP_LOAD_STATE4_0_STATE_BLOCK(enum a4xx_state_block val)
376 {
377 return ((val) << CP_LOAD_STATE4_0_STATE_BLOCK__SHIFT) & CP_LOAD_STATE4_0_STATE_BLOCK__MASK;
378 }
379 #define CP_LOAD_STATE4_0_NUM_UNIT__MASK 0xffc00000
380 #define CP_LOAD_STATE4_0_NUM_UNIT__SHIFT 22
381 static inline uint32_t CP_LOAD_STATE4_0_NUM_UNIT(uint32_t val)
382 {
383 return ((val) << CP_LOAD_STATE4_0_NUM_UNIT__SHIFT) & CP_LOAD_STATE4_0_NUM_UNIT__MASK;
384 }
385
386 #define REG_CP_LOAD_STATE4_1 0x00000001
387 #define CP_LOAD_STATE4_1_STATE_TYPE__MASK 0x00000003
388 #define CP_LOAD_STATE4_1_STATE_TYPE__SHIFT 0
389 static inline uint32_t CP_LOAD_STATE4_1_STATE_TYPE(enum a4xx_state_type val)
390 {
391 return ((val) << CP_LOAD_STATE4_1_STATE_TYPE__SHIFT) & CP_LOAD_STATE4_1_STATE_TYPE__MASK;
392 }
393 #define CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK 0xfffffffc
394 #define CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT 2
395 static inline uint32_t CP_LOAD_STATE4_1_EXT_SRC_ADDR(uint32_t val)
396 {
397 assert(!(val & 0x3));
398 return ((val >> 2) << CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK;
399 }
400
401 #define REG_CP_LOAD_STATE4_2 0x00000002
402 #define CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK 0xffffffff
403 #define CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT 0
404 static inline uint32_t CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI(uint32_t val)
405 {
406 return ((val) << CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__SHIFT) & CP_LOAD_STATE4_2_EXT_SRC_ADDR_HI__MASK;
407 }
408
409 #define REG_CP_DRAW_INDX_0 0x00000000
410 #define CP_DRAW_INDX_0_VIZ_QUERY__MASK 0xffffffff
411 #define CP_DRAW_INDX_0_VIZ_QUERY__SHIFT 0
412 static inline uint32_t CP_DRAW_INDX_0_VIZ_QUERY(uint32_t val)
413 {
414 return ((val) << CP_DRAW_INDX_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_0_VIZ_QUERY__MASK;
415 }
416
417 #define REG_CP_DRAW_INDX_1 0x00000001
418 #define CP_DRAW_INDX_1_PRIM_TYPE__MASK 0x0000003f
419 #define CP_DRAW_INDX_1_PRIM_TYPE__SHIFT 0
420 static inline uint32_t CP_DRAW_INDX_1_PRIM_TYPE(enum pc_di_primtype val)
421 {
422 return ((val) << CP_DRAW_INDX_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_1_PRIM_TYPE__MASK;
423 }
424 #define CP_DRAW_INDX_1_SOURCE_SELECT__MASK 0x000000c0
425 #define CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT 6
426 static inline uint32_t CP_DRAW_INDX_1_SOURCE_SELECT(enum pc_di_src_sel val)
427 {
428 return ((val) << CP_DRAW_INDX_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_1_SOURCE_SELECT__MASK;
429 }
430 #define CP_DRAW_INDX_1_VIS_CULL__MASK 0x00000600
431 #define CP_DRAW_INDX_1_VIS_CULL__SHIFT 9
432 static inline uint32_t CP_DRAW_INDX_1_VIS_CULL(enum pc_di_vis_cull_mode val)
433 {
434 return ((val) << CP_DRAW_INDX_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_1_VIS_CULL__MASK;
435 }
436 #define CP_DRAW_INDX_1_INDEX_SIZE__MASK 0x00000800
437 #define CP_DRAW_INDX_1_INDEX_SIZE__SHIFT 11
438 static inline uint32_t CP_DRAW_INDX_1_INDEX_SIZE(enum pc_di_index_size val)
439 {
440 return ((val) << CP_DRAW_INDX_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_1_INDEX_SIZE__MASK;
441 }
442 #define CP_DRAW_INDX_1_NOT_EOP 0x00001000
443 #define CP_DRAW_INDX_1_SMALL_INDEX 0x00002000
444 #define CP_DRAW_INDX_1_PRE_DRAW_INITIATOR_ENABLE 0x00004000
445 #define CP_DRAW_INDX_1_NUM_INSTANCES__MASK 0xff000000
446 #define CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT 24
447 static inline uint32_t CP_DRAW_INDX_1_NUM_INSTANCES(uint32_t val)
448 {
449 return ((val) << CP_DRAW_INDX_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_1_NUM_INSTANCES__MASK;
450 }
451
452 #define REG_CP_DRAW_INDX_2 0x00000002
453 #define CP_DRAW_INDX_2_NUM_INDICES__MASK 0xffffffff
454 #define CP_DRAW_INDX_2_NUM_INDICES__SHIFT 0
455 static inline uint32_t CP_DRAW_INDX_2_NUM_INDICES(uint32_t val)
456 {
457 return ((val) << CP_DRAW_INDX_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_NUM_INDICES__MASK;
458 }
459
460 #define REG_CP_DRAW_INDX_3 0x00000003
461 #define CP_DRAW_INDX_3_INDX_BASE__MASK 0xffffffff
462 #define CP_DRAW_INDX_3_INDX_BASE__SHIFT 0
463 static inline uint32_t CP_DRAW_INDX_3_INDX_BASE(uint32_t val)
464 {
465 return ((val) << CP_DRAW_INDX_3_INDX_BASE__SHIFT) & CP_DRAW_INDX_3_INDX_BASE__MASK;
466 }
467
468 #define REG_CP_DRAW_INDX_4 0x00000004
469 #define CP_DRAW_INDX_4_INDX_SIZE__MASK 0xffffffff
470 #define CP_DRAW_INDX_4_INDX_SIZE__SHIFT 0
471 static inline uint32_t CP_DRAW_INDX_4_INDX_SIZE(uint32_t val)
472 {
473 return ((val) << CP_DRAW_INDX_4_INDX_SIZE__SHIFT) & CP_DRAW_INDX_4_INDX_SIZE__MASK;
474 }
475
476 #define REG_CP_DRAW_INDX_2_0 0x00000000
477 #define CP_DRAW_INDX_2_0_VIZ_QUERY__MASK 0xffffffff
478 #define CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT 0
479 static inline uint32_t CP_DRAW_INDX_2_0_VIZ_QUERY(uint32_t val)
480 {
481 return ((val) << CP_DRAW_INDX_2_0_VIZ_QUERY__SHIFT) & CP_DRAW_INDX_2_0_VIZ_QUERY__MASK;
482 }
483
484 #define REG_CP_DRAW_INDX_2_1 0x00000001
485 #define CP_DRAW_INDX_2_1_PRIM_TYPE__MASK 0x0000003f
486 #define CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT 0
487 static inline uint32_t CP_DRAW_INDX_2_1_PRIM_TYPE(enum pc_di_primtype val)
488 {
489 return ((val) << CP_DRAW_INDX_2_1_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_2_1_PRIM_TYPE__MASK;
490 }
491 #define CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK 0x000000c0
492 #define CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT 6
493 static inline uint32_t CP_DRAW_INDX_2_1_SOURCE_SELECT(enum pc_di_src_sel val)
494 {
495 return ((val) << CP_DRAW_INDX_2_1_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_2_1_SOURCE_SELECT__MASK;
496 }
497 #define CP_DRAW_INDX_2_1_VIS_CULL__MASK 0x00000600
498 #define CP_DRAW_INDX_2_1_VIS_CULL__SHIFT 9
499 static inline uint32_t CP_DRAW_INDX_2_1_VIS_CULL(enum pc_di_vis_cull_mode val)
500 {
501 return ((val) << CP_DRAW_INDX_2_1_VIS_CULL__SHIFT) & CP_DRAW_INDX_2_1_VIS_CULL__MASK;
502 }
503 #define CP_DRAW_INDX_2_1_INDEX_SIZE__MASK 0x00000800
504 #define CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT 11
505 static inline uint32_t CP_DRAW_INDX_2_1_INDEX_SIZE(enum pc_di_index_size val)
506 {
507 return ((val) << CP_DRAW_INDX_2_1_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_2_1_INDEX_SIZE__MASK;
508 }
509 #define CP_DRAW_INDX_2_1_NOT_EOP 0x00001000
510 #define CP_DRAW_INDX_2_1_SMALL_INDEX 0x00002000
511 #define CP_DRAW_INDX_2_1_PRE_DRAW_INITIATOR_ENABLE 0x00004000
512 #define CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK 0xff000000
513 #define CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT 24
514 static inline uint32_t CP_DRAW_INDX_2_1_NUM_INSTANCES(uint32_t val)
515 {
516 return ((val) << CP_DRAW_INDX_2_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_2_1_NUM_INSTANCES__MASK;
517 }
518
519 #define REG_CP_DRAW_INDX_2_2 0x00000002
520 #define CP_DRAW_INDX_2_2_NUM_INDICES__MASK 0xffffffff
521 #define CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT 0
522 static inline uint32_t CP_DRAW_INDX_2_2_NUM_INDICES(uint32_t val)
523 {
524 return ((val) << CP_DRAW_INDX_2_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_2_2_NUM_INDICES__MASK;
525 }
526
527 #define REG_CP_DRAW_INDX_OFFSET_0 0x00000000
528 #define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK 0x0000003f
529 #define CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT 0
530 static inline uint32_t CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(enum pc_di_primtype val)
531 {
532 return ((val) << CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__SHIFT) & CP_DRAW_INDX_OFFSET_0_PRIM_TYPE__MASK;
533 }
534 #define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK 0x000000c0
535 #define CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT 6
536 static inline uint32_t CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel val)
537 {
538 return ((val) << CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT) & CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK;
539 }
540 #define CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK 0x00000300
541 #define CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT 8
542 static inline uint32_t CP_DRAW_INDX_OFFSET_0_VIS_CULL(enum pc_di_vis_cull_mode val)
543 {
544 return ((val) << CP_DRAW_INDX_OFFSET_0_VIS_CULL__SHIFT) & CP_DRAW_INDX_OFFSET_0_VIS_CULL__MASK;
545 }
546 #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK 0x00000c00
547 #define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT 10
548 static inline uint32_t CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(enum a4xx_index_size val)
549 {
550 return ((val) << CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK;
551 }
552 #define CP_DRAW_INDX_OFFSET_0_TESS_MODE__MASK 0x01f00000
553 #define CP_DRAW_INDX_OFFSET_0_TESS_MODE__SHIFT 20
554 static inline uint32_t CP_DRAW_INDX_OFFSET_0_TESS_MODE(uint32_t val)
555 {
556 return ((val) << CP_DRAW_INDX_OFFSET_0_TESS_MODE__SHIFT) & CP_DRAW_INDX_OFFSET_0_TESS_MODE__MASK;
557 }
558
559 #define REG_CP_DRAW_INDX_OFFSET_1 0x00000001
560 #define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK 0xffffffff
561 #define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT 0
562 static inline uint32_t CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES(uint32_t val)
563 {
564 return ((val) << CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__SHIFT) & CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK;
565 }
566
567 #define REG_CP_DRAW_INDX_OFFSET_2 0x00000002
568 #define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK 0xffffffff
569 #define CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT 0
570 static inline uint32_t CP_DRAW_INDX_OFFSET_2_NUM_INDICES(uint32_t val)
571 {
572 return ((val) << CP_DRAW_INDX_OFFSET_2_NUM_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_2_NUM_INDICES__MASK;
573 }
574
575 #define REG_CP_DRAW_INDX_OFFSET_3 0x00000003
576
577 #define REG_CP_DRAW_INDX_OFFSET_4 0x00000004
578 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK 0xffffffff
579 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT 0
580 static inline uint32_t CP_DRAW_INDX_OFFSET_4_INDX_BASE(uint32_t val)
581 {
582 return ((val) << CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT) & CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK;
583 }
584
585 #define REG_CP_DRAW_INDX_OFFSET_5 0x00000005
586 #define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK 0xffffffff
587 #define CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT 0
588 static inline uint32_t CP_DRAW_INDX_OFFSET_5_INDX_SIZE(uint32_t val)
589 {
590 return ((val) << CP_DRAW_INDX_OFFSET_5_INDX_SIZE__SHIFT) & CP_DRAW_INDX_OFFSET_5_INDX_SIZE__MASK;
591 }
592
593 #define REG_A4XX_CP_DRAW_INDIRECT_0 0x00000000
594 #define A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__MASK 0x0000003f
595 #define A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT 0
596 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val)
597 {
598 return ((val) << A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_PRIM_TYPE__MASK;
599 }
600 #define A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__MASK 0x000000c0
601 #define A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__SHIFT 6
602 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val)
603 {
604 return ((val) << A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_SOURCE_SELECT__MASK;
605 }
606 #define A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__MASK 0x00000300
607 #define A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__SHIFT 8
608 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val)
609 {
610 return ((val) << A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_VIS_CULL__MASK;
611 }
612 #define A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__MASK 0x00000c00
613 #define A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT 10
614 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val)
615 {
616 return ((val) << A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_INDEX_SIZE__MASK;
617 }
618 #define A4XX_CP_DRAW_INDIRECT_0_TESS_MODE__MASK 0x01f00000
619 #define A4XX_CP_DRAW_INDIRECT_0_TESS_MODE__SHIFT 20
620 static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_TESS_MODE(uint32_t val)
621 {
622 return ((val) << A4XX_CP_DRAW_INDIRECT_0_TESS_MODE__SHIFT) & A4XX_CP_DRAW_INDIRECT_0_TESS_MODE__MASK;
623 }
624
625 #define REG_A4XX_CP_DRAW_INDIRECT_1 0x00000001
626 #define A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK 0xffffffff
627 #define A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT 0
628 static inline uint32_t A4XX_CP_DRAW_INDIRECT_1_INDIRECT(uint32_t val)
629 {
630 return ((val) << A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT) & A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK;
631 }
632
633
634 #define REG_A5XX_CP_DRAW_INDIRECT_2 0x00000002
635 #define A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK 0xffffffff
636 #define A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT 0
637 static inline uint32_t A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI(uint32_t val)
638 {
639 return ((val) << A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__SHIFT) & A5XX_CP_DRAW_INDIRECT_2_INDIRECT_HI__MASK;
640 }
641
642 #define REG_A4XX_CP_DRAW_INDX_INDIRECT_0 0x00000000
643 #define A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__MASK 0x0000003f
644 #define A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT 0
645 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE(enum pc_di_primtype val)
646 {
647 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_PRIM_TYPE__MASK;
648 }
649 #define A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__MASK 0x000000c0
650 #define A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__SHIFT 6
651 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT(enum pc_di_src_sel val)
652 {
653 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_SOURCE_SELECT__MASK;
654 }
655 #define A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__MASK 0x00000300
656 #define A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__SHIFT 8
657 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL(enum pc_di_vis_cull_mode val)
658 {
659 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_VIS_CULL__MASK;
660 }
661 #define A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__MASK 0x00000c00
662 #define A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT 10
663 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE(enum a4xx_index_size val)
664 {
665 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_INDEX_SIZE__MASK;
666 }
667 #define A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE__MASK 0x01f00000
668 #define A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE__SHIFT 20
669 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE(uint32_t val)
670 {
671 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_MODE__MASK;
672 }
673
674
675 #define REG_A4XX_CP_DRAW_INDX_INDIRECT_1 0x00000001
676 #define A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__MASK 0xffffffff
677 #define A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__SHIFT 0
678 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE(uint32_t val)
679 {
680 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__MASK;
681 }
682
683 #define REG_A4XX_CP_DRAW_INDX_INDIRECT_2 0x00000002
684 #define A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__MASK 0xffffffff
685 #define A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__SHIFT 0
686 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE(uint32_t val)
687 {
688 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_2_INDX_SIZE__MASK;
689 }
690
691 #define REG_A4XX_CP_DRAW_INDX_INDIRECT_3 0x00000003
692 #define A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__MASK 0xffffffff
693 #define A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__SHIFT 0
694 static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT(uint32_t val)
695 {
696 return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__MASK;
697 }
698
699
700 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_1 0x00000001
701 #define A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__MASK 0xffffffff
702 #define A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT 0
703 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO(uint32_t val)
704 {
705 return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__MASK;
706 }
707
708 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_2 0x00000002
709 #define A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__MASK 0xffffffff
710 #define A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT 0
711 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI(uint32_t val)
712 {
713 return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_2_INDX_BASE_HI__MASK;
714 }
715
716 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_3 0x00000003
717 #define A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__MASK 0xffffffff
718 #define A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT 0
719 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(uint32_t val)
720 {
721 return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES__MASK;
722 }
723
724 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_4 0x00000004
725 #define A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__MASK 0xffffffff
726 #define A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT 0
727 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO(uint32_t val)
728 {
729 return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_4_INDIRECT_LO__MASK;
730 }
731
732 #define REG_A5XX_CP_DRAW_INDX_INDIRECT_5 0x00000005
733 #define A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__MASK 0xffffffff
734 #define A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT 0
735 static inline uint32_t A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI(uint32_t val)
736 {
737 return ((val) << A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__SHIFT) & A5XX_CP_DRAW_INDX_INDIRECT_5_INDIRECT_HI__MASK;
738 }
739
740 static inline uint32_t REG_CP_SET_DRAW_STATE_(uint32_t i0) { return 0x00000000 + 0x3*i0; }
741
742 static inline uint32_t REG_CP_SET_DRAW_STATE__0(uint32_t i0) { return 0x00000000 + 0x3*i0; }
743 #define CP_SET_DRAW_STATE__0_COUNT__MASK 0x0000ffff
744 #define CP_SET_DRAW_STATE__0_COUNT__SHIFT 0
745 static inline uint32_t CP_SET_DRAW_STATE__0_COUNT(uint32_t val)
746 {
747 return ((val) << CP_SET_DRAW_STATE__0_COUNT__SHIFT) & CP_SET_DRAW_STATE__0_COUNT__MASK;
748 }
749 #define CP_SET_DRAW_STATE__0_DIRTY 0x00010000
750 #define CP_SET_DRAW_STATE__0_DISABLE 0x00020000
751 #define CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS 0x00040000
752 #define CP_SET_DRAW_STATE__0_LOAD_IMMED 0x00080000
753 #define CP_SET_DRAW_STATE__0_GROUP_ID__MASK 0x1f000000
754 #define CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT 24
755 static inline uint32_t CP_SET_DRAW_STATE__0_GROUP_ID(uint32_t val)
756 {
757 return ((val) << CP_SET_DRAW_STATE__0_GROUP_ID__SHIFT) & CP_SET_DRAW_STATE__0_GROUP_ID__MASK;
758 }
759
760 static inline uint32_t REG_CP_SET_DRAW_STATE__1(uint32_t i0) { return 0x00000001 + 0x3*i0; }
761 #define CP_SET_DRAW_STATE__1_ADDR_LO__MASK 0xffffffff
762 #define CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT 0
763 static inline uint32_t CP_SET_DRAW_STATE__1_ADDR_LO(uint32_t val)
764 {
765 return ((val) << CP_SET_DRAW_STATE__1_ADDR_LO__SHIFT) & CP_SET_DRAW_STATE__1_ADDR_LO__MASK;
766 }
767
768 static inline uint32_t REG_CP_SET_DRAW_STATE__2(uint32_t i0) { return 0x00000002 + 0x3*i0; }
769 #define CP_SET_DRAW_STATE__2_ADDR_HI__MASK 0xffffffff
770 #define CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT 0
771 static inline uint32_t CP_SET_DRAW_STATE__2_ADDR_HI(uint32_t val)
772 {
773 return ((val) << CP_SET_DRAW_STATE__2_ADDR_HI__SHIFT) & CP_SET_DRAW_STATE__2_ADDR_HI__MASK;
774 }
775
776 #define REG_CP_SET_BIN_0 0x00000000
777
778 #define REG_CP_SET_BIN_1 0x00000001
779 #define CP_SET_BIN_1_X1__MASK 0x0000ffff
780 #define CP_SET_BIN_1_X1__SHIFT 0
781 static inline uint32_t CP_SET_BIN_1_X1(uint32_t val)
782 {
783 return ((val) << CP_SET_BIN_1_X1__SHIFT) & CP_SET_BIN_1_X1__MASK;
784 }
785 #define CP_SET_BIN_1_Y1__MASK 0xffff0000
786 #define CP_SET_BIN_1_Y1__SHIFT 16
787 static inline uint32_t CP_SET_BIN_1_Y1(uint32_t val)
788 {
789 return ((val) << CP_SET_BIN_1_Y1__SHIFT) & CP_SET_BIN_1_Y1__MASK;
790 }
791
792 #define REG_CP_SET_BIN_2 0x00000002
793 #define CP_SET_BIN_2_X2__MASK 0x0000ffff
794 #define CP_SET_BIN_2_X2__SHIFT 0
795 static inline uint32_t CP_SET_BIN_2_X2(uint32_t val)
796 {
797 return ((val) << CP_SET_BIN_2_X2__SHIFT) & CP_SET_BIN_2_X2__MASK;
798 }
799 #define CP_SET_BIN_2_Y2__MASK 0xffff0000
800 #define CP_SET_BIN_2_Y2__SHIFT 16
801 static inline uint32_t CP_SET_BIN_2_Y2(uint32_t val)
802 {
803 return ((val) << CP_SET_BIN_2_Y2__SHIFT) & CP_SET_BIN_2_Y2__MASK;
804 }
805
806 #define REG_CP_SET_BIN_DATA_0 0x00000000
807 #define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK 0xffffffff
808 #define CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT 0
809 static inline uint32_t CP_SET_BIN_DATA_0_BIN_DATA_ADDR(uint32_t val)
810 {
811 return ((val) << CP_SET_BIN_DATA_0_BIN_DATA_ADDR__SHIFT) & CP_SET_BIN_DATA_0_BIN_DATA_ADDR__MASK;
812 }
813
814 #define REG_CP_SET_BIN_DATA_1 0x00000001
815 #define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK 0xffffffff
816 #define CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT 0
817 static inline uint32_t CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS(uint32_t val)
818 {
819 return ((val) << CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__SHIFT) & CP_SET_BIN_DATA_1_BIN_SIZE_ADDRESS__MASK;
820 }
821
822 #define REG_CP_SET_BIN_DATA5_0 0x00000000
823 #define CP_SET_BIN_DATA5_0_VSC_SIZE__MASK 0x003f0000
824 #define CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT 16
825 static inline uint32_t CP_SET_BIN_DATA5_0_VSC_SIZE(uint32_t val)
826 {
827 return ((val) << CP_SET_BIN_DATA5_0_VSC_SIZE__SHIFT) & CP_SET_BIN_DATA5_0_VSC_SIZE__MASK;
828 }
829 #define CP_SET_BIN_DATA5_0_VSC_N__MASK 0x07c00000
830 #define CP_SET_BIN_DATA5_0_VSC_N__SHIFT 22
831 static inline uint32_t CP_SET_BIN_DATA5_0_VSC_N(uint32_t val)
832 {
833 return ((val) << CP_SET_BIN_DATA5_0_VSC_N__SHIFT) & CP_SET_BIN_DATA5_0_VSC_N__MASK;
834 }
835
836 #define REG_CP_SET_BIN_DATA5_1 0x00000001
837 #define CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK 0xffffffff
838 #define CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT 0
839 static inline uint32_t CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO(uint32_t val)
840 {
841 return ((val) << CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__SHIFT) & CP_SET_BIN_DATA5_1_BIN_DATA_ADDR_LO__MASK;
842 }
843
844 #define REG_CP_SET_BIN_DATA5_2 0x00000002
845 #define CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK 0xffffffff
846 #define CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT 0
847 static inline uint32_t CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI(uint32_t val)
848 {
849 return ((val) << CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__SHIFT) & CP_SET_BIN_DATA5_2_BIN_DATA_ADDR_HI__MASK;
850 }
851
852 #define REG_CP_SET_BIN_DATA5_3 0x00000003
853 #define CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK 0xffffffff
854 #define CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT 0
855 static inline uint32_t CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO(uint32_t val)
856 {
857 return ((val) << CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__SHIFT) & CP_SET_BIN_DATA5_3_BIN_SIZE_ADDRESS_LO__MASK;
858 }
859
860 #define REG_CP_SET_BIN_DATA5_4 0x00000004
861 #define CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK 0xffffffff
862 #define CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT 0
863 static inline uint32_t CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI(uint32_t val)
864 {
865 return ((val) << CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__SHIFT) & CP_SET_BIN_DATA5_4_BIN_SIZE_ADDRESS_HI__MASK;
866 }
867
868 #define REG_CP_REG_TO_MEM_0 0x00000000
869 #define CP_REG_TO_MEM_0_REG__MASK 0x0000ffff
870 #define CP_REG_TO_MEM_0_REG__SHIFT 0
871 static inline uint32_t CP_REG_TO_MEM_0_REG(uint32_t val)
872 {
873 return ((val) << CP_REG_TO_MEM_0_REG__SHIFT) & CP_REG_TO_MEM_0_REG__MASK;
874 }
875 #define CP_REG_TO_MEM_0_CNT__MASK 0x3ff80000
876 #define CP_REG_TO_MEM_0_CNT__SHIFT 19
877 static inline uint32_t CP_REG_TO_MEM_0_CNT(uint32_t val)
878 {
879 return ((val) << CP_REG_TO_MEM_0_CNT__SHIFT) & CP_REG_TO_MEM_0_CNT__MASK;
880 }
881 #define CP_REG_TO_MEM_0_64B 0x40000000
882 #define CP_REG_TO_MEM_0_ACCUMULATE 0x80000000
883
884 #define REG_CP_REG_TO_MEM_1 0x00000001
885 #define CP_REG_TO_MEM_1_DEST__MASK 0xffffffff
886 #define CP_REG_TO_MEM_1_DEST__SHIFT 0
887 static inline uint32_t CP_REG_TO_MEM_1_DEST(uint32_t val)
888 {
889 return ((val) << CP_REG_TO_MEM_1_DEST__SHIFT) & CP_REG_TO_MEM_1_DEST__MASK;
890 }
891
892 #define REG_CP_MEM_TO_MEM_0 0x00000000
893 #define CP_MEM_TO_MEM_0_NEG_A 0x00000001
894 #define CP_MEM_TO_MEM_0_NEG_B 0x00000002
895 #define CP_MEM_TO_MEM_0_NEG_C 0x00000004
896 #define CP_MEM_TO_MEM_0_DOUBLE 0x20000000
897
898 #define REG_CP_COND_WRITE_0 0x00000000
899 #define CP_COND_WRITE_0_FUNCTION__MASK 0x00000007
900 #define CP_COND_WRITE_0_FUNCTION__SHIFT 0
901 static inline uint32_t CP_COND_WRITE_0_FUNCTION(enum cp_cond_function val)
902 {
903 return ((val) << CP_COND_WRITE_0_FUNCTION__SHIFT) & CP_COND_WRITE_0_FUNCTION__MASK;
904 }
905 #define CP_COND_WRITE_0_POLL_MEMORY 0x00000010
906 #define CP_COND_WRITE_0_WRITE_MEMORY 0x00000100
907
908 #define REG_CP_COND_WRITE_1 0x00000001
909 #define CP_COND_WRITE_1_POLL_ADDR__MASK 0xffffffff
910 #define CP_COND_WRITE_1_POLL_ADDR__SHIFT 0
911 static inline uint32_t CP_COND_WRITE_1_POLL_ADDR(uint32_t val)
912 {
913 return ((val) << CP_COND_WRITE_1_POLL_ADDR__SHIFT) & CP_COND_WRITE_1_POLL_ADDR__MASK;
914 }
915
916 #define REG_CP_COND_WRITE_2 0x00000002
917 #define CP_COND_WRITE_2_REF__MASK 0xffffffff
918 #define CP_COND_WRITE_2_REF__SHIFT 0
919 static inline uint32_t CP_COND_WRITE_2_REF(uint32_t val)
920 {
921 return ((val) << CP_COND_WRITE_2_REF__SHIFT) & CP_COND_WRITE_2_REF__MASK;
922 }
923
924 #define REG_CP_COND_WRITE_3 0x00000003
925 #define CP_COND_WRITE_3_MASK__MASK 0xffffffff
926 #define CP_COND_WRITE_3_MASK__SHIFT 0
927 static inline uint32_t CP_COND_WRITE_3_MASK(uint32_t val)
928 {
929 return ((val) << CP_COND_WRITE_3_MASK__SHIFT) & CP_COND_WRITE_3_MASK__MASK;
930 }
931
932 #define REG_CP_COND_WRITE_4 0x00000004
933 #define CP_COND_WRITE_4_WRITE_ADDR__MASK 0xffffffff
934 #define CP_COND_WRITE_4_WRITE_ADDR__SHIFT 0
935 static inline uint32_t CP_COND_WRITE_4_WRITE_ADDR(uint32_t val)
936 {
937 return ((val) << CP_COND_WRITE_4_WRITE_ADDR__SHIFT) & CP_COND_WRITE_4_WRITE_ADDR__MASK;
938 }
939
940 #define REG_CP_COND_WRITE_5 0x00000005
941 #define CP_COND_WRITE_5_WRITE_DATA__MASK 0xffffffff
942 #define CP_COND_WRITE_5_WRITE_DATA__SHIFT 0
943 static inline uint32_t CP_COND_WRITE_5_WRITE_DATA(uint32_t val)
944 {
945 return ((val) << CP_COND_WRITE_5_WRITE_DATA__SHIFT) & CP_COND_WRITE_5_WRITE_DATA__MASK;
946 }
947
948 #define REG_CP_COND_WRITE5_0 0x00000000
949 #define CP_COND_WRITE5_0_FUNCTION__MASK 0x00000007
950 #define CP_COND_WRITE5_0_FUNCTION__SHIFT 0
951 static inline uint32_t CP_COND_WRITE5_0_FUNCTION(enum cp_cond_function val)
952 {
953 return ((val) << CP_COND_WRITE5_0_FUNCTION__SHIFT) & CP_COND_WRITE5_0_FUNCTION__MASK;
954 }
955 #define CP_COND_WRITE5_0_POLL_MEMORY 0x00000010
956 #define CP_COND_WRITE5_0_WRITE_MEMORY 0x00000100
957
958 #define REG_CP_COND_WRITE5_1 0x00000001
959 #define CP_COND_WRITE5_1_POLL_ADDR_LO__MASK 0xffffffff
960 #define CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT 0
961 static inline uint32_t CP_COND_WRITE5_1_POLL_ADDR_LO(uint32_t val)
962 {
963 return ((val) << CP_COND_WRITE5_1_POLL_ADDR_LO__SHIFT) & CP_COND_WRITE5_1_POLL_ADDR_LO__MASK;
964 }
965
966 #define REG_CP_COND_WRITE5_2 0x00000002
967 #define CP_COND_WRITE5_2_POLL_ADDR_HI__MASK 0xffffffff
968 #define CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT 0
969 static inline uint32_t CP_COND_WRITE5_2_POLL_ADDR_HI(uint32_t val)
970 {
971 return ((val) << CP_COND_WRITE5_2_POLL_ADDR_HI__SHIFT) & CP_COND_WRITE5_2_POLL_ADDR_HI__MASK;
972 }
973
974 #define REG_CP_COND_WRITE5_3 0x00000003
975 #define CP_COND_WRITE5_3_REF__MASK 0xffffffff
976 #define CP_COND_WRITE5_3_REF__SHIFT 0
977 static inline uint32_t CP_COND_WRITE5_3_REF(uint32_t val)
978 {
979 return ((val) << CP_COND_WRITE5_3_REF__SHIFT) & CP_COND_WRITE5_3_REF__MASK;
980 }
981
982 #define REG_CP_COND_WRITE5_4 0x00000004
983 #define CP_COND_WRITE5_4_MASK__MASK 0xffffffff
984 #define CP_COND_WRITE5_4_MASK__SHIFT 0
985 static inline uint32_t CP_COND_WRITE5_4_MASK(uint32_t val)
986 {
987 return ((val) << CP_COND_WRITE5_4_MASK__SHIFT) & CP_COND_WRITE5_4_MASK__MASK;
988 }
989
990 #define REG_CP_COND_WRITE5_5 0x00000005
991 #define CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK 0xffffffff
992 #define CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT 0
993 static inline uint32_t CP_COND_WRITE5_5_WRITE_ADDR_LO(uint32_t val)
994 {
995 return ((val) << CP_COND_WRITE5_5_WRITE_ADDR_LO__SHIFT) & CP_COND_WRITE5_5_WRITE_ADDR_LO__MASK;
996 }
997
998 #define REG_CP_COND_WRITE5_6 0x00000006
999 #define CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK 0xffffffff
1000 #define CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT 0
1001 static inline uint32_t CP_COND_WRITE5_6_WRITE_ADDR_HI(uint32_t val)
1002 {
1003 return ((val) << CP_COND_WRITE5_6_WRITE_ADDR_HI__SHIFT) & CP_COND_WRITE5_6_WRITE_ADDR_HI__MASK;
1004 }
1005
1006 #define REG_CP_COND_WRITE5_7 0x00000007
1007 #define CP_COND_WRITE5_7_WRITE_DATA__MASK 0xffffffff
1008 #define CP_COND_WRITE5_7_WRITE_DATA__SHIFT 0
1009 static inline uint32_t CP_COND_WRITE5_7_WRITE_DATA(uint32_t val)
1010 {
1011 return ((val) << CP_COND_WRITE5_7_WRITE_DATA__SHIFT) & CP_COND_WRITE5_7_WRITE_DATA__MASK;
1012 }
1013
1014 #define REG_CP_DISPATCH_COMPUTE_0 0x00000000
1015
1016 #define REG_CP_DISPATCH_COMPUTE_1 0x00000001
1017 #define CP_DISPATCH_COMPUTE_1_X__MASK 0xffffffff
1018 #define CP_DISPATCH_COMPUTE_1_X__SHIFT 0
1019 static inline uint32_t CP_DISPATCH_COMPUTE_1_X(uint32_t val)
1020 {
1021 return ((val) << CP_DISPATCH_COMPUTE_1_X__SHIFT) & CP_DISPATCH_COMPUTE_1_X__MASK;
1022 }
1023
1024 #define REG_CP_DISPATCH_COMPUTE_2 0x00000002
1025 #define CP_DISPATCH_COMPUTE_2_Y__MASK 0xffffffff
1026 #define CP_DISPATCH_COMPUTE_2_Y__SHIFT 0
1027 static inline uint32_t CP_DISPATCH_COMPUTE_2_Y(uint32_t val)
1028 {
1029 return ((val) << CP_DISPATCH_COMPUTE_2_Y__SHIFT) & CP_DISPATCH_COMPUTE_2_Y__MASK;
1030 }
1031
1032 #define REG_CP_DISPATCH_COMPUTE_3 0x00000003
1033 #define CP_DISPATCH_COMPUTE_3_Z__MASK 0xffffffff
1034 #define CP_DISPATCH_COMPUTE_3_Z__SHIFT 0
1035 static inline uint32_t CP_DISPATCH_COMPUTE_3_Z(uint32_t val)
1036 {
1037 return ((val) << CP_DISPATCH_COMPUTE_3_Z__SHIFT) & CP_DISPATCH_COMPUTE_3_Z__MASK;
1038 }
1039
1040 #define REG_CP_SET_RENDER_MODE_0 0x00000000
1041 #define CP_SET_RENDER_MODE_0_MODE__MASK 0x000001ff
1042 #define CP_SET_RENDER_MODE_0_MODE__SHIFT 0
1043 static inline uint32_t CP_SET_RENDER_MODE_0_MODE(enum render_mode_cmd val)
1044 {
1045 return ((val) << CP_SET_RENDER_MODE_0_MODE__SHIFT) & CP_SET_RENDER_MODE_0_MODE__MASK;
1046 }
1047
1048 #define REG_CP_SET_RENDER_MODE_1 0x00000001
1049 #define CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK 0xffffffff
1050 #define CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT 0
1051 static inline uint32_t CP_SET_RENDER_MODE_1_ADDR_0_LO(uint32_t val)
1052 {
1053 return ((val) << CP_SET_RENDER_MODE_1_ADDR_0_LO__SHIFT) & CP_SET_RENDER_MODE_1_ADDR_0_LO__MASK;
1054 }
1055
1056 #define REG_CP_SET_RENDER_MODE_2 0x00000002
1057 #define CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK 0xffffffff
1058 #define CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT 0
1059 static inline uint32_t CP_SET_RENDER_MODE_2_ADDR_0_HI(uint32_t val)
1060 {
1061 return ((val) << CP_SET_RENDER_MODE_2_ADDR_0_HI__SHIFT) & CP_SET_RENDER_MODE_2_ADDR_0_HI__MASK;
1062 }
1063
1064 #define REG_CP_SET_RENDER_MODE_3 0x00000003
1065 #define CP_SET_RENDER_MODE_3_VSC_ENABLE 0x00000008
1066 #define CP_SET_RENDER_MODE_3_GMEM_ENABLE 0x00000010
1067
1068 #define REG_CP_SET_RENDER_MODE_4 0x00000004
1069
1070 #define REG_CP_SET_RENDER_MODE_5 0x00000005
1071 #define CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK 0xffffffff
1072 #define CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT 0
1073 static inline uint32_t CP_SET_RENDER_MODE_5_ADDR_1_LEN(uint32_t val)
1074 {
1075 return ((val) << CP_SET_RENDER_MODE_5_ADDR_1_LEN__SHIFT) & CP_SET_RENDER_MODE_5_ADDR_1_LEN__MASK;
1076 }
1077
1078 #define REG_CP_SET_RENDER_MODE_6 0x00000006
1079 #define CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK 0xffffffff
1080 #define CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT 0
1081 static inline uint32_t CP_SET_RENDER_MODE_6_ADDR_1_LO(uint32_t val)
1082 {
1083 return ((val) << CP_SET_RENDER_MODE_6_ADDR_1_LO__SHIFT) & CP_SET_RENDER_MODE_6_ADDR_1_LO__MASK;
1084 }
1085
1086 #define REG_CP_SET_RENDER_MODE_7 0x00000007
1087 #define CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK 0xffffffff
1088 #define CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT 0
1089 static inline uint32_t CP_SET_RENDER_MODE_7_ADDR_1_HI(uint32_t val)
1090 {
1091 return ((val) << CP_SET_RENDER_MODE_7_ADDR_1_HI__SHIFT) & CP_SET_RENDER_MODE_7_ADDR_1_HI__MASK;
1092 }
1093
1094 #define REG_CP_COMPUTE_CHECKPOINT_0 0x00000000
1095 #define CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MASK 0xffffffff
1096 #define CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT 0
1097 static inline uint32_t CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO(uint32_t val)
1098 {
1099 return ((val) << CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__SHIFT) & CP_COMPUTE_CHECKPOINT_0_ADDR_0_LO__MASK;
1100 }
1101
1102 #define REG_CP_COMPUTE_CHECKPOINT_1 0x00000001
1103 #define CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MASK 0xffffffff
1104 #define CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT 0
1105 static inline uint32_t CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI(uint32_t val)
1106 {
1107 return ((val) << CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__SHIFT) & CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI__MASK;
1108 }
1109
1110 #define REG_CP_COMPUTE_CHECKPOINT_2 0x00000002
1111
1112 #define REG_CP_COMPUTE_CHECKPOINT_3 0x00000003
1113 #define CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__MASK 0xffffffff
1114 #define CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__SHIFT 0
1115 static inline uint32_t CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN(uint32_t val)
1116 {
1117 return ((val) << CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__SHIFT) & CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__MASK;
1118 }
1119
1120 #define REG_CP_COMPUTE_CHECKPOINT_4 0x00000004
1121
1122 #define REG_CP_COMPUTE_CHECKPOINT_5 0x00000005
1123 #define CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK 0xffffffff
1124 #define CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT 0
1125 static inline uint32_t CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO(uint32_t val)
1126 {
1127 return ((val) << CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__SHIFT) & CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK;
1128 }
1129
1130 #define REG_CP_COMPUTE_CHECKPOINT_6 0x00000006
1131 #define CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MASK 0xffffffff
1132 #define CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT 0
1133 static inline uint32_t CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI(uint32_t val)
1134 {
1135 return ((val) << CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__SHIFT) & CP_COMPUTE_CHECKPOINT_6_ADDR_1_HI__MASK;
1136 }
1137
1138 #define REG_CP_COMPUTE_CHECKPOINT_7 0x00000007
1139
1140 #define REG_CP_PERFCOUNTER_ACTION_0 0x00000000
1141
1142 #define REG_CP_PERFCOUNTER_ACTION_1 0x00000001
1143 #define CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK 0xffffffff
1144 #define CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT 0
1145 static inline uint32_t CP_PERFCOUNTER_ACTION_1_ADDR_0_LO(uint32_t val)
1146 {
1147 return ((val) << CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__SHIFT) & CP_PERFCOUNTER_ACTION_1_ADDR_0_LO__MASK;
1148 }
1149
1150 #define REG_CP_PERFCOUNTER_ACTION_2 0x00000002
1151 #define CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK 0xffffffff
1152 #define CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT 0
1153 static inline uint32_t CP_PERFCOUNTER_ACTION_2_ADDR_0_HI(uint32_t val)
1154 {
1155 return ((val) << CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__SHIFT) & CP_PERFCOUNTER_ACTION_2_ADDR_0_HI__MASK;
1156 }
1157
1158 #define REG_CP_EVENT_WRITE_0 0x00000000
1159 #define CP_EVENT_WRITE_0_EVENT__MASK 0x000000ff
1160 #define CP_EVENT_WRITE_0_EVENT__SHIFT 0
1161 static inline uint32_t CP_EVENT_WRITE_0_EVENT(enum vgt_event_type val)
1162 {
1163 return ((val) << CP_EVENT_WRITE_0_EVENT__SHIFT) & CP_EVENT_WRITE_0_EVENT__MASK;
1164 }
1165 #define CP_EVENT_WRITE_0_TIMESTAMP 0x40000000
1166
1167 #define REG_CP_EVENT_WRITE_1 0x00000001
1168 #define CP_EVENT_WRITE_1_ADDR_0_LO__MASK 0xffffffff
1169 #define CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT 0
1170 static inline uint32_t CP_EVENT_WRITE_1_ADDR_0_LO(uint32_t val)
1171 {
1172 return ((val) << CP_EVENT_WRITE_1_ADDR_0_LO__SHIFT) & CP_EVENT_WRITE_1_ADDR_0_LO__MASK;
1173 }
1174
1175 #define REG_CP_EVENT_WRITE_2 0x00000002
1176 #define CP_EVENT_WRITE_2_ADDR_0_HI__MASK 0xffffffff
1177 #define CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT 0
1178 static inline uint32_t CP_EVENT_WRITE_2_ADDR_0_HI(uint32_t val)
1179 {
1180 return ((val) << CP_EVENT_WRITE_2_ADDR_0_HI__SHIFT) & CP_EVENT_WRITE_2_ADDR_0_HI__MASK;
1181 }
1182
1183 #define REG_CP_EVENT_WRITE_3 0x00000003
1184
1185 #define REG_CP_BLIT_0 0x00000000
1186 #define CP_BLIT_0_OP__MASK 0x0000000f
1187 #define CP_BLIT_0_OP__SHIFT 0
1188 static inline uint32_t CP_BLIT_0_OP(enum cp_blit_cmd val)
1189 {
1190 return ((val) << CP_BLIT_0_OP__SHIFT) & CP_BLIT_0_OP__MASK;
1191 }
1192
1193 #define REG_CP_BLIT_1 0x00000001
1194 #define CP_BLIT_1_SRC_X1__MASK 0x00003fff
1195 #define CP_BLIT_1_SRC_X1__SHIFT 0
1196 static inline uint32_t CP_BLIT_1_SRC_X1(uint32_t val)
1197 {
1198 return ((val) << CP_BLIT_1_SRC_X1__SHIFT) & CP_BLIT_1_SRC_X1__MASK;
1199 }
1200 #define CP_BLIT_1_SRC_Y1__MASK 0x3fff0000
1201 #define CP_BLIT_1_SRC_Y1__SHIFT 16
1202 static inline uint32_t CP_BLIT_1_SRC_Y1(uint32_t val)
1203 {
1204 return ((val) << CP_BLIT_1_SRC_Y1__SHIFT) & CP_BLIT_1_SRC_Y1__MASK;
1205 }
1206
1207 #define REG_CP_BLIT_2 0x00000002
1208 #define CP_BLIT_2_SRC_X2__MASK 0x00003fff
1209 #define CP_BLIT_2_SRC_X2__SHIFT 0
1210 static inline uint32_t CP_BLIT_2_SRC_X2(uint32_t val)
1211 {
1212 return ((val) << CP_BLIT_2_SRC_X2__SHIFT) & CP_BLIT_2_SRC_X2__MASK;
1213 }
1214 #define CP_BLIT_2_SRC_Y2__MASK 0x3fff0000
1215 #define CP_BLIT_2_SRC_Y2__SHIFT 16
1216 static inline uint32_t CP_BLIT_2_SRC_Y2(uint32_t val)
1217 {
1218 return ((val) << CP_BLIT_2_SRC_Y2__SHIFT) & CP_BLIT_2_SRC_Y2__MASK;
1219 }
1220
1221 #define REG_CP_BLIT_3 0x00000003
1222 #define CP_BLIT_3_DST_X1__MASK 0x00003fff
1223 #define CP_BLIT_3_DST_X1__SHIFT 0
1224 static inline uint32_t CP_BLIT_3_DST_X1(uint32_t val)
1225 {
1226 return ((val) << CP_BLIT_3_DST_X1__SHIFT) & CP_BLIT_3_DST_X1__MASK;
1227 }
1228 #define CP_BLIT_3_DST_Y1__MASK 0x3fff0000
1229 #define CP_BLIT_3_DST_Y1__SHIFT 16
1230 static inline uint32_t CP_BLIT_3_DST_Y1(uint32_t val)
1231 {
1232 return ((val) << CP_BLIT_3_DST_Y1__SHIFT) & CP_BLIT_3_DST_Y1__MASK;
1233 }
1234
1235 #define REG_CP_BLIT_4 0x00000004
1236 #define CP_BLIT_4_DST_X2__MASK 0x00003fff
1237 #define CP_BLIT_4_DST_X2__SHIFT 0
1238 static inline uint32_t CP_BLIT_4_DST_X2(uint32_t val)
1239 {
1240 return ((val) << CP_BLIT_4_DST_X2__SHIFT) & CP_BLIT_4_DST_X2__MASK;
1241 }
1242 #define CP_BLIT_4_DST_Y2__MASK 0x3fff0000
1243 #define CP_BLIT_4_DST_Y2__SHIFT 16
1244 static inline uint32_t CP_BLIT_4_DST_Y2(uint32_t val)
1245 {
1246 return ((val) << CP_BLIT_4_DST_Y2__SHIFT) & CP_BLIT_4_DST_Y2__MASK;
1247 }
1248
1249 #define REG_CP_EXEC_CS_0 0x00000000
1250
1251 #define REG_CP_EXEC_CS_1 0x00000001
1252 #define CP_EXEC_CS_1_NGROUPS_X__MASK 0xffffffff
1253 #define CP_EXEC_CS_1_NGROUPS_X__SHIFT 0
1254 static inline uint32_t CP_EXEC_CS_1_NGROUPS_X(uint32_t val)
1255 {
1256 return ((val) << CP_EXEC_CS_1_NGROUPS_X__SHIFT) & CP_EXEC_CS_1_NGROUPS_X__MASK;
1257 }
1258
1259 #define REG_CP_EXEC_CS_2 0x00000002
1260 #define CP_EXEC_CS_2_NGROUPS_Y__MASK 0xffffffff
1261 #define CP_EXEC_CS_2_NGROUPS_Y__SHIFT 0
1262 static inline uint32_t CP_EXEC_CS_2_NGROUPS_Y(uint32_t val)
1263 {
1264 return ((val) << CP_EXEC_CS_2_NGROUPS_Y__SHIFT) & CP_EXEC_CS_2_NGROUPS_Y__MASK;
1265 }
1266
1267 #define REG_CP_EXEC_CS_3 0x00000003
1268 #define CP_EXEC_CS_3_NGROUPS_Z__MASK 0xffffffff
1269 #define CP_EXEC_CS_3_NGROUPS_Z__SHIFT 0
1270 static inline uint32_t CP_EXEC_CS_3_NGROUPS_Z(uint32_t val)
1271 {
1272 return ((val) << CP_EXEC_CS_3_NGROUPS_Z__SHIFT) & CP_EXEC_CS_3_NGROUPS_Z__MASK;
1273 }
1274
1275 #define REG_A4XX_CP_EXEC_CS_INDIRECT_0 0x00000000
1276
1277
1278 #define REG_A4XX_CP_EXEC_CS_INDIRECT_1 0x00000001
1279 #define A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__MASK 0xffffffff
1280 #define A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__SHIFT 0
1281 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_1_ADDR(uint32_t val)
1282 {
1283 return ((val) << A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__MASK;
1284 }
1285
1286 #define REG_A4XX_CP_EXEC_CS_INDIRECT_2 0x00000002
1287 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__MASK 0x00000ffc
1288 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__SHIFT 2
1289 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX(uint32_t val)
1290 {
1291 return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEX__MASK;
1292 }
1293 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__MASK 0x003ff000
1294 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__SHIFT 12
1295 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY(uint32_t val)
1296 {
1297 return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEY__MASK;
1298 }
1299 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__MASK 0xffc00000
1300 #define A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__SHIFT 22
1301 static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ(uint32_t val)
1302 {
1303 return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__MASK;
1304 }
1305
1306
1307 #define REG_A5XX_CP_EXEC_CS_INDIRECT_1 0x00000001
1308 #define A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK 0xffffffff
1309 #define A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT 0
1310 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO(uint32_t val)
1311 {
1312 return ((val) << A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK;
1313 }
1314
1315 #define REG_A5XX_CP_EXEC_CS_INDIRECT_2 0x00000002
1316 #define A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__MASK 0xffffffff
1317 #define A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT 0
1318 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI(uint32_t val)
1319 {
1320 return ((val) << A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_2_ADDR_HI__MASK;
1321 }
1322
1323 #define REG_A5XX_CP_EXEC_CS_INDIRECT_3 0x00000003
1324 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__MASK 0x00000ffc
1325 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT 2
1326 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(uint32_t val)
1327 {
1328 return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX__MASK;
1329 }
1330 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__MASK 0x003ff000
1331 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT 12
1332 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(uint32_t val)
1333 {
1334 return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY__MASK;
1335 }
1336 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK 0xffc00000
1337 #define A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT 22
1338 static inline uint32_t A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(uint32_t val)
1339 {
1340 return ((val) << A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__SHIFT) & A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ__MASK;
1341 }
1342
1343
1344 #endif /* ADRENO_PM4_XML */