src/gallium/drivers/freedreno/freedreno_clear.c

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29 #include "pipe/p_state.h"
  30 #include "util/u_string.h"
  31 #include "util/u_memory.h"
  32 #include "util/u_inlines.h"
  33 #include "util/u_pack_color.h"
  34
  35 #include "freedreno_clear.h"
  36 #include "freedreno_context.h"
  37 #include "freedreno_resource.h"
  38 #include "freedreno_state.h"
  39 #include "freedreno_program.h"
  40 #include "freedreno_zsa.h"
  41 #include "freedreno_util.h"
  42
  43 static uint32_t
  44 pack_rgba(enum pipe_format format, const float *rgba)
  45 {
  46         union util_color uc;
  47         util_pack_color(rgba, format, &uc);
  48         return uc.ui;
  49 }
  50
  51 static void
  52 fd_clear(struct pipe_context *pctx, unsigned buffers,
  53                 const union pipe_color_union *color, double depth, unsigned stencil)
  54 {
  55         struct fd_context *ctx = fd_context(pctx);
  56         struct fd_ringbuffer *ring = ctx->ring;
  57         struct pipe_framebuffer_state *fb = &ctx->framebuffer;
  58         uint32_t reg, colr = 0;
  59
  60         ctx->cleared |= buffers;
  61         ctx->resolve |= buffers;
  62         ctx->needs_flush = true;
  63
  64         if (buffers & PIPE_CLEAR_COLOR)
  65                 fd_resource(fb->cbufs[0]->texture)->dirty = true;
  66
  67         if (buffers & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL))
  68                 fd_resource(fb->zsbuf->texture)->dirty = true;
  69
  70         DBG("depth=%f, stencil=%u", depth, stencil);
  71
  72         if ((buffers & PIPE_CLEAR_COLOR) && fb->nr_cbufs)
  73                 colr  = pack_rgba(fb->cbufs[0]->format, color->f);
  74
  75         /* emit generic state now: */
  76         fd_state_emit(pctx, ctx->dirty &
  77                         (FD_DIRTY_BLEND | FD_DIRTY_VIEWPORT |
  78                                         FD_DIRTY_FRAMEBUFFER | FD_DIRTY_SCISSOR));
  79
  80         fd_emit_vertex_bufs(ring, 0x9c, (struct fd_vertex_buf[]) {
  81                         { .prsc = ctx->solid_vertexbuf, .size = 48 },
  82                 }, 1);
  83
  84         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
  85         OUT_RING(ring, CP_REG(REG_VGT_INDX_OFFSET));
  86         OUT_RING(ring, 0);
  87
  88         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
  89         OUT_RING(ring, CP_REG(REG_VGT_VERTEX_REUSE_BLOCK_CNTL));
  90         OUT_RING(ring, 0x0000028f);
  91
  92         fd_program_emit(ring, &ctx->solid_prog);
  93
  94         OUT_PKT0(ring, REG_TC_CNTL_STATUS, 1);
  95         OUT_RING(ring, TC_CNTL_STATUS_L2_INVALIDATE);
  96
  97         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
  98         OUT_RING(ring, CP_REG(REG_CLEAR_COLOR));
  99         OUT_RING(ring, colr);
 100
 101         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 102         OUT_RING(ring, CP_REG(REG_A220_RB_LRZ_VSC_CONTROL));
 103         OUT_RING(ring, 0x00000084);
 104
 105         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 106         OUT_RING(ring, CP_REG(REG_RB_COPY_CONTROL));
 107         reg = 0;
 108         if (buffers & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL)) {
 109                 reg |= RB_COPY_CONTROL_DEPTH_CLEAR_ENABLE;
 110                 switch (fd_pipe2depth(fb->zsbuf->format)) {
 111                 case DEPTHX_24_8:
 112                         if (buffers & PIPE_CLEAR_DEPTH)
 113                                 reg |= RB_COPY_CONTROL_CLEAR_MASK(0xe);
 114                         if (buffers & PIPE_CLEAR_STENCIL)
 115                                 reg |= RB_COPY_CONTROL_CLEAR_MASK(0x1);
 116                         break;
 117                 case DEPTHX_16:
 118                         if (buffers & PIPE_CLEAR_DEPTH)
 119                                 reg |= RB_COPY_CONTROL_CLEAR_MASK(0xf);
 120                         break;
 121                 }
 122         }
 123         OUT_RING(ring, reg);
 124
 125         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 126         OUT_RING(ring, CP_REG(REG_RB_DEPTH_CLEAR));
 127         reg = 0;
 128         if (buffers & (PIPE_CLEAR_DEPTH | PIPE_CLEAR_STENCIL)) {
 129                 switch (fd_pipe2depth(fb->zsbuf->format)) {
 130                 case DEPTHX_24_8:
 131                         reg = (((uint32_t)(0xffffff * depth)) << 8) |
 132                                 (stencil & 0xff);
 133                         break;
 134                 case DEPTHX_16:
 135                         reg = (uint32_t)(0xffffffff * depth);
 136                         break;
 137                 }
 138         }
 139         OUT_RING(ring, reg);
 140
 141         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 142         OUT_RING(ring, CP_REG(REG_RB_DEPTHCONTROL));
 143         reg = 0;
 144         if (buffers & PIPE_CLEAR_DEPTH) {
 145                 reg |= RB_DEPTHCONTROL_ZFUNC(GL_ALWAYS) |
 146                                 RB_DEPTHCONTROL_Z_ENABLE |
 147                                 RB_DEPTHCONTROL_Z_WRITE_ENABLE |
 148                                 RB_DEPTHCONTROL_EARLY_Z_ENABLE;
 149         }
 150         if (buffers & PIPE_CLEAR_STENCIL) {
 151                 reg |= RB_DEPTHCONTROL_STENCILFUNC(GL_ALWAYS) |
 152                                 RB_DEPTHCONTROL_STENCIL_ENABLE |
 153                                 RB_DEPTHCONTROL_STENCILZPASS(STENCIL_REPLACE);
 154         }
 155         OUT_RING(ring, reg);
 156
 157         OUT_PKT3(ring, CP_SET_CONSTANT, 3);
 158         OUT_RING(ring, CP_REG(REG_PA_CL_CLIP_CNTL));
 159         OUT_RING(ring, 0x00000000);        /* PA_CL_CLIP_CNTL */
 160         OUT_RING(ring, PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST |  /* PA_SU_SC_MODE_CNTL */
 161                         PA_SU_SC_MODE_CNTL_POLYMODE_FRONT_PTYPE(DRAW_TRIANGLES) |
 162                         PA_SU_SC_MODE_CNTL_POLYMODE_BACK_PTYPE(DRAW_TRIANGLES));
 163
 164         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 165         OUT_RING(ring, CP_REG(REG_PA_SC_AA_MASK));
 166         OUT_RING(ring, 0x0000ffff);
 167
 168         OUT_PKT3(ring, CP_SET_CONSTANT, 3);
 169         OUT_RING(ring, CP_REG(REG_PA_SC_WINDOW_SCISSOR_TL));
 170         OUT_RING(ring, xy2d(0,0));              /* PA_SC_WINDOW_SCISSOR_TL */
 171         OUT_RING(ring, xy2d(fb->width,      /* PA_SC_WINDOW_SCISSOR_BR */
 172                         fb->height));
 173
 174         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 175         OUT_RING(ring, CP_REG(REG_RB_COLOR_MASK));
 176         if (buffers & PIPE_CLEAR_COLOR) {
 177                 OUT_RING(ring, RB_COLOR_MASK_WRITE_RED |
 178                                 RB_COLOR_MASK_WRITE_GREEN |
 179                                 RB_COLOR_MASK_WRITE_BLUE |
 180                                 RB_COLOR_MASK_WRITE_ALPHA);
 181         } else {
 182                 OUT_RING(ring, 0x0);
 183         }
 184
 185         OUT_PKT3(ring, CP_DRAW_INDX, 3);
 186         OUT_RING(ring, 0x00000000);
 187         OUT_RING(ring, DRAW(DI_PT_RECTLIST, DI_SRC_SEL_AUTO_INDEX,
 188                         INDEX_SIZE_IGN, IGNORE_VISIBILITY));
 189         OUT_RING(ring, 3);                                      /* NumIndices */
 190
 191         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 192         OUT_RING(ring, CP_REG(REG_A220_RB_LRZ_VSC_CONTROL));
 193         OUT_RING(ring, 0x00000000);
 194
 195         OUT_PKT3(ring, CP_SET_CONSTANT, 2);
 196         OUT_RING(ring, CP_REG(REG_RB_COPY_CONTROL));
 197         OUT_RING(ring, 0x00000000);
 198
 199         ctx->dirty |= FD_DIRTY_ZSA |
 200                         FD_DIRTY_RASTERIZER |
 201                         FD_DIRTY_SAMPLE_MASK |
 202                         FD_DIRTY_PROG |
 203                         FD_DIRTY_CONSTBUF |
 204                         FD_DIRTY_BLEND;
 205 }
 206
 207 static void
 208 fd_clear_render_target(struct pipe_context *pctx, struct pipe_surface *ps,
 209                 const union pipe_color_union *color,
 210                 unsigned x, unsigned y, unsigned w, unsigned h)
 211 {
 212         DBG("TODO: x=%u, y=%u, w=%u, h=%u", x, y, w, h);
 213 }
 214
 215 static void
 216 fd_clear_depth_stencil(struct pipe_context *pctx, struct pipe_surface *ps,
 217                 unsigned buffers, double depth, unsigned stencil,
 218                 unsigned x, unsigned y, unsigned w, unsigned h)
 219 {
 220         DBG("TODO: buffers=%u, depth=%f, stencil=%u, x=%u, y=%u, w=%u, h=%u",
 221                         buffers, depth, stencil, x, y, w, h);
 222 }
 223
 224 void
 225 fd_clear_init(struct pipe_context *pctx)
 226 {
 227         pctx->clear = fd_clear;
 228         pctx->clear_render_target = fd_clear_render_target;
 229         pctx->clear_depth_stencil = fd_clear_depth_stencil;
 230 }