1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
29 #ifndef FREEDRENO_CONTEXT_H_
30 #define FREEDRENO_CONTEXT_H_
32 #include "pipe/p_context.h"
33 #include "indices/u_primconvert.h"
34 #include "util/u_blitter.h"
35 #include "util/list.h"
36 #include "util/u_slab.h"
37 #include "util/u_string.h"
39 #include "freedreno_batch.h"
40 #include "freedreno_screen.h"
41 #include "freedreno_gmem.h"
42 #include "freedreno_util.h"
44 #define BORDER_COLOR_UPLOAD_SIZE (2 * PIPE_MAX_SAMPLERS * BORDERCOLOR_SIZE)
46 struct fd_vertex_stateobj
;
48 struct fd_texture_stateobj
{
49 struct pipe_sampler_view
*textures
[PIPE_MAX_SAMPLERS
];
50 unsigned num_textures
;
51 unsigned valid_textures
;
52 struct pipe_sampler_state
*samplers
[PIPE_MAX_SAMPLERS
];
53 unsigned num_samplers
;
54 unsigned valid_samplers
;
57 struct fd_program_stateobj
{
60 /* rest only used by fd2.. split out: */
62 /* Indexed by semantic name or TGSI_SEMANTIC_COUNT + semantic index
63 * for TGSI_SEMANTIC_GENERIC. Special vs exports (position and point-
64 * size) are not included in this
66 uint8_t export_linkage
[63];
69 struct fd_constbuf_stateobj
{
70 struct pipe_constant_buffer cb
[PIPE_MAX_CONSTANT_BUFFERS
];
71 uint32_t enabled_mask
;
75 struct fd_vertexbuf_stateobj
{
76 struct pipe_vertex_buffer vb
[PIPE_MAX_ATTRIBS
];
78 uint32_t enabled_mask
;
82 struct fd_vertex_stateobj
{
83 struct pipe_vertex_element pipe
[PIPE_MAX_ATTRIBS
];
84 unsigned num_elements
;
87 struct fd_streamout_stateobj
{
88 struct pipe_stream_output_target
*targets
[PIPE_MAX_SO_BUFFERS
];
90 /* Track offset from vtxcnt for streamout data. This counter
91 * is just incremented by # of vertices on each draw until
92 * reset or new streamout buffer bound.
94 * When we eventually have GS, the CPU won't actually know the
95 * number of vertices per draw, so I think we'll have to do
96 * something more clever.
98 unsigned offsets
[PIPE_MAX_SO_BUFFERS
];
101 /* group together the vertex and vertexbuf state.. for ease of passing
102 * around, and because various internal operations (gmem<->mem, etc)
103 * need their own vertex state:
105 struct fd_vertex_state
{
106 struct fd_vertex_stateobj
*vtx
;
107 struct fd_vertexbuf_stateobj vertexbuf
;
110 /* Bitmask of stages in rendering that a particular query query is
111 * active. Queries will be automatically started/stopped (generating
112 * additional fd_hw_sample_period's) on entrance/exit from stages that
113 * are applicable to the query.
115 * NOTE: set the stage to NULL at end of IB to ensure no query is still
116 * active. Things aren't going to work out the way you want if a query
117 * is active across IB's (or between tile IB and draw IB)
119 enum fd_render_stage
{
120 FD_STAGE_NULL
= 0x01,
121 FD_STAGE_DRAW
= 0x02,
122 FD_STAGE_CLEAR
= 0x04,
123 /* TODO before queries which include MEM2GMEM or GMEM2MEM will
124 * work we will need to call fd_hw_query_prepare() from somewhere
125 * appropriate so that queries in the tiling IB get backed with
126 * memory to write results to.
128 FD_STAGE_MEM2GMEM
= 0x08,
129 FD_STAGE_GMEM2MEM
= 0x10,
130 /* used for driver internal draws (ie. util_blitter_blit()): */
131 FD_STAGE_BLIT
= 0x20,
135 #define MAX_HW_SAMPLE_PROVIDERS 4
136 struct fd_hw_sample_provider
;
140 struct pipe_context base
;
142 struct fd_device
*dev
;
143 struct fd_screen
*screen
;
145 struct blitter_context
*blitter
;
146 struct primconvert_context
*primconvert
;
148 /* slab for pipe_transfer allocations: */
149 struct util_slab_mempool transfer_pool
;
151 /* slabs for fd_hw_sample and fd_hw_sample_period allocations: */
152 struct util_slab_mempool sample_pool
;
153 struct util_slab_mempool sample_period_pool
;
155 /* next sample offset.. incremented for each sample in the batch/
156 * submit, reset to zero on next submit.
158 uint32_t next_sample_offset
;
160 /* sample-providers for hw queries: */
161 const struct fd_hw_sample_provider
*sample_providers
[MAX_HW_SAMPLE_PROVIDERS
];
163 /* cached samples (in case multiple queries need to reference
164 * the same sample snapshot)
166 struct fd_hw_sample
*sample_cache
[MAX_HW_SAMPLE_PROVIDERS
];
168 /* which sample providers were active in the current batch: */
169 uint32_t active_providers
;
171 /* tracking for current stage, to know when to start/stop
172 * any active queries:
174 enum fd_render_stage stage
;
176 /* list of active queries: */
177 struct list_head active_queries
;
179 /* list of queries that are not active, but were active in the
182 struct list_head current_queries
;
184 /* current query result bo and tile stride: */
185 struct fd_bo
*query_bo
;
186 uint32_t query_tile_stride
;
188 /* table with PIPE_PRIM_MAX entries mapping PIPE_PRIM_x to
189 * DI_PT_x value to use for draw initiator. There are some
190 * slight differences between generation:
192 const uint8_t *primtypes
;
193 uint32_t primtype_mask
;
195 /* shaders used by clear, and gmem->mem blits: */
196 struct fd_program_stateobj solid_prog
; // TODO move to screen?
198 /* shaders used by mem->gmem blits: */
199 struct fd_program_stateobj blit_prog
[MAX_RENDER_TARGETS
]; // TODO move to screen?
200 struct fd_program_stateobj blit_z
, blit_zs
;
202 /* do we need to mem2gmem before rendering. We don't, if for example,
203 * there was a glClear() that invalidated the entire previous buffer
204 * contents. Keep track of which buffer(s) are cleared, or needs
205 * restore. Masks of PIPE_CLEAR_*
207 * The 'cleared' bits will be set for buffers which are *entirely*
208 * cleared, and 'partial_cleared' bits will be set if you must
209 * check cleared_scissor.
212 /* align bitmask values w/ PIPE_CLEAR_*.. since that is convenient.. */
213 FD_BUFFER_COLOR
= PIPE_CLEAR_COLOR
,
214 FD_BUFFER_DEPTH
= PIPE_CLEAR_DEPTH
,
215 FD_BUFFER_STENCIL
= PIPE_CLEAR_STENCIL
,
216 FD_BUFFER_ALL
= FD_BUFFER_COLOR
| FD_BUFFER_DEPTH
| FD_BUFFER_STENCIL
,
217 } cleared
, partial_cleared
, restore
, resolve
;
221 /* To decide whether to render to system memory, keep track of the
222 * number of draws, and whether any of them require multisample,
223 * depth_test (or depth write), stencil_test, blending, and
224 * color_logic_Op (since those functions are disabled when by-
228 FD_GMEM_CLEARS_DEPTH_STENCIL
= 0x01,
229 FD_GMEM_DEPTH_ENABLED
= 0x02,
230 FD_GMEM_STENCIL_ENABLED
= 0x04,
232 FD_GMEM_MSAA_ENABLED
= 0x08,
233 FD_GMEM_BLEND_ENABLED
= 0x10,
234 FD_GMEM_LOGICOP_ENABLED
= 0x20,
236 unsigned num_draws
; /* number of draws in current batch */
241 uint64_t prims_emitted
;
242 uint64_t prims_generated
;
244 uint64_t batch_total
, batch_sysmem
, batch_gmem
, batch_restore
;
247 /* TODO get rid of this.. only used in gmem/tiling code paths (and
248 * NULL the rest of the time). Just leaving for now to reduce some
251 struct fd_ringbuffer
*ring
;
253 /* Current batch.. the rule here is that you can deref ctx->batch
254 * in codepaths from pipe_context entrypoints. But not in code-
255 * paths from fd_batch_flush() (basically, the stuff that gets
256 * called from GMEM code), since in those code-paths the batch
257 * you care about is not necessarily the same as ctx->batch.
259 struct fd_batch
*batch
;
261 /* Keep track if WAIT_FOR_IDLE is needed for registers we need
266 /* Do we need to re-emit RB_FRAME_BUFFER_DIMENSION? At least on a3xx
267 * it is not a banked context register, so it needs a WFI to update.
268 * Keep track if it has actually changed, to avoid unneeded WFI.
272 /* Keep track of DRAW initiators that need to be patched up depending
273 * on whether we using binning or not:
275 struct util_dynarray draw_patches
;
277 struct pipe_scissor_state scissor
;
279 /* we don't have a disable/enable bit for scissor, so instead we keep
280 * a disabled-scissor state which matches the entire bound framebuffer
281 * and use that when scissor is not enabled.
283 struct pipe_scissor_state disabled_scissor
;
285 /* Track the maximal bounds of the scissor of all the draws within a
286 * batch. Used at the tile rendering step (fd_gmem_render_tiles(),
287 * mem2gmem/gmem2mem) to avoid needlessly moving data in/out of gmem.
289 struct pipe_scissor_state max_scissor
;
291 /* Track the cleared scissor for color/depth/stencil, so we know
292 * which, if any, tiles need to be restored (mem2gmem). Only valid
293 * if the corresponding bit in ctx->cleared is set.
296 struct pipe_scissor_state color
, depth
, stencil
;
299 /* Current gmem/tiling configuration.. gets updated on render_tiles()
300 * if out of date with current maximal-scissor/cpp:
302 struct fd_gmem_stateobj gmem
;
303 struct fd_vsc_pipe pipe
[8];
304 struct fd_tile tile
[512];
306 /* which state objects need to be re-emit'd: */
308 FD_DIRTY_BLEND
= (1 << 0),
309 FD_DIRTY_RASTERIZER
= (1 << 1),
310 FD_DIRTY_ZSA
= (1 << 2),
311 FD_DIRTY_FRAGTEX
= (1 << 3),
312 FD_DIRTY_VERTTEX
= (1 << 4),
313 FD_DIRTY_TEXSTATE
= (1 << 5),
315 FD_SHADER_DIRTY_VP
= (1 << 6),
316 FD_SHADER_DIRTY_FP
= (1 << 7),
317 /* skip geom/tcs/tes/compute */
318 FD_DIRTY_PROG
= FD_SHADER_DIRTY_FP
| FD_SHADER_DIRTY_VP
,
320 FD_DIRTY_BLEND_COLOR
= (1 << 12),
321 FD_DIRTY_STENCIL_REF
= (1 << 13),
322 FD_DIRTY_SAMPLE_MASK
= (1 << 14),
323 FD_DIRTY_FRAMEBUFFER
= (1 << 15),
324 FD_DIRTY_STIPPLE
= (1 << 16),
325 FD_DIRTY_VIEWPORT
= (1 << 17),
326 FD_DIRTY_CONSTBUF
= (1 << 18),
327 FD_DIRTY_VTXSTATE
= (1 << 19),
328 FD_DIRTY_VTXBUF
= (1 << 20),
329 FD_DIRTY_INDEXBUF
= (1 << 21),
330 FD_DIRTY_SCISSOR
= (1 << 22),
331 FD_DIRTY_STREAMOUT
= (1 << 23),
332 FD_DIRTY_UCP
= (1 << 24),
333 FD_DIRTY_BLEND_DUAL
= (1 << 25),
336 struct pipe_blend_state
*blend
;
337 struct pipe_rasterizer_state
*rasterizer
;
338 struct pipe_depth_stencil_alpha_state
*zsa
;
340 struct fd_texture_stateobj verttex
, fragtex
;
342 struct fd_program_stateobj prog
;
344 struct fd_vertex_state vtx
;
346 struct pipe_blend_color blend_color
;
347 struct pipe_stencil_ref stencil_ref
;
348 unsigned sample_mask
;
349 struct pipe_framebuffer_state framebuffer
;
350 struct pipe_poly_stipple stipple
;
351 struct pipe_viewport_state viewport
;
352 struct fd_constbuf_stateobj constbuf
[PIPE_SHADER_TYPES
];
353 struct pipe_index_buffer indexbuf
;
354 struct fd_streamout_stateobj streamout
;
355 struct pipe_clip_state ucp
;
357 struct pipe_query
*cond_query
;
358 bool cond_cond
; /* inverted rendering condition */
361 struct pipe_debug_callback debug
;
363 /* GMEM/tile handling fxns: */
364 void (*emit_tile_init
)(struct fd_context
*ctx
);
365 void (*emit_tile_prep
)(struct fd_context
*ctx
, struct fd_tile
*tile
);
366 void (*emit_tile_mem2gmem
)(struct fd_context
*ctx
, struct fd_tile
*tile
);
367 void (*emit_tile_renderprep
)(struct fd_context
*ctx
, struct fd_tile
*tile
);
368 void (*emit_tile_gmem2mem
)(struct fd_context
*ctx
, struct fd_tile
*tile
);
370 /* optional, for GMEM bypass: */
371 void (*emit_sysmem_prep
)(struct fd_context
*ctx
);
374 bool (*draw_vbo
)(struct fd_context
*ctx
, const struct pipe_draw_info
*info
);
375 void (*clear
)(struct fd_context
*ctx
, unsigned buffers
,
376 const union pipe_color_union
*color
, double depth
, unsigned stencil
);
378 /* constant emit: (note currently not used/needed for a2xx) */
379 void (*emit_const
)(struct fd_ringbuffer
*ring
, enum shader_t type
,
380 uint32_t regid
, uint32_t offset
, uint32_t sizedwords
,
381 const uint32_t *dwords
, struct pipe_resource
*prsc
);
382 /* emit bo addresses as constant: */
383 void (*emit_const_bo
)(struct fd_ringbuffer
*ring
, enum shader_t type
, boolean write
,
384 uint32_t regid
, uint32_t num
, struct pipe_resource
**prscs
, uint32_t *offsets
);
386 /* indirect-branch emit: */
387 void (*emit_ib
)(struct fd_ringbuffer
*ring
, struct fd_ringbuffer
*target
);
390 static inline struct fd_context
*
391 fd_context(struct pipe_context
*pctx
)
393 return (struct fd_context
*)pctx
;
396 static inline struct pipe_scissor_state
*
397 fd_context_get_scissor(struct fd_context
*ctx
)
399 if (ctx
->rasterizer
&& ctx
->rasterizer
->scissor
)
400 return &ctx
->scissor
;
401 return &ctx
->disabled_scissor
;
405 fd_supported_prim(struct fd_context
*ctx
, unsigned prim
)
407 return (1 << prim
) & ctx
->primtype_mask
;
411 fd_reset_wfi(struct fd_context
*ctx
)
413 ctx
->needs_wfi
= true;
416 /* emit a WAIT_FOR_IDLE only if needed, ie. if there has not already
417 * been one since last draw:
420 fd_wfi(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
)
422 if (ctx
->needs_wfi
) {
424 ctx
->needs_wfi
= false;
428 /* emit a CP_EVENT_WRITE:
431 fd_event_write(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
432 enum vgt_event_type evt
)
434 OUT_PKT3(ring
, CP_EVENT_WRITE
, 1);
439 struct pipe_context
* fd_context_init(struct fd_context
*ctx
,
440 struct pipe_screen
*pscreen
, const uint8_t *primtypes
,
443 void fd_context_render(struct pipe_context
*pctx
);
445 void fd_context_destroy(struct pipe_context
*pctx
);
447 #endif /* FREEDRENO_CONTEXT_H_ */