src/gallium/drivers/freedreno/freedreno_context.h

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29 #ifndef FREEDRENO_CONTEXT_H_
  30 #define FREEDRENO_CONTEXT_H_
  31
  32 #include "pipe/p_context.h"
  33 #include "indices/u_primconvert.h"
  34 #include "util/u_blitter.h"
  35 #include "util/list.h"
  36 #include "util/u_slab.h"
  37 #include "util/u_string.h"
  38
  39 #include "freedreno_screen.h"
  40 #include "freedreno_gmem.h"
  41 #include "freedreno_util.h"
  42
  43 #define BORDER_COLOR_UPLOAD_SIZE (2 * PIPE_MAX_SAMPLERS * BORDERCOLOR_SIZE)
  44
  45 struct fd_vertex_stateobj;
  46
  47 struct fd_texture_stateobj {
  48         struct pipe_sampler_view *textures[PIPE_MAX_SAMPLERS];
  49         unsigned num_textures;
  50         struct pipe_sampler_state *samplers[PIPE_MAX_SAMPLERS];
  51         unsigned num_samplers;
  52         unsigned dirty_samplers;
  53 };
  54
  55 struct fd_program_stateobj {
  56         void *vp, *fp;
  57         enum {
  58                 FD_SHADER_DIRTY_VP = (1 << 0),
  59                 FD_SHADER_DIRTY_FP = (1 << 1),
  60         } dirty;
  61         uint8_t num_exports;
  62         /* Indexed by semantic name or TGSI_SEMANTIC_COUNT + semantic index
  63          * for TGSI_SEMANTIC_GENERIC.  Special vs exports (position and point-
  64          * size) are not included in this
  65          */
  66         uint8_t export_linkage[63];
  67 };
  68
  69 struct fd_constbuf_stateobj {
  70         struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS];
  71         uint32_t enabled_mask;
  72         uint32_t dirty_mask;
  73 };
  74
  75 struct fd_vertexbuf_stateobj {
  76         struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS];
  77         unsigned count;
  78         uint32_t enabled_mask;
  79         uint32_t dirty_mask;
  80 };
  81
  82 struct fd_vertex_stateobj {
  83         struct pipe_vertex_element pipe[PIPE_MAX_ATTRIBS];
  84         unsigned num_elements;
  85 };
  86
  87 struct fd_streamout_stateobj {
  88         struct pipe_stream_output_target *targets[PIPE_MAX_SO_BUFFERS];
  89         unsigned num_targets;
  90         /* Track offset from vtxcnt for streamout data.  This counter
  91          * is just incremented by # of vertices on each draw until
  92          * reset or new streamout buffer bound.
  93          *
  94          * When we eventually have GS, the CPU won't actually know the
  95          * number of vertices per draw, so I think we'll have to do
  96          * something more clever.
  97          */
  98         unsigned offsets[PIPE_MAX_SO_BUFFERS];
  99 };
 100
 101 /* group together the vertex and vertexbuf state.. for ease of passing
 102  * around, and because various internal operations (gmem<->mem, etc)
 103  * need their own vertex state:
 104  */
 105 struct fd_vertex_state {
 106         struct fd_vertex_stateobj *vtx;
 107         struct fd_vertexbuf_stateobj vertexbuf;
 108 };
 109
 110 /* Bitmask of stages in rendering that a particular query query is
 111  * active.  Queries will be automatically started/stopped (generating
 112  * additional fd_hw_sample_period's) on entrance/exit from stages that
 113  * are applicable to the query.
 114  *
 115  * NOTE: set the stage to NULL at end of IB to ensure no query is still
 116  * active.  Things aren't going to work out the way you want if a query
 117  * is active across IB's (or between tile IB and draw IB)
 118  */
 119 enum fd_render_stage {
 120         FD_STAGE_NULL     = 0x00,
 121         FD_STAGE_DRAW     = 0x01,
 122         FD_STAGE_CLEAR    = 0x02,
 123         /* TODO before queries which include MEM2GMEM or GMEM2MEM will
 124          * work we will need to call fd_hw_query_prepare() from somewhere
 125          * appropriate so that queries in the tiling IB get backed with
 126          * memory to write results to.
 127          */
 128         FD_STAGE_MEM2GMEM = 0x04,
 129         FD_STAGE_GMEM2MEM = 0x08,
 130         /* used for driver internal draws (ie. util_blitter_blit()): */
 131         FD_STAGE_BLIT     = 0x10,
 132 };
 133
 134 #define MAX_HW_SAMPLE_PROVIDERS 4
 135 struct fd_hw_sample_provider;
 136 struct fd_hw_sample;
 137
 138 struct fd_context {
 139         struct pipe_context base;
 140
 141         struct fd_device *dev;
 142         struct fd_screen *screen;
 143
 144         struct blitter_context *blitter;
 145         struct primconvert_context *primconvert;
 146
 147         /* slab for pipe_transfer allocations: */
 148         struct util_slab_mempool transfer_pool;
 149
 150         /* slabs for fd_hw_sample and fd_hw_sample_period allocations: */
 151         struct util_slab_mempool sample_pool;
 152         struct util_slab_mempool sample_period_pool;
 153
 154         /* next sample offset.. incremented for each sample in the batch/
 155          * submit, reset to zero on next submit.
 156          */
 157         uint32_t next_sample_offset;
 158
 159         /* sample-providers for hw queries: */
 160         const struct fd_hw_sample_provider *sample_providers[MAX_HW_SAMPLE_PROVIDERS];
 161
 162         /* cached samples (in case multiple queries need to reference
 163          * the same sample snapshot)
 164          */
 165         struct fd_hw_sample *sample_cache[MAX_HW_SAMPLE_PROVIDERS];
 166
 167         /* which sample providers were active in the current batch: */
 168         uint32_t active_providers;
 169
 170         /* tracking for current stage, to know when to start/stop
 171          * any active queries:
 172          */
 173         enum fd_render_stage stage;
 174
 175         /* list of active queries: */
 176         struct list_head active_queries;
 177
 178         /* list of queries that are not active, but were active in the
 179          * current submit:
 180          */
 181         struct list_head current_queries;
 182
 183         /* current query result bo and tile stride: */
 184         struct fd_bo *query_bo;
 185         uint32_t query_tile_stride;
 186
 187         /* list of resources used by currently-unsubmitted renders */
 188         struct list_head used_resources;
 189
 190         /* table with PIPE_PRIM_MAX entries mapping PIPE_PRIM_x to
 191          * DI_PT_x value to use for draw initiator.  There are some
 192          * slight differences between generation:
 193          */
 194         const uint8_t *primtypes;
 195         uint32_t primtype_mask;
 196
 197         /* shaders used by clear, and gmem->mem blits: */
 198         struct fd_program_stateobj solid_prog; // TODO move to screen?
 199
 200         /* shaders used by mem->gmem blits: */
 201         struct fd_program_stateobj blit_prog[MAX_RENDER_TARGETS]; // TODO move to screen?
 202         struct fd_program_stateobj blit_z, blit_zs;
 203
 204         /* do we need to mem2gmem before rendering.  We don't, if for example,
 205          * there was a glClear() that invalidated the entire previous buffer
 206          * contents.  Keep track of which buffer(s) are cleared, or needs
 207          * restore.  Masks of PIPE_CLEAR_*
 208          *
 209          * The 'cleared' bits will be set for buffers which are *entirely*
 210          * cleared, and 'partial_cleared' bits will be set if you must
 211          * check cleared_scissor.
 212          */
 213         enum {
 214                 /* align bitmask values w/ PIPE_CLEAR_*.. since that is convenient.. */
 215                 FD_BUFFER_COLOR   = PIPE_CLEAR_COLOR,
 216                 FD_BUFFER_DEPTH   = PIPE_CLEAR_DEPTH,
 217                 FD_BUFFER_STENCIL = PIPE_CLEAR_STENCIL,
 218                 FD_BUFFER_ALL     = FD_BUFFER_COLOR | FD_BUFFER_DEPTH | FD_BUFFER_STENCIL,
 219         } cleared, partial_cleared, restore, resolve;
 220
 221         bool needs_flush;
 222
 223         /* To decide whether to render to system memory, keep track of the
 224          * number of draws, and whether any of them require multisample,
 225          * depth_test (or depth write), stencil_test, blending, and
 226          * color_logic_Op (since those functions are disabled when by-
 227          * passing GMEM.
 228          */
 229         enum {
 230                 FD_GMEM_CLEARS_DEPTH_STENCIL = 0x01,
 231                 FD_GMEM_DEPTH_ENABLED        = 0x02,
 232                 FD_GMEM_STENCIL_ENABLED      = 0x04,
 233
 234                 FD_GMEM_MSAA_ENABLED         = 0x08,
 235                 FD_GMEM_BLEND_ENABLED        = 0x10,
 236                 FD_GMEM_LOGICOP_ENABLED      = 0x20,
 237         } gmem_reason;
 238         unsigned num_draws;   /* number of draws in current batch */
 239
 240         /* Stats/counters:
 241          */
 242         struct {
 243                 uint64_t prims_emitted;
 244                 uint64_t prims_generated;
 245                 uint64_t draw_calls;
 246                 uint64_t batch_total, batch_sysmem, batch_gmem, batch_restore;
 247         } stats;
 248
 249         /* we can't really sanely deal with wraparound point in ringbuffer
 250          * and because of the way tiling works we can't really flush at
 251          * arbitrary points (without a big performance hit).  When we get
 252          * too close to the end of the current ringbuffer, cycle to the next
 253          * one (and wait for pending rendering from next rb to complete).
 254          * We want the # of ringbuffers to be high enough that we don't
 255          * normally have to wait before resetting to the start of the next
 256          * rb.
 257          */
 258         struct fd_ringbuffer *rings[8];
 259         unsigned rings_idx;
 260
 261         /* NOTE: currently using a single ringbuffer for both draw and
 262          * tiling commands, we need to make sure we need to leave enough
 263          * room at the end to append the tiling commands when we flush.
 264          * 0x7000 dwords should be a couple times more than we ever need
 265          * so should be a nice conservative threshold.
 266          */
 267 #define FD_TILING_COMMANDS_DWORDS 0x7000
 268
 269         /* normal draw/clear cmds: */
 270         struct fd_ringbuffer *ring;
 271         struct fd_ringmarker *draw_start, *draw_end;
 272
 273         /* binning pass draw/clear cmds: */
 274         struct fd_ringbuffer *binning_ring;
 275         struct fd_ringmarker *binning_start, *binning_end;
 276
 277         /* Keep track if WAIT_FOR_IDLE is needed for registers we need
 278          * to update via RMW:
 279          */
 280         bool needs_wfi;
 281
 282         /* Do we need to re-emit RB_FRAME_BUFFER_DIMENSION?  At least on a3xx
 283          * it is not a banked context register, so it needs a WFI to update.
 284          * Keep track if it has actually changed, to avoid unneeded WFI.
 285          * */
 286         bool needs_rb_fbd;
 287
 288         /* Keep track of DRAW initiators that need to be patched up depending
 289          * on whether we using binning or not:
 290          */
 291         struct util_dynarray draw_patches;
 292
 293         struct pipe_scissor_state scissor;
 294
 295         /* we don't have a disable/enable bit for scissor, so instead we keep
 296          * a disabled-scissor state which matches the entire bound framebuffer
 297          * and use that when scissor is not enabled.
 298          */
 299         struct pipe_scissor_state disabled_scissor;
 300
 301         /* Track the maximal bounds of the scissor of all the draws within a
 302          * batch.  Used at the tile rendering step (fd_gmem_render_tiles(),
 303          * mem2gmem/gmem2mem) to avoid needlessly moving data in/out of gmem.
 304          */
 305         struct pipe_scissor_state max_scissor;
 306
 307         /* Track the cleared scissor for color/depth/stencil, so we know
 308          * which, if any, tiles need to be restored (mem2gmem).  Only valid
 309          * if the corresponding bit in ctx->cleared is set.
 310          */
 311         struct {
 312                 struct pipe_scissor_state color, depth, stencil;
 313         } cleared_scissor;
 314
 315         /* Current gmem/tiling configuration.. gets updated on render_tiles()
 316          * if out of date with current maximal-scissor/cpp:
 317          */
 318         struct fd_gmem_stateobj gmem;
 319         struct fd_vsc_pipe      pipe[8];
 320         struct fd_tile          tile[256];
 321
 322         /* which state objects need to be re-emit'd: */
 323         enum {
 324                 FD_DIRTY_BLEND       = (1 <<  0),
 325                 FD_DIRTY_RASTERIZER  = (1 <<  1),
 326                 FD_DIRTY_ZSA         = (1 <<  2),
 327                 FD_DIRTY_FRAGTEX     = (1 <<  3),
 328                 FD_DIRTY_VERTTEX     = (1 <<  4),
 329                 FD_DIRTY_TEXSTATE    = (1 <<  5),
 330                 FD_DIRTY_PROG        = (1 <<  6),
 331                 FD_DIRTY_BLEND_COLOR = (1 <<  7),
 332                 FD_DIRTY_STENCIL_REF = (1 <<  8),
 333                 FD_DIRTY_SAMPLE_MASK = (1 <<  9),
 334                 FD_DIRTY_FRAMEBUFFER = (1 << 10),
 335                 FD_DIRTY_STIPPLE     = (1 << 11),
 336                 FD_DIRTY_VIEWPORT    = (1 << 12),
 337                 FD_DIRTY_CONSTBUF    = (1 << 13),
 338                 FD_DIRTY_VTXSTATE    = (1 << 14),
 339                 FD_DIRTY_VTXBUF      = (1 << 15),
 340                 FD_DIRTY_INDEXBUF    = (1 << 16),
 341                 FD_DIRTY_SCISSOR     = (1 << 17),
 342                 FD_DIRTY_STREAMOUT   = (1 << 18),
 343                 FD_DIRTY_UCP         = (1 << 19),
 344                 FD_DIRTY_BLEND_DUAL  = (1 << 20),
 345         } dirty;
 346
 347         struct pipe_blend_state *blend;
 348         struct pipe_rasterizer_state *rasterizer;
 349         struct pipe_depth_stencil_alpha_state *zsa;
 350
 351         struct fd_texture_stateobj verttex, fragtex;
 352
 353         struct fd_program_stateobj prog;
 354
 355         struct fd_vertex_state vtx;
 356
 357         struct pipe_blend_color blend_color;
 358         struct pipe_stencil_ref stencil_ref;
 359         unsigned sample_mask;
 360         struct pipe_framebuffer_state framebuffer;
 361         struct pipe_poly_stipple stipple;
 362         struct pipe_viewport_state viewport;
 363         struct fd_constbuf_stateobj constbuf[PIPE_SHADER_TYPES];
 364         struct pipe_index_buffer indexbuf;
 365         struct fd_streamout_stateobj streamout;
 366         struct pipe_clip_state ucp;
 367
 368         struct pipe_query *cond_query;
 369         bool cond_cond; /* inverted rendering condition */
 370         uint cond_mode;
 371
 372         /* GMEM/tile handling fxns: */
 373         void (*emit_tile_init)(struct fd_context *ctx);
 374         void (*emit_tile_prep)(struct fd_context *ctx, struct fd_tile *tile);
 375         void (*emit_tile_mem2gmem)(struct fd_context *ctx, struct fd_tile *tile);
 376         void (*emit_tile_renderprep)(struct fd_context *ctx, struct fd_tile *tile);
 377         void (*emit_tile_gmem2mem)(struct fd_context *ctx, struct fd_tile *tile);
 378
 379         /* optional, for GMEM bypass: */
 380         void (*emit_sysmem_prep)(struct fd_context *ctx);
 381
 382         /* draw: */
 383         void (*draw_vbo)(struct fd_context *ctx, const struct pipe_draw_info *info);
 384         void (*clear)(struct fd_context *ctx, unsigned buffers,
 385                         const union pipe_color_union *color, double depth, unsigned stencil);
 386
 387         /* constant emit:  (note currently not used/needed for a2xx) */
 388         void (*emit_const)(struct fd_ringbuffer *ring, enum shader_t type,
 389                         uint32_t regid, uint32_t offset, uint32_t sizedwords,
 390                         const uint32_t *dwords, struct pipe_resource *prsc);
 391         void (*emit_const_bo)(struct fd_ringbuffer *ring, enum shader_t type, boolean write,
 392                         uint32_t regid, uint32_t num, struct fd_bo **bos, uint32_t *offsets);
 393
 394         /* indirect-branch emit: */
 395         void (*emit_ib)(struct fd_ringbuffer *ring, struct fd_ringmarker *start,
 396                         struct fd_ringmarker *end);
 397 };
 398
 399 static inline struct fd_context *
 400 fd_context(struct pipe_context *pctx)
 401 {
 402         return (struct fd_context *)pctx;
 403 }
 404
 405 static inline struct pipe_scissor_state *
 406 fd_context_get_scissor(struct fd_context *ctx)
 407 {
 408         if (ctx->rasterizer && ctx->rasterizer->scissor)
 409                 return &ctx->scissor;
 410         return &ctx->disabled_scissor;
 411 }
 412
 413 static inline bool
 414 fd_supported_prim(struct fd_context *ctx, unsigned prim)
 415 {
 416         return (1 << prim) & ctx->primtype_mask;
 417 }
 418
 419 static inline void
 420 fd_reset_wfi(struct fd_context *ctx)
 421 {
 422         ctx->needs_wfi = true;
 423 }
 424
 425 /* emit a WAIT_FOR_IDLE only if needed, ie. if there has not already
 426  * been one since last draw:
 427  */
 428 static inline void
 429 fd_wfi(struct fd_context *ctx, struct fd_ringbuffer *ring)
 430 {
 431         if (ctx->needs_wfi) {
 432                 OUT_WFI(ring);
 433                 ctx->needs_wfi = false;
 434         }
 435 }
 436
 437 /* emit a CP_EVENT_WRITE:
 438  */
 439 static inline void
 440 fd_event_write(struct fd_context *ctx, struct fd_ringbuffer *ring,
 441                 enum vgt_event_type evt)
 442 {
 443         OUT_PKT3(ring, CP_EVENT_WRITE, 1);
 444         OUT_RING(ring, evt);
 445         fd_reset_wfi(ctx);
 446 }
 447
 448 struct pipe_context * fd_context_init(struct fd_context *ctx,
 449                 struct pipe_screen *pscreen, const uint8_t *primtypes,
 450                 void *priv);
 451
 452 void fd_context_render(struct pipe_context *pctx);
 453
 454 void fd_context_destroy(struct pipe_context *pctx);
 455
 456 #endif /* FREEDRENO_CONTEXT_H_ */