1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
29 #ifndef FREEDRENO_CONTEXT_H_
30 #define FREEDRENO_CONTEXT_H_
32 #include "pipe/p_context.h"
33 #include "indices/u_primconvert.h"
34 #include "util/u_blitter.h"
35 #include "util/u_double_list.h"
36 #include "util/u_slab.h"
37 #include "util/u_string.h"
39 #include "freedreno_screen.h"
40 #include "freedreno_gmem.h"
41 #include "freedreno_util.h"
43 struct fd_vertex_stateobj
;
45 struct fd_texture_stateobj
{
46 struct pipe_sampler_view
*textures
[PIPE_MAX_SAMPLERS
];
47 unsigned num_textures
;
48 struct pipe_sampler_state
*samplers
[PIPE_MAX_SAMPLERS
];
49 unsigned num_samplers
;
50 unsigned dirty_samplers
;
53 struct fd_program_stateobj
{
56 FD_SHADER_DIRTY_VP
= (1 << 0),
57 FD_SHADER_DIRTY_FP
= (1 << 1),
60 /* Indexed by semantic name or TGSI_SEMANTIC_COUNT + semantic index
61 * for TGSI_SEMANTIC_GENERIC. Special vs exports (position and point-
62 * size) are not included in this
64 uint8_t export_linkage
[63];
67 struct fd_constbuf_stateobj
{
68 struct pipe_constant_buffer cb
[PIPE_MAX_CONSTANT_BUFFERS
];
69 uint32_t enabled_mask
;
73 struct fd_vertexbuf_stateobj
{
74 struct pipe_vertex_buffer vb
[PIPE_MAX_ATTRIBS
];
76 uint32_t enabled_mask
;
80 struct fd_vertex_stateobj
{
81 struct pipe_vertex_element pipe
[PIPE_MAX_ATTRIBS
];
82 unsigned num_elements
;
85 /* Bitmask of stages in rendering that a particular query query is
86 * active. Queries will be automatically started/stopped (generating
87 * additional fd_hw_sample_period's) on entrance/exit from stages that
88 * are applicable to the query.
90 * NOTE: set the stage to NULL at end of IB to ensure no query is still
91 * active. Things aren't going to work out the way you want if a query
92 * is active across IB's (or between tile IB and draw IB)
94 enum fd_render_stage
{
97 FD_STAGE_CLEAR
= 0x02,
98 /* TODO before queries which include MEM2GMEM or GMEM2MEM will
99 * work we will need to call fd_hw_query_prepare() from somewhere
100 * appropriate so that queries in the tiling IB get backed with
101 * memory to write results to.
103 FD_STAGE_MEM2GMEM
= 0x04,
104 FD_STAGE_GMEM2MEM
= 0x08,
105 /* used for driver internal draws (ie. util_blitter_blit()): */
106 FD_STAGE_BLIT
= 0x10,
109 #define MAX_HW_SAMPLE_PROVIDERS 4
110 struct fd_hw_sample_provider
;
114 struct pipe_context base
;
116 struct fd_device
*dev
;
117 struct fd_screen
*screen
;
119 struct blitter_context
*blitter
;
120 struct primconvert_context
*primconvert
;
122 /* slab for pipe_transfer allocations: */
123 struct util_slab_mempool transfer_pool
;
125 /* slabs for fd_hw_sample and fd_hw_sample_period allocations: */
126 struct util_slab_mempool sample_pool
;
127 struct util_slab_mempool sample_period_pool
;
129 /* next sample offset.. incremented for each sample in the batch/
130 * submit, reset to zero on next submit.
132 uint32_t next_sample_offset
;
134 /* sample-providers for hw queries: */
135 const struct fd_hw_sample_provider
*sample_providers
[MAX_HW_SAMPLE_PROVIDERS
];
137 /* cached samples (in case multiple queries need to reference
138 * the same sample snapshot)
140 struct fd_hw_sample
*sample_cache
[MAX_HW_SAMPLE_PROVIDERS
];
142 /* tracking for current stage, to know when to start/stop
143 * any active queries:
145 enum fd_render_stage stage
;
147 /* list of active queries: */
148 struct list_head active_queries
;
150 /* list of queries that are not active, but were active in the
153 struct list_head current_queries
;
155 /* current query result bo and tile stride: */
156 struct fd_bo
*query_bo
;
157 uint32_t query_tile_stride
;
159 /* table with PIPE_PRIM_MAX entries mapping PIPE_PRIM_x to
160 * DI_PT_x value to use for draw initiator. There are some
161 * slight differences between generation:
163 const uint8_t *primtypes
;
164 uint32_t primtype_mask
;
166 /* shaders used by clear, and gmem->mem blits: */
167 struct fd_program_stateobj solid_prog
; // TODO move to screen?
169 /* shaders used by mem->gmem blits: */
170 struct fd_program_stateobj blit_prog
; // TODO move to screen?
172 /* do we need to mem2gmem before rendering. We don't, if for example,
173 * there was a glClear() that invalidated the entire previous buffer
174 * contents. Keep track of which buffer(s) are cleared, or needs
175 * restore. Masks of PIPE_CLEAR_*
178 /* align bitmask values w/ PIPE_CLEAR_*.. since that is convenient.. */
179 FD_BUFFER_COLOR
= PIPE_CLEAR_COLOR0
,
180 FD_BUFFER_DEPTH
= PIPE_CLEAR_DEPTH
,
181 FD_BUFFER_STENCIL
= PIPE_CLEAR_STENCIL
,
182 FD_BUFFER_ALL
= FD_BUFFER_COLOR
| FD_BUFFER_DEPTH
| FD_BUFFER_STENCIL
,
183 } cleared
, restore
, resolve
;
187 /* To decide whether to render to system memory, keep track of the
188 * number of draws, and whether any of them require multisample,
189 * depth_test (or depth write), stencil_test, blending, and
190 * color_logic_Op (since those functions are disabled when by-
194 FD_GMEM_CLEARS_DEPTH_STENCIL
= 0x01,
195 FD_GMEM_DEPTH_ENABLED
= 0x02,
196 FD_GMEM_STENCIL_ENABLED
= 0x04,
198 FD_GMEM_MSAA_ENABLED
= 0x08,
199 FD_GMEM_BLEND_ENABLED
= 0x10,
200 FD_GMEM_LOGICOP_ENABLED
= 0x20,
202 unsigned num_draws
; /* number of draws in current batch */
207 uint64_t prims_emitted
;
209 uint64_t batch_total
, batch_sysmem
, batch_gmem
, batch_restore
;
212 /* we can't really sanely deal with wraparound point in ringbuffer
213 * and because of the way tiling works we can't really flush at
214 * arbitrary points (without a big performance hit). When we get
215 * too close to the end of the current ringbuffer, cycle to the next
216 * one (and wait for pending rendering from next rb to complete).
217 * We want the # of ringbuffers to be high enough that we don't
218 * normally have to wait before resetting to the start of the next
221 struct fd_ringbuffer
*rings
[8];
224 /* NOTE: currently using a single ringbuffer for both draw and
225 * tiling commands, we need to make sure we need to leave enough
226 * room at the end to append the tiling commands when we flush.
227 * 0x7000 dwords should be a couple times more than we ever need
228 * so should be a nice conservative threshold.
230 #define FD_TILING_COMMANDS_DWORDS 0x7000
232 /* normal draw/clear cmds: */
233 struct fd_ringbuffer
*ring
;
234 struct fd_ringmarker
*draw_start
, *draw_end
;
236 /* binning pass draw/clear cmds: */
237 struct fd_ringbuffer
*binning_ring
;
238 struct fd_ringmarker
*binning_start
, *binning_end
;
240 /* Keep track if WAIT_FOR_IDLE is needed for registers we need
245 /* Do we need to re-emit RB_FRAME_BUFFER_DIMENSION? At least on a3xx
246 * it is not a banked context register, so it needs a WFI to update.
247 * Keep track if it has actually changed, to avoid unneeded WFI.
251 /* Keep track of DRAW initiators that need to be patched up depending
252 * on whether we using binning or not:
254 struct util_dynarray draw_patches
;
256 struct pipe_scissor_state scissor
;
258 /* we don't have a disable/enable bit for scissor, so instead we keep
259 * a disabled-scissor state which matches the entire bound framebuffer
260 * and use that when scissor is not enabled.
262 struct pipe_scissor_state disabled_scissor
;
264 /* Track the maximal bounds of the scissor of all the draws within a
265 * batch. Used at the tile rendering step (fd_gmem_render_tiles(),
266 * mem2gmem/gmem2mem) to avoid needlessly moving data in/out of gmem.
268 struct pipe_scissor_state max_scissor
;
270 /* Current gmem/tiling configuration.. gets updated on render_tiles()
271 * if out of date with current maximal-scissor/cpp:
273 struct fd_gmem_stateobj gmem
;
274 struct fd_vsc_pipe pipe
[8];
275 struct fd_tile tile
[64];
277 /* which state objects need to be re-emit'd: */
279 FD_DIRTY_BLEND
= (1 << 0),
280 FD_DIRTY_RASTERIZER
= (1 << 1),
281 FD_DIRTY_ZSA
= (1 << 2),
282 FD_DIRTY_FRAGTEX
= (1 << 3),
283 FD_DIRTY_VERTTEX
= (1 << 4),
284 FD_DIRTY_TEXSTATE
= (1 << 5),
285 FD_DIRTY_PROG
= (1 << 6),
286 FD_DIRTY_BLEND_COLOR
= (1 << 7),
287 FD_DIRTY_STENCIL_REF
= (1 << 8),
288 FD_DIRTY_SAMPLE_MASK
= (1 << 9),
289 FD_DIRTY_FRAMEBUFFER
= (1 << 10),
290 FD_DIRTY_STIPPLE
= (1 << 11),
291 FD_DIRTY_VIEWPORT
= (1 << 12),
292 FD_DIRTY_CONSTBUF
= (1 << 13),
293 FD_DIRTY_VTXSTATE
= (1 << 14),
294 FD_DIRTY_VTXBUF
= (1 << 15),
295 FD_DIRTY_INDEXBUF
= (1 << 16),
296 FD_DIRTY_SCISSOR
= (1 << 17),
299 struct pipe_blend_state
*blend
;
300 struct pipe_rasterizer_state
*rasterizer
;
301 struct pipe_depth_stencil_alpha_state
*zsa
;
303 struct fd_texture_stateobj verttex
, fragtex
;
305 struct fd_program_stateobj prog
;
307 struct fd_vertex_stateobj
*vtx
;
309 struct pipe_blend_color blend_color
;
310 struct pipe_stencil_ref stencil_ref
;
311 unsigned sample_mask
;
312 struct pipe_framebuffer_state framebuffer
;
313 struct pipe_poly_stipple stipple
;
314 struct pipe_viewport_state viewport
;
315 struct fd_constbuf_stateobj constbuf
[PIPE_SHADER_TYPES
];
316 struct fd_vertexbuf_stateobj vertexbuf
;
317 struct pipe_index_buffer indexbuf
;
319 /* GMEM/tile handling fxns: */
320 void (*emit_tile_init
)(struct fd_context
*ctx
);
321 void (*emit_tile_prep
)(struct fd_context
*ctx
, struct fd_tile
*tile
);
322 void (*emit_tile_mem2gmem
)(struct fd_context
*ctx
, struct fd_tile
*tile
);
323 void (*emit_tile_renderprep
)(struct fd_context
*ctx
, struct fd_tile
*tile
);
324 void (*emit_tile_gmem2mem
)(struct fd_context
*ctx
, struct fd_tile
*tile
);
326 /* optional, for GMEM bypass: */
327 void (*emit_sysmem_prep
)(struct fd_context
*ctx
);
330 void (*draw
)(struct fd_context
*pctx
, const struct pipe_draw_info
*info
);
331 void (*clear
)(struct fd_context
*ctx
, unsigned buffers
,
332 const union pipe_color_union
*color
, double depth
, unsigned stencil
);
335 static INLINE
struct fd_context
*
336 fd_context(struct pipe_context
*pctx
)
338 return (struct fd_context
*)pctx
;
341 static INLINE
struct pipe_scissor_state
*
342 fd_context_get_scissor(struct fd_context
*ctx
)
344 if (ctx
->rasterizer
&& ctx
->rasterizer
->scissor
)
345 return &ctx
->scissor
;
346 return &ctx
->disabled_scissor
;
350 fd_supported_prim(struct fd_context
*ctx
, unsigned prim
)
352 return (1 << prim
) & ctx
->primtype_mask
;
356 fd_reset_wfi(struct fd_context
*ctx
)
358 ctx
->needs_wfi
= true;
361 /* emit a WAIT_FOR_IDLE only if needed, ie. if there has not already
362 * been one since last draw:
365 fd_wfi(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
)
367 if (ctx
->needs_wfi
) {
369 ctx
->needs_wfi
= false;
373 /* emit a CP_EVENT_WRITE:
376 fd_event_write(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
377 enum vgt_event_type evt
)
379 OUT_PKT3(ring
, CP_EVENT_WRITE
, 1);
384 struct pipe_context
* fd_context_init(struct fd_context
*ctx
,
385 struct pipe_screen
*pscreen
, const uint8_t *primtypes
,
388 void fd_context_render(struct pipe_context
*pctx
);
390 void fd_context_destroy(struct pipe_context
*pctx
);
392 #endif /* FREEDRENO_CONTEXT_H_ */