src/gallium/drivers/freedreno/freedreno_context.h

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29 #ifndef FREEDRENO_CONTEXT_H_
  30 #define FREEDRENO_CONTEXT_H_
  31
  32 #include "pipe/p_context.h"
  33 #include "indices/u_primconvert.h"
  34 #include "util/u_blitter.h"
  35 #include "util/list.h"
  36 #include "util/u_slab.h"
  37 #include "util/u_string.h"
  38
  39 #include "freedreno_screen.h"
  40 #include "freedreno_gmem.h"
  41 #include "freedreno_util.h"
  42
  43 #define BORDER_COLOR_UPLOAD_SIZE (2 * PIPE_MAX_SAMPLERS * BORDERCOLOR_SIZE)
  44
  45 struct fd_vertex_stateobj;
  46
  47 struct fd_texture_stateobj {
  48         struct pipe_sampler_view *textures[PIPE_MAX_SAMPLERS];
  49         unsigned num_textures;
  50         unsigned valid_textures;
  51         struct pipe_sampler_state *samplers[PIPE_MAX_SAMPLERS];
  52         unsigned num_samplers;
  53         unsigned valid_samplers;
  54 };
  55
  56 struct fd_program_stateobj {
  57         void *vp, *fp;
  58
  59         /* rest only used by fd2.. split out: */
  60         uint8_t num_exports;
  61         /* Indexed by semantic name or TGSI_SEMANTIC_COUNT + semantic index
  62          * for TGSI_SEMANTIC_GENERIC.  Special vs exports (position and point-
  63          * size) are not included in this
  64          */
  65         uint8_t export_linkage[63];
  66 };
  67
  68 struct fd_constbuf_stateobj {
  69         struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS];
  70         uint32_t enabled_mask;
  71         uint32_t dirty_mask;
  72 };
  73
  74 struct fd_vertexbuf_stateobj {
  75         struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS];
  76         unsigned count;
  77         uint32_t enabled_mask;
  78         uint32_t dirty_mask;
  79 };
  80
  81 struct fd_vertex_stateobj {
  82         struct pipe_vertex_element pipe[PIPE_MAX_ATTRIBS];
  83         unsigned num_elements;
  84 };
  85
  86 struct fd_streamout_stateobj {
  87         struct pipe_stream_output_target *targets[PIPE_MAX_SO_BUFFERS];
  88         unsigned num_targets;
  89         /* Track offset from vtxcnt for streamout data.  This counter
  90          * is just incremented by # of vertices on each draw until
  91          * reset or new streamout buffer bound.
  92          *
  93          * When we eventually have GS, the CPU won't actually know the
  94          * number of vertices per draw, so I think we'll have to do
  95          * something more clever.
  96          */
  97         unsigned offsets[PIPE_MAX_SO_BUFFERS];
  98 };
  99
 100 /* group together the vertex and vertexbuf state.. for ease of passing
 101  * around, and because various internal operations (gmem<->mem, etc)
 102  * need their own vertex state:
 103  */
 104 struct fd_vertex_state {
 105         struct fd_vertex_stateobj *vtx;
 106         struct fd_vertexbuf_stateobj vertexbuf;
 107 };
 108
 109 /* Bitmask of stages in rendering that a particular query query is
 110  * active.  Queries will be automatically started/stopped (generating
 111  * additional fd_hw_sample_period's) on entrance/exit from stages that
 112  * are applicable to the query.
 113  *
 114  * NOTE: set the stage to NULL at end of IB to ensure no query is still
 115  * active.  Things aren't going to work out the way you want if a query
 116  * is active across IB's (or between tile IB and draw IB)
 117  */
 118 enum fd_render_stage {
 119         FD_STAGE_NULL     = 0x00,
 120         FD_STAGE_DRAW     = 0x01,
 121         FD_STAGE_CLEAR    = 0x02,
 122         /* TODO before queries which include MEM2GMEM or GMEM2MEM will
 123          * work we will need to call fd_hw_query_prepare() from somewhere
 124          * appropriate so that queries in the tiling IB get backed with
 125          * memory to write results to.
 126          */
 127         FD_STAGE_MEM2GMEM = 0x04,
 128         FD_STAGE_GMEM2MEM = 0x08,
 129         /* used for driver internal draws (ie. util_blitter_blit()): */
 130         FD_STAGE_BLIT     = 0x10,
 131 };
 132
 133 #define MAX_HW_SAMPLE_PROVIDERS 4
 134 struct fd_hw_sample_provider;
 135 struct fd_hw_sample;
 136
 137 struct fd_context {
 138         struct pipe_context base;
 139
 140         struct fd_device *dev;
 141         struct fd_screen *screen;
 142
 143         struct blitter_context *blitter;
 144         struct primconvert_context *primconvert;
 145
 146         /* slab for pipe_transfer allocations: */
 147         struct util_slab_mempool transfer_pool;
 148
 149         /* slabs for fd_hw_sample and fd_hw_sample_period allocations: */
 150         struct util_slab_mempool sample_pool;
 151         struct util_slab_mempool sample_period_pool;
 152
 153         /* next sample offset.. incremented for each sample in the batch/
 154          * submit, reset to zero on next submit.
 155          */
 156         uint32_t next_sample_offset;
 157
 158         /* sample-providers for hw queries: */
 159         const struct fd_hw_sample_provider *sample_providers[MAX_HW_SAMPLE_PROVIDERS];
 160
 161         /* cached samples (in case multiple queries need to reference
 162          * the same sample snapshot)
 163          */
 164         struct fd_hw_sample *sample_cache[MAX_HW_SAMPLE_PROVIDERS];
 165
 166         /* which sample providers were active in the current batch: */
 167         uint32_t active_providers;
 168
 169         /* tracking for current stage, to know when to start/stop
 170          * any active queries:
 171          */
 172         enum fd_render_stage stage;
 173
 174         /* list of active queries: */
 175         struct list_head active_queries;
 176
 177         /* list of queries that are not active, but were active in the
 178          * current submit:
 179          */
 180         struct list_head current_queries;
 181
 182         /* current query result bo and tile stride: */
 183         struct fd_bo *query_bo;
 184         uint32_t query_tile_stride;
 185
 186         /* list of resources used by currently-unsubmitted renders */
 187         struct list_head used_resources;
 188
 189         /* table with PIPE_PRIM_MAX entries mapping PIPE_PRIM_x to
 190          * DI_PT_x value to use for draw initiator.  There are some
 191          * slight differences between generation:
 192          */
 193         const uint8_t *primtypes;
 194         uint32_t primtype_mask;
 195
 196         /* shaders used by clear, and gmem->mem blits: */
 197         struct fd_program_stateobj solid_prog; // TODO move to screen?
 198
 199         /* shaders used by mem->gmem blits: */
 200         struct fd_program_stateobj blit_prog[MAX_RENDER_TARGETS]; // TODO move to screen?
 201         struct fd_program_stateobj blit_z, blit_zs;
 202
 203         /* do we need to mem2gmem before rendering.  We don't, if for example,
 204          * there was a glClear() that invalidated the entire previous buffer
 205          * contents.  Keep track of which buffer(s) are cleared, or needs
 206          * restore.  Masks of PIPE_CLEAR_*
 207          *
 208          * The 'cleared' bits will be set for buffers which are *entirely*
 209          * cleared, and 'partial_cleared' bits will be set if you must
 210          * check cleared_scissor.
 211          */
 212         enum {
 213                 /* align bitmask values w/ PIPE_CLEAR_*.. since that is convenient.. */
 214                 FD_BUFFER_COLOR   = PIPE_CLEAR_COLOR,
 215                 FD_BUFFER_DEPTH   = PIPE_CLEAR_DEPTH,
 216                 FD_BUFFER_STENCIL = PIPE_CLEAR_STENCIL,
 217                 FD_BUFFER_ALL     = FD_BUFFER_COLOR | FD_BUFFER_DEPTH | FD_BUFFER_STENCIL,
 218         } cleared, partial_cleared, restore, resolve;
 219
 220         bool needs_flush;
 221
 222         /* To decide whether to render to system memory, keep track of the
 223          * number of draws, and whether any of them require multisample,
 224          * depth_test (or depth write), stencil_test, blending, and
 225          * color_logic_Op (since those functions are disabled when by-
 226          * passing GMEM.
 227          */
 228         enum {
 229                 FD_GMEM_CLEARS_DEPTH_STENCIL = 0x01,
 230                 FD_GMEM_DEPTH_ENABLED        = 0x02,
 231                 FD_GMEM_STENCIL_ENABLED      = 0x04,
 232
 233                 FD_GMEM_MSAA_ENABLED         = 0x08,
 234                 FD_GMEM_BLEND_ENABLED        = 0x10,
 235                 FD_GMEM_LOGICOP_ENABLED      = 0x20,
 236         } gmem_reason;
 237         unsigned num_draws;   /* number of draws in current batch */
 238
 239         /* Stats/counters:
 240          */
 241         struct {
 242                 uint64_t prims_emitted;
 243                 uint64_t prims_generated;
 244                 uint64_t draw_calls;
 245                 uint64_t batch_total, batch_sysmem, batch_gmem, batch_restore;
 246         } stats;
 247
 248         /* we can't really sanely deal with wraparound point in ringbuffer
 249          * and because of the way tiling works we can't really flush at
 250          * arbitrary points (without a big performance hit).  When we get
 251          * too close to the end of the current ringbuffer, cycle to the next
 252          * one (and wait for pending rendering from next rb to complete).
 253          * We want the # of ringbuffers to be high enough that we don't
 254          * normally have to wait before resetting to the start of the next
 255          * rb.
 256          */
 257         struct fd_ringbuffer *rings[8];
 258         unsigned rings_idx;
 259
 260         /* NOTE: currently using a single ringbuffer for both draw and
 261          * tiling commands, we need to make sure we need to leave enough
 262          * room at the end to append the tiling commands when we flush.
 263          * 0x7000 dwords should be a couple times more than we ever need
 264          * so should be a nice conservative threshold.
 265          */
 266 #define FD_TILING_COMMANDS_DWORDS 0x7000
 267
 268         /* normal draw/clear cmds: */
 269         struct fd_ringbuffer *ring;
 270         struct fd_ringmarker *draw_start, *draw_end;
 271
 272         /* binning pass draw/clear cmds: */
 273         struct fd_ringbuffer *binning_ring;
 274         struct fd_ringmarker *binning_start, *binning_end;
 275
 276         /* Keep track if WAIT_FOR_IDLE is needed for registers we need
 277          * to update via RMW:
 278          */
 279         bool needs_wfi;
 280
 281         /* Do we need to re-emit RB_FRAME_BUFFER_DIMENSION?  At least on a3xx
 282          * it is not a banked context register, so it needs a WFI to update.
 283          * Keep track if it has actually changed, to avoid unneeded WFI.
 284          * */
 285         bool needs_rb_fbd;
 286
 287         /* Keep track of DRAW initiators that need to be patched up depending
 288          * on whether we using binning or not:
 289          */
 290         struct util_dynarray draw_patches;
 291
 292         struct pipe_scissor_state scissor;
 293
 294         /* we don't have a disable/enable bit for scissor, so instead we keep
 295          * a disabled-scissor state which matches the entire bound framebuffer
 296          * and use that when scissor is not enabled.
 297          */
 298         struct pipe_scissor_state disabled_scissor;
 299
 300         /* Track the maximal bounds of the scissor of all the draws within a
 301          * batch.  Used at the tile rendering step (fd_gmem_render_tiles(),
 302          * mem2gmem/gmem2mem) to avoid needlessly moving data in/out of gmem.
 303          */
 304         struct pipe_scissor_state max_scissor;
 305
 306         /* Track the cleared scissor for color/depth/stencil, so we know
 307          * which, if any, tiles need to be restored (mem2gmem).  Only valid
 308          * if the corresponding bit in ctx->cleared is set.
 309          */
 310         struct {
 311                 struct pipe_scissor_state color, depth, stencil;
 312         } cleared_scissor;
 313
 314         /* Current gmem/tiling configuration.. gets updated on render_tiles()
 315          * if out of date with current maximal-scissor/cpp:
 316          */
 317         struct fd_gmem_stateobj gmem;
 318         struct fd_vsc_pipe      pipe[8];
 319         struct fd_tile          tile[256];
 320
 321         /* which state objects need to be re-emit'd: */
 322         enum {
 323                 FD_DIRTY_BLEND       = (1 <<  0),
 324                 FD_DIRTY_RASTERIZER  = (1 <<  1),
 325                 FD_DIRTY_ZSA         = (1 <<  2),
 326                 FD_DIRTY_FRAGTEX     = (1 <<  3),
 327                 FD_DIRTY_VERTTEX     = (1 <<  4),
 328                 FD_DIRTY_TEXSTATE    = (1 <<  5),
 329
 330                 FD_SHADER_DIRTY_VP   = (1 <<  6),
 331                 FD_SHADER_DIRTY_FP   = (1 <<  7),
 332                 /* skip geom/tcs/tes/compute */
 333                 FD_DIRTY_PROG        = FD_SHADER_DIRTY_FP | FD_SHADER_DIRTY_VP,
 334
 335                 FD_DIRTY_BLEND_COLOR = (1 << 12),
 336                 FD_DIRTY_STENCIL_REF = (1 << 13),
 337                 FD_DIRTY_SAMPLE_MASK = (1 << 14),
 338                 FD_DIRTY_FRAMEBUFFER = (1 << 15),
 339                 FD_DIRTY_STIPPLE     = (1 << 16),
 340                 FD_DIRTY_VIEWPORT    = (1 << 17),
 341                 FD_DIRTY_CONSTBUF    = (1 << 18),
 342                 FD_DIRTY_VTXSTATE    = (1 << 19),
 343                 FD_DIRTY_VTXBUF      = (1 << 20),
 344                 FD_DIRTY_INDEXBUF    = (1 << 21),
 345                 FD_DIRTY_SCISSOR     = (1 << 22),
 346                 FD_DIRTY_STREAMOUT   = (1 << 23),
 347                 FD_DIRTY_UCP         = (1 << 24),
 348                 FD_DIRTY_BLEND_DUAL  = (1 << 25),
 349         } dirty;
 350
 351         struct pipe_blend_state *blend;
 352         struct pipe_rasterizer_state *rasterizer;
 353         struct pipe_depth_stencil_alpha_state *zsa;
 354
 355         struct fd_texture_stateobj verttex, fragtex;
 356
 357         struct fd_program_stateobj prog;
 358
 359         struct fd_vertex_state vtx;
 360
 361         struct pipe_blend_color blend_color;
 362         struct pipe_stencil_ref stencil_ref;
 363         unsigned sample_mask;
 364         struct pipe_framebuffer_state framebuffer;
 365         struct pipe_poly_stipple stipple;
 366         struct pipe_viewport_state viewport;
 367         struct fd_constbuf_stateobj constbuf[PIPE_SHADER_TYPES];
 368         struct pipe_index_buffer indexbuf;
 369         struct fd_streamout_stateobj streamout;
 370         struct pipe_clip_state ucp;
 371
 372         struct pipe_query *cond_query;
 373         bool cond_cond; /* inverted rendering condition */
 374         uint cond_mode;
 375
 376         struct pipe_debug_callback debug;
 377
 378         /* GMEM/tile handling fxns: */
 379         void (*emit_tile_init)(struct fd_context *ctx);
 380         void (*emit_tile_prep)(struct fd_context *ctx, struct fd_tile *tile);
 381         void (*emit_tile_mem2gmem)(struct fd_context *ctx, struct fd_tile *tile);
 382         void (*emit_tile_renderprep)(struct fd_context *ctx, struct fd_tile *tile);
 383         void (*emit_tile_gmem2mem)(struct fd_context *ctx, struct fd_tile *tile);
 384
 385         /* optional, for GMEM bypass: */
 386         void (*emit_sysmem_prep)(struct fd_context *ctx);
 387
 388         /* draw: */
 389         bool (*draw_vbo)(struct fd_context *ctx, const struct pipe_draw_info *info);
 390         void (*clear)(struct fd_context *ctx, unsigned buffers,
 391                         const union pipe_color_union *color, double depth, unsigned stencil);
 392
 393         /* constant emit:  (note currently not used/needed for a2xx) */
 394         void (*emit_const)(struct fd_ringbuffer *ring, enum shader_t type,
 395                         uint32_t regid, uint32_t offset, uint32_t sizedwords,
 396                         const uint32_t *dwords, struct pipe_resource *prsc);
 397         /* emit bo addresses as constant: */
 398         void (*emit_const_bo)(struct fd_ringbuffer *ring, enum shader_t type, boolean write,
 399                         uint32_t regid, uint32_t num, struct pipe_resource **prscs, uint32_t *offsets);
 400
 401         /* indirect-branch emit: */
 402         void (*emit_ib)(struct fd_ringbuffer *ring, struct fd_ringmarker *start,
 403                         struct fd_ringmarker *end);
 404 };
 405
 406 static inline struct fd_context *
 407 fd_context(struct pipe_context *pctx)
 408 {
 409         return (struct fd_context *)pctx;
 410 }
 411
 412 static inline struct pipe_scissor_state *
 413 fd_context_get_scissor(struct fd_context *ctx)
 414 {
 415         if (ctx->rasterizer && ctx->rasterizer->scissor)
 416                 return &ctx->scissor;
 417         return &ctx->disabled_scissor;
 418 }
 419
 420 static inline bool
 421 fd_supported_prim(struct fd_context *ctx, unsigned prim)
 422 {
 423         return (1 << prim) & ctx->primtype_mask;
 424 }
 425
 426 static inline void
 427 fd_reset_wfi(struct fd_context *ctx)
 428 {
 429         ctx->needs_wfi = true;
 430 }
 431
 432 /* emit a WAIT_FOR_IDLE only if needed, ie. if there has not already
 433  * been one since last draw:
 434  */
 435 static inline void
 436 fd_wfi(struct fd_context *ctx, struct fd_ringbuffer *ring)
 437 {
 438         if (ctx->needs_wfi) {
 439                 OUT_WFI(ring);
 440                 ctx->needs_wfi = false;
 441         }
 442 }
 443
 444 /* emit a CP_EVENT_WRITE:
 445  */
 446 static inline void
 447 fd_event_write(struct fd_context *ctx, struct fd_ringbuffer *ring,
 448                 enum vgt_event_type evt)
 449 {
 450         OUT_PKT3(ring, CP_EVENT_WRITE, 1);
 451         OUT_RING(ring, evt);
 452         fd_reset_wfi(ctx);
 453 }
 454
 455 struct pipe_context * fd_context_init(struct fd_context *ctx,
 456                 struct pipe_screen *pscreen, const uint8_t *primtypes,
 457                 void *priv);
 458
 459 void fd_context_render(struct pipe_context *pctx);
 460
 461 void fd_context_destroy(struct pipe_context *pctx);
 462
 463 #endif /* FREEDRENO_CONTEXT_H_ */