src/gallium/drivers/freedreno/freedreno_context.h

   1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
   2
   3 /*
   4  * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  23  * SOFTWARE.
  24  *
  25  * Authors:
  26  *    Rob Clark <robclark@freedesktop.org>
  27  */
  28
  29 #ifndef FREEDRENO_CONTEXT_H_
  30 #define FREEDRENO_CONTEXT_H_
  31
  32 #include "pipe/p_context.h"
  33 #include "indices/u_primconvert.h"
  34 #include "util/u_blitter.h"
  35 #include "util/list.h"
  36 #include "util/u_slab.h"
  37 #include "util/u_string.h"
  38
  39 #include "freedreno_batch.h"
  40 #include "freedreno_screen.h"
  41 #include "freedreno_gmem.h"
  42 #include "freedreno_util.h"
  43
  44 #define BORDER_COLOR_UPLOAD_SIZE (2 * PIPE_MAX_SAMPLERS * BORDERCOLOR_SIZE)
  45
  46 struct fd_vertex_stateobj;
  47
  48 struct fd_texture_stateobj {
  49         struct pipe_sampler_view *textures[PIPE_MAX_SAMPLERS];
  50         unsigned num_textures;
  51         unsigned valid_textures;
  52         struct pipe_sampler_state *samplers[PIPE_MAX_SAMPLERS];
  53         unsigned num_samplers;
  54         unsigned valid_samplers;
  55 };
  56
  57 struct fd_program_stateobj {
  58         void *vp, *fp;
  59
  60         /* rest only used by fd2.. split out: */
  61         uint8_t num_exports;
  62         /* Indexed by semantic name or TGSI_SEMANTIC_COUNT + semantic index
  63          * for TGSI_SEMANTIC_GENERIC.  Special vs exports (position and point-
  64          * size) are not included in this
  65          */
  66         uint8_t export_linkage[63];
  67 };
  68
  69 struct fd_constbuf_stateobj {
  70         struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS];
  71         uint32_t enabled_mask;
  72         uint32_t dirty_mask;
  73 };
  74
  75 struct fd_vertexbuf_stateobj {
  76         struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS];
  77         unsigned count;
  78         uint32_t enabled_mask;
  79         uint32_t dirty_mask;
  80 };
  81
  82 struct fd_vertex_stateobj {
  83         struct pipe_vertex_element pipe[PIPE_MAX_ATTRIBS];
  84         unsigned num_elements;
  85 };
  86
  87 struct fd_streamout_stateobj {
  88         struct pipe_stream_output_target *targets[PIPE_MAX_SO_BUFFERS];
  89         unsigned num_targets;
  90         /* Track offset from vtxcnt for streamout data.  This counter
  91          * is just incremented by # of vertices on each draw until
  92          * reset or new streamout buffer bound.
  93          *
  94          * When we eventually have GS, the CPU won't actually know the
  95          * number of vertices per draw, so I think we'll have to do
  96          * something more clever.
  97          */
  98         unsigned offsets[PIPE_MAX_SO_BUFFERS];
  99 };
 100
 101 /* group together the vertex and vertexbuf state.. for ease of passing
 102  * around, and because various internal operations (gmem<->mem, etc)
 103  * need their own vertex state:
 104  */
 105 struct fd_vertex_state {
 106         struct fd_vertex_stateobj *vtx;
 107         struct fd_vertexbuf_stateobj vertexbuf;
 108 };
 109
 110 /* Bitmask of stages in rendering that a particular query query is
 111  * active.  Queries will be automatically started/stopped (generating
 112  * additional fd_hw_sample_period's) on entrance/exit from stages that
 113  * are applicable to the query.
 114  *
 115  * NOTE: set the stage to NULL at end of IB to ensure no query is still
 116  * active.  Things aren't going to work out the way you want if a query
 117  * is active across IB's (or between tile IB and draw IB)
 118  */
 119 enum fd_render_stage {
 120         FD_STAGE_NULL     = 0x01,
 121         FD_STAGE_DRAW     = 0x02,
 122         FD_STAGE_CLEAR    = 0x04,
 123         /* TODO before queries which include MEM2GMEM or GMEM2MEM will
 124          * work we will need to call fd_hw_query_prepare() from somewhere
 125          * appropriate so that queries in the tiling IB get backed with
 126          * memory to write results to.
 127          */
 128         FD_STAGE_MEM2GMEM = 0x08,
 129         FD_STAGE_GMEM2MEM = 0x10,
 130         /* used for driver internal draws (ie. util_blitter_blit()): */
 131         FD_STAGE_BLIT     = 0x20,
 132         FD_STAGE_ALL      = 0xff,
 133 };
 134
 135 #define MAX_HW_SAMPLE_PROVIDERS 4
 136 struct fd_hw_sample_provider;
 137 struct fd_hw_sample;
 138
 139 struct fd_context {
 140         struct pipe_context base;
 141
 142         struct fd_device *dev;
 143         struct fd_screen *screen;
 144
 145         struct blitter_context *blitter;
 146         struct primconvert_context *primconvert;
 147
 148         /* slab for pipe_transfer allocations: */
 149         struct util_slab_mempool transfer_pool;
 150
 151         /* slabs for fd_hw_sample and fd_hw_sample_period allocations: */
 152         struct util_slab_mempool sample_pool;
 153         struct util_slab_mempool sample_period_pool;
 154
 155         /* next sample offset.. incremented for each sample in the batch/
 156          * submit, reset to zero on next submit.
 157          */
 158         uint32_t next_sample_offset;
 159
 160         /* sample-providers for hw queries: */
 161         const struct fd_hw_sample_provider *sample_providers[MAX_HW_SAMPLE_PROVIDERS];
 162
 163         /* cached samples (in case multiple queries need to reference
 164          * the same sample snapshot)
 165          */
 166         struct fd_hw_sample *sample_cache[MAX_HW_SAMPLE_PROVIDERS];
 167
 168         /* which sample providers were active in the current batch: */
 169         uint32_t active_providers;
 170
 171         /* tracking for current stage, to know when to start/stop
 172          * any active queries:
 173          */
 174         enum fd_render_stage stage;
 175
 176         /* list of active queries: */
 177         struct list_head active_queries;
 178
 179         /* list of queries that are not active, but were active in the
 180          * current submit:
 181          */
 182         struct list_head current_queries;
 183
 184         /* current query result bo and tile stride: */
 185         struct fd_bo *query_bo;
 186         uint32_t query_tile_stride;
 187
 188         /* table with PIPE_PRIM_MAX entries mapping PIPE_PRIM_x to
 189          * DI_PT_x value to use for draw initiator.  There are some
 190          * slight differences between generation:
 191          */
 192         const uint8_t *primtypes;
 193         uint32_t primtype_mask;
 194
 195         /* shaders used by clear, and gmem->mem blits: */
 196         struct fd_program_stateobj solid_prog; // TODO move to screen?
 197
 198         /* shaders used by mem->gmem blits: */
 199         struct fd_program_stateobj blit_prog[MAX_RENDER_TARGETS]; // TODO move to screen?
 200         struct fd_program_stateobj blit_z, blit_zs;
 201
 202         /* Stats/counters:
 203          */
 204         struct {
 205                 uint64_t prims_emitted;
 206                 uint64_t prims_generated;
 207                 uint64_t draw_calls;
 208                 uint64_t batch_total, batch_sysmem, batch_gmem, batch_restore;
 209         } stats;
 210
 211         /* Current batch.. the rule here is that you can deref ctx->batch
 212          * in codepaths from pipe_context entrypoints.  But not in code-
 213          * paths from fd_batch_flush() (basically, the stuff that gets
 214          * called from GMEM code), since in those code-paths the batch
 215          * you care about is not necessarily the same as ctx->batch.
 216          */
 217         struct fd_batch *batch;
 218
 219         /* Keep track if WAIT_FOR_IDLE is needed for registers we need
 220          * to update via RMW:
 221          */
 222         bool needs_wfi;
 223
 224         /* Do we need to re-emit RB_FRAME_BUFFER_DIMENSION?  At least on a3xx
 225          * it is not a banked context register, so it needs a WFI to update.
 226          * Keep track if it has actually changed, to avoid unneeded WFI.
 227          * */
 228         bool needs_rb_fbd;
 229
 230         struct pipe_scissor_state scissor;
 231
 232         /* we don't have a disable/enable bit for scissor, so instead we keep
 233          * a disabled-scissor state which matches the entire bound framebuffer
 234          * and use that when scissor is not enabled.
 235          */
 236         struct pipe_scissor_state disabled_scissor;
 237
 238         /* Current gmem/tiling configuration.. gets updated on render_tiles()
 239          * if out of date with current maximal-scissor/cpp:
 240          *
 241          * (NOTE: this is kind of related to the batch, but moving it there
 242          * means we'd always have to recalc tiles ever batch)
 243          */
 244         struct fd_gmem_stateobj gmem;
 245         struct fd_vsc_pipe      pipe[8];
 246         struct fd_tile          tile[512];
 247
 248         /* which state objects need to be re-emit'd: */
 249         enum {
 250                 FD_DIRTY_BLEND       = (1 <<  0),
 251                 FD_DIRTY_RASTERIZER  = (1 <<  1),
 252                 FD_DIRTY_ZSA         = (1 <<  2),
 253                 FD_DIRTY_FRAGTEX     = (1 <<  3),
 254                 FD_DIRTY_VERTTEX     = (1 <<  4),
 255                 FD_DIRTY_TEXSTATE    = (1 <<  5),
 256
 257                 FD_SHADER_DIRTY_VP   = (1 <<  6),
 258                 FD_SHADER_DIRTY_FP   = (1 <<  7),
 259                 /* skip geom/tcs/tes/compute */
 260                 FD_DIRTY_PROG        = FD_SHADER_DIRTY_FP | FD_SHADER_DIRTY_VP,
 261
 262                 FD_DIRTY_BLEND_COLOR = (1 << 12),
 263                 FD_DIRTY_STENCIL_REF = (1 << 13),
 264                 FD_DIRTY_SAMPLE_MASK = (1 << 14),
 265                 FD_DIRTY_FRAMEBUFFER = (1 << 15),
 266                 FD_DIRTY_STIPPLE     = (1 << 16),
 267                 FD_DIRTY_VIEWPORT    = (1 << 17),
 268                 FD_DIRTY_CONSTBUF    = (1 << 18),
 269                 FD_DIRTY_VTXSTATE    = (1 << 19),
 270                 FD_DIRTY_VTXBUF      = (1 << 20),
 271                 FD_DIRTY_INDEXBUF    = (1 << 21),
 272                 FD_DIRTY_SCISSOR     = (1 << 22),
 273                 FD_DIRTY_STREAMOUT   = (1 << 23),
 274                 FD_DIRTY_UCP         = (1 << 24),
 275                 FD_DIRTY_BLEND_DUAL  = (1 << 25),
 276         } dirty;
 277
 278         struct pipe_blend_state *blend;
 279         struct pipe_rasterizer_state *rasterizer;
 280         struct pipe_depth_stencil_alpha_state *zsa;
 281
 282         struct fd_texture_stateobj verttex, fragtex;
 283
 284         struct fd_program_stateobj prog;
 285
 286         struct fd_vertex_state vtx;
 287
 288         struct pipe_blend_color blend_color;
 289         struct pipe_stencil_ref stencil_ref;
 290         unsigned sample_mask;
 291         struct pipe_poly_stipple stipple;
 292         struct pipe_viewport_state viewport;
 293         struct fd_constbuf_stateobj constbuf[PIPE_SHADER_TYPES];
 294         struct pipe_index_buffer indexbuf;
 295         struct fd_streamout_stateobj streamout;
 296         struct pipe_clip_state ucp;
 297
 298         struct pipe_query *cond_query;
 299         bool cond_cond; /* inverted rendering condition */
 300         uint cond_mode;
 301
 302         struct pipe_debug_callback debug;
 303
 304         /* GMEM/tile handling fxns: */
 305         void (*emit_tile_init)(struct fd_batch *batch);
 306         void (*emit_tile_prep)(struct fd_batch *batch, struct fd_tile *tile);
 307         void (*emit_tile_mem2gmem)(struct fd_batch *batch, struct fd_tile *tile);
 308         void (*emit_tile_renderprep)(struct fd_batch *batch, struct fd_tile *tile);
 309         void (*emit_tile_gmem2mem)(struct fd_batch *batch, struct fd_tile *tile);
 310
 311         /* optional, for GMEM bypass: */
 312         void (*emit_sysmem_prep)(struct fd_batch *batch);
 313
 314         /* draw: */
 315         bool (*draw_vbo)(struct fd_context *ctx, const struct pipe_draw_info *info);
 316         void (*clear)(struct fd_context *ctx, unsigned buffers,
 317                         const union pipe_color_union *color, double depth, unsigned stencil);
 318
 319         /* constant emit:  (note currently not used/needed for a2xx) */
 320         void (*emit_const)(struct fd_ringbuffer *ring, enum shader_t type,
 321                         uint32_t regid, uint32_t offset, uint32_t sizedwords,
 322                         const uint32_t *dwords, struct pipe_resource *prsc);
 323         /* emit bo addresses as constant: */
 324         void (*emit_const_bo)(struct fd_ringbuffer *ring, enum shader_t type, boolean write,
 325                         uint32_t regid, uint32_t num, struct pipe_resource **prscs, uint32_t *offsets);
 326
 327         /* indirect-branch emit: */
 328         void (*emit_ib)(struct fd_ringbuffer *ring, struct fd_ringbuffer *target);
 329 };
 330
 331 static inline struct fd_context *
 332 fd_context(struct pipe_context *pctx)
 333 {
 334         return (struct fd_context *)pctx;
 335 }
 336
 337 static inline struct pipe_scissor_state *
 338 fd_context_get_scissor(struct fd_context *ctx)
 339 {
 340         if (ctx->rasterizer && ctx->rasterizer->scissor)
 341                 return &ctx->scissor;
 342         return &ctx->disabled_scissor;
 343 }
 344
 345 static inline bool
 346 fd_supported_prim(struct fd_context *ctx, unsigned prim)
 347 {
 348         return (1 << prim) & ctx->primtype_mask;
 349 }
 350
 351 static inline void
 352 fd_reset_wfi(struct fd_context *ctx)
 353 {
 354         ctx->needs_wfi = true;
 355 }
 356
 357 /* emit a WAIT_FOR_IDLE only if needed, ie. if there has not already
 358  * been one since last draw:
 359  */
 360 static inline void
 361 fd_wfi(struct fd_context *ctx, struct fd_ringbuffer *ring)
 362 {
 363         if (ctx->needs_wfi) {
 364                 OUT_WFI(ring);
 365                 ctx->needs_wfi = false;
 366         }
 367 }
 368
 369 /* emit a CP_EVENT_WRITE:
 370  */
 371 static inline void
 372 fd_event_write(struct fd_context *ctx, struct fd_ringbuffer *ring,
 373                 enum vgt_event_type evt)
 374 {
 375         OUT_PKT3(ring, CP_EVENT_WRITE, 1);
 376         OUT_RING(ring, evt);
 377         fd_reset_wfi(ctx);
 378 }
 379
 380 struct pipe_context * fd_context_init(struct fd_context *ctx,
 381                 struct pipe_screen *pscreen, const uint8_t *primtypes,
 382                 void *priv);
 383
 384 void fd_context_destroy(struct pipe_context *pctx);
 385
 386 #endif /* FREEDRENO_CONTEXT_H_ */