1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
29 #include "pipe/p_state.h"
30 #include "util/u_draw.h"
31 #include "util/u_string.h"
32 #include "util/u_memory.h"
33 #include "util/u_prim.h"
34 #include "util/u_format.h"
35 #include "util/u_helpers.h"
37 #include "freedreno_draw.h"
38 #include "freedreno_context.h"
39 #include "freedreno_state.h"
40 #include "freedreno_resource.h"
41 #include "freedreno_query_acc.h"
42 #include "freedreno_query_hw.h"
43 #include "freedreno_util.h"
46 resource_read(struct fd_batch
*batch
, struct pipe_resource
*prsc
)
50 fd_batch_resource_used(batch
, fd_resource(prsc
), false);
54 resource_written(struct fd_batch
*batch
, struct pipe_resource
*prsc
)
58 fd_resource(prsc
)->valid
= true;
59 fd_batch_resource_used(batch
, fd_resource(prsc
), true);
63 fd_draw_vbo(struct pipe_context
*pctx
, const struct pipe_draw_info
*info
)
65 struct fd_context
*ctx
= fd_context(pctx
);
66 struct fd_batch
*batch
= ctx
->batch
;
67 struct pipe_framebuffer_state
*pfb
= &batch
->framebuffer
;
68 struct pipe_scissor_state
*scissor
= fd_context_get_scissor(ctx
);
69 unsigned i
, prims
, buffers
= 0, restore_buffers
= 0;
71 /* for debugging problems with indirect draw, it is convenient
72 * to be able to emulate it, to determine if game is feeding us
75 if (info
->indirect
&& (fd_mesa_debug
& FD_DBG_NOINDR
)) {
76 util_draw_indirect(pctx
, info
);
80 if (!info
->count_from_stream_output
&& !info
->indirect
&&
81 !info
->primitive_restart
&&
82 !u_trim_pipe_prim(info
->mode
, (unsigned*)&info
->count
))
85 /* if we supported transform feedback, we'd have to disable this: */
86 if (((scissor
->maxx
- scissor
->minx
) *
87 (scissor
->maxy
- scissor
->miny
)) == 0) {
91 /* TODO: push down the region versions into the tiles */
92 if (!fd_render_condition_check(pctx
))
95 /* emulate unsupported primitives: */
96 if (!fd_supported_prim(ctx
, info
->mode
)) {
97 if (ctx
->streamout
.num_targets
> 0)
98 debug_error("stream-out with emulated prims");
99 util_primconvert_save_rasterizer_state(ctx
->primconvert
, ctx
->rasterizer
);
100 util_primconvert_draw_vbo(ctx
->primconvert
, info
);
104 /* Upload a user index buffer. */
105 struct pipe_resource
*indexbuf
= NULL
;
106 unsigned index_offset
= 0;
107 struct pipe_draw_info new_info
;
108 if (info
->index_size
) {
109 if (info
->has_user_indices
) {
110 if (!util_upload_index_buffer(pctx
, info
, &indexbuf
, &index_offset
))
113 new_info
.index
.resource
= indexbuf
;
114 new_info
.has_user_indices
= false;
117 indexbuf
= info
->index
.resource
;
122 fd_batch_reset(batch
);
123 fd_context_all_dirty(ctx
);
126 batch
->blit
= ctx
->in_blit
;
127 batch
->back_blit
= ctx
->in_shadow
;
129 /* NOTE: needs to be before resource_written(batch->query_buf), otherwise
130 * query_buf may not be created yet.
132 fd_batch_set_stage(batch
, FD_STAGE_DRAW
);
135 * Figure out the buffers/features we need:
138 mtx_lock(&ctx
->screen
->lock
);
140 if (fd_depth_enabled(ctx
)) {
141 if (fd_resource(pfb
->zsbuf
->texture
)->valid
)
142 restore_buffers
|= FD_BUFFER_DEPTH
;
143 buffers
|= FD_BUFFER_DEPTH
;
144 resource_written(batch
, pfb
->zsbuf
->texture
);
145 batch
->gmem_reason
|= FD_GMEM_DEPTH_ENABLED
;
148 if (fd_stencil_enabled(ctx
)) {
149 if (fd_resource(pfb
->zsbuf
->texture
)->valid
)
150 restore_buffers
|= FD_BUFFER_DEPTH
;
151 buffers
|= FD_BUFFER_STENCIL
;
152 resource_written(batch
, pfb
->zsbuf
->texture
);
153 batch
->gmem_reason
|= FD_GMEM_STENCIL_ENABLED
;
156 if (fd_logicop_enabled(ctx
))
157 batch
->gmem_reason
|= FD_GMEM_LOGICOP_ENABLED
;
159 for (i
= 0; i
< pfb
->nr_cbufs
; i
++) {
160 struct pipe_resource
*surf
;
165 surf
= pfb
->cbufs
[i
]->texture
;
167 resource_written(batch
, surf
);
169 if (fd_resource(surf
)->valid
)
170 restore_buffers
|= PIPE_CLEAR_COLOR0
<< i
;
172 buffers
|= PIPE_CLEAR_COLOR0
<< i
;
174 if (surf
->nr_samples
> 1)
175 batch
->gmem_reason
|= FD_GMEM_MSAA_ENABLED
;
177 if (fd_blend_enabled(ctx
, i
))
178 batch
->gmem_reason
|= FD_GMEM_BLEND_ENABLED
;
181 /* Mark SSBOs as being written.. we don't actually know which ones are
182 * read vs written, so just assume the worst
184 foreach_bit(i
, ctx
->shaderbuf
[PIPE_SHADER_FRAGMENT
].enabled_mask
)
185 resource_written(batch
, ctx
->shaderbuf
[PIPE_SHADER_FRAGMENT
].sb
[i
].buffer
);
187 foreach_bit(i
, ctx
->shaderimg
[PIPE_SHADER_FRAGMENT
].enabled_mask
) {
188 struct pipe_image_view
*img
=
189 &ctx
->shaderimg
[PIPE_SHADER_FRAGMENT
].si
[i
];
190 if (img
->access
& PIPE_IMAGE_ACCESS_WRITE
)
191 resource_written(batch
, img
->resource
);
193 resource_read(batch
, img
->resource
);
196 foreach_bit(i
, ctx
->constbuf
[PIPE_SHADER_VERTEX
].enabled_mask
)
197 resource_read(batch
, ctx
->constbuf
[PIPE_SHADER_VERTEX
].cb
[i
].buffer
);
198 foreach_bit(i
, ctx
->constbuf
[PIPE_SHADER_FRAGMENT
].enabled_mask
)
199 resource_read(batch
, ctx
->constbuf
[PIPE_SHADER_FRAGMENT
].cb
[i
].buffer
);
201 /* Mark VBOs as being read */
202 foreach_bit(i
, ctx
->vtx
.vertexbuf
.enabled_mask
) {
203 assert(!ctx
->vtx
.vertexbuf
.vb
[i
].is_user_buffer
);
204 resource_read(batch
, ctx
->vtx
.vertexbuf
.vb
[i
].buffer
.resource
);
207 /* Mark index buffer as being read */
208 resource_read(batch
, indexbuf
);
210 /* Mark indirect draw buffer as being read */
212 resource_read(batch
, info
->indirect
->buffer
);
214 /* Mark textures as being read */
215 foreach_bit(i
, ctx
->tex
[PIPE_SHADER_VERTEX
].valid_textures
)
216 resource_read(batch
, ctx
->tex
[PIPE_SHADER_VERTEX
].textures
[i
]->texture
);
217 foreach_bit(i
, ctx
->tex
[PIPE_SHADER_FRAGMENT
].valid_textures
)
218 resource_read(batch
, ctx
->tex
[PIPE_SHADER_FRAGMENT
].textures
[i
]->texture
);
220 /* Mark streamout buffers as being written.. */
221 for (i
= 0; i
< ctx
->streamout
.num_targets
; i
++)
222 if (ctx
->streamout
.targets
[i
])
223 resource_written(batch
, ctx
->streamout
.targets
[i
]->buffer
);
225 resource_written(batch
, batch
->query_buf
);
227 list_for_each_entry(struct fd_acc_query
, aq
, &ctx
->acc_active_queries
, node
)
228 resource_written(batch
, aq
->prsc
);
230 mtx_unlock(&ctx
->screen
->lock
);
234 prims
= u_reduced_prims_for_vertices(info
->mode
, info
->count
);
236 ctx
->stats
.draw_calls
++;
238 /* TODO prims_emitted should be clipped when the stream-out buffer is
239 * not large enough. See max_tf_vtx().. probably need to move that
240 * into common code. Although a bit more annoying since a2xx doesn't
241 * use ir3 so no common way to get at the pipe_stream_output_info
242 * which is needed for this calculation.
244 if (ctx
->streamout
.num_targets
> 0)
245 ctx
->stats
.prims_emitted
+= prims
;
246 ctx
->stats
.prims_generated
+= prims
;
248 /* any buffers that haven't been cleared yet, we need to restore: */
249 batch
->restore
|= restore_buffers
& (FD_BUFFER_ALL
& ~batch
->cleared
);
250 /* and any buffers used, need to be resolved: */
251 batch
->resolve
|= buffers
;
253 DBG("%p: %x %ux%u num_draws=%u (%s/%s)", batch
, buffers
,
254 pfb
->width
, pfb
->height
, batch
->num_draws
,
255 util_format_short_name(pipe_surface_format(pfb
->cbufs
[0])),
256 util_format_short_name(pipe_surface_format(pfb
->zsbuf
)));
258 if (ctx
->draw_vbo(ctx
, info
, index_offset
))
259 batch
->needs_flush
= true;
261 for (i
= 0; i
< ctx
->streamout
.num_targets
; i
++)
262 ctx
->streamout
.offsets
[i
] += info
->count
;
264 if (fd_mesa_debug
& FD_DBG_DDRAW
)
265 fd_context_all_dirty(ctx
);
267 fd_batch_check_size(batch
);
269 if (info
== &new_info
)
270 pipe_resource_reference(&indexbuf
, NULL
);
273 /* Generic clear implementation (partially) using u_blitter: */
275 fd_blitter_clear(struct pipe_context
*pctx
, unsigned buffers
,
276 const union pipe_color_union
*color
, double depth
, unsigned stencil
)
278 struct fd_context
*ctx
= fd_context(pctx
);
279 struct pipe_framebuffer_state
*pfb
= &ctx
->batch
->framebuffer
;
280 struct blitter_context
*blitter
= ctx
->blitter
;
282 fd_blitter_pipe_begin(ctx
, false, true, FD_STAGE_CLEAR
);
284 util_blitter_common_clear_setup(blitter
, pfb
->width
, pfb
->height
,
285 buffers
, NULL
, NULL
);
287 struct pipe_stencil_ref sr
= {
288 .ref_value
= { stencil
& 0xff }
290 pctx
->set_stencil_ref(pctx
, &sr
);
292 struct pipe_constant_buffer cb
= {
294 .user_buffer
= &color
->ui
,
296 pctx
->set_constant_buffer(pctx
, PIPE_SHADER_FRAGMENT
, 0, &cb
);
298 if (!ctx
->clear_rs_state
) {
299 const struct pipe_rasterizer_state tmpl
= {
300 .cull_face
= PIPE_FACE_NONE
,
301 .half_pixel_center
= 1,
302 .bottom_edge_rule
= 1,
306 ctx
->clear_rs_state
= pctx
->create_rasterizer_state(pctx
, &tmpl
);
308 pctx
->bind_rasterizer_state(pctx
, ctx
->clear_rs_state
);
310 struct pipe_viewport_state vp
= {
311 .scale
= { 0.5f
* pfb
->width
, -0.5f
* pfb
->height
, depth
},
312 .translate
= { 0.5f
* pfb
->width
, 0.5f
* pfb
->height
, 0.0f
},
314 pctx
->set_viewport_states(pctx
, 0, 1, &vp
);
316 pctx
->bind_vertex_elements_state(pctx
, ctx
->solid_vbuf_state
.vtx
);
317 pctx
->set_vertex_buffers(pctx
, blitter
->vb_slot
, 1,
318 &ctx
->solid_vbuf_state
.vertexbuf
.vb
[0]);
319 pctx
->set_stream_output_targets(pctx
, 0, NULL
, NULL
);
320 pctx
->bind_vs_state(pctx
, ctx
->solid_prog
.vp
);
321 pctx
->bind_fs_state(pctx
, ctx
->solid_prog
.fp
);
323 struct pipe_draw_info info
= {
324 .mode
= PIPE_PRIM_MAX
, /* maps to DI_PT_RECTLIST */
329 ctx
->draw_vbo(ctx
, &info
, 0);
331 util_blitter_restore_constant_buffer_state(blitter
);
332 util_blitter_restore_vertex_states(blitter
);
333 util_blitter_restore_fragment_states(blitter
);
334 util_blitter_restore_textures(blitter
);
335 util_blitter_restore_fb_state(blitter
);
336 util_blitter_restore_render_cond(blitter
);
337 util_blitter_unset_running_flag(blitter
);
339 fd_blitter_pipe_end(ctx
);
342 /* TODO figure out how to make better use of existing state mechanism
343 * for clear (and possibly gmem->mem / mem->gmem) so we can (a) keep
344 * track of what state really actually changes, and (b) reduce the code
345 * in the a2xx/a3xx parts.
349 fd_clear(struct pipe_context
*pctx
, unsigned buffers
,
350 const union pipe_color_union
*color
, double depth
, unsigned stencil
)
352 struct fd_context
*ctx
= fd_context(pctx
);
353 struct fd_batch
*batch
= ctx
->batch
;
354 struct pipe_framebuffer_state
*pfb
= &batch
->framebuffer
;
355 struct pipe_scissor_state
*scissor
= fd_context_get_scissor(ctx
);
356 unsigned cleared_buffers
;
359 /* TODO: push down the region versions into the tiles */
360 if (!fd_render_condition_check(pctx
))
364 fd_batch_reset(batch
);
365 fd_context_all_dirty(ctx
);
368 /* for bookkeeping about which buffers have been cleared (and thus
369 * can fully or partially skip mem2gmem) we need to ignore buffers
370 * that have already had a draw, in case apps do silly things like
371 * clear after draw (ie. if you only clear the color buffer, but
372 * something like alpha-test causes side effects from the draw in
373 * the depth buffer, etc)
375 cleared_buffers
= buffers
& (FD_BUFFER_ALL
& ~batch
->restore
);
377 /* do we have full-screen scissor? */
378 if (!memcmp(scissor
, &ctx
->disabled_scissor
, sizeof(*scissor
))) {
379 batch
->cleared
|= cleared_buffers
;
381 batch
->partial_cleared
|= cleared_buffers
;
382 if (cleared_buffers
& PIPE_CLEAR_COLOR
)
383 batch
->cleared_scissor
.color
= *scissor
;
384 if (cleared_buffers
& PIPE_CLEAR_DEPTH
)
385 batch
->cleared_scissor
.depth
= *scissor
;
386 if (cleared_buffers
& PIPE_CLEAR_STENCIL
)
387 batch
->cleared_scissor
.stencil
= *scissor
;
389 batch
->resolve
|= buffers
;
390 batch
->needs_flush
= true;
392 mtx_lock(&ctx
->screen
->lock
);
394 if (buffers
& PIPE_CLEAR_COLOR
)
395 for (i
= 0; i
< pfb
->nr_cbufs
; i
++)
396 if (buffers
& (PIPE_CLEAR_COLOR0
<< i
))
397 resource_written(batch
, pfb
->cbufs
[i
]->texture
);
399 if (buffers
& (PIPE_CLEAR_DEPTH
| PIPE_CLEAR_STENCIL
)) {
400 resource_written(batch
, pfb
->zsbuf
->texture
);
401 batch
->gmem_reason
|= FD_GMEM_CLEARS_DEPTH_STENCIL
;
404 resource_written(batch
, batch
->query_buf
);
406 list_for_each_entry(struct fd_acc_query
, aq
, &ctx
->acc_active_queries
, node
)
407 resource_written(batch
, aq
->prsc
);
409 mtx_unlock(&ctx
->screen
->lock
);
411 DBG("%p: %x %ux%u depth=%f, stencil=%u (%s/%s)", batch
, buffers
,
412 pfb
->width
, pfb
->height
, depth
, stencil
,
413 util_format_short_name(pipe_surface_format(pfb
->cbufs
[0])),
414 util_format_short_name(pipe_surface_format(pfb
->zsbuf
)));
416 /* if per-gen backend doesn't implement ctx->clear() generic
419 bool fallback
= true;
422 fd_batch_set_stage(batch
, FD_STAGE_CLEAR
);
424 if (ctx
->clear(ctx
, buffers
, color
, depth
, stencil
)) {
425 if (fd_mesa_debug
& FD_DBG_DCLEAR
)
426 fd_context_all_dirty(ctx
);
433 fd_blitter_clear(pctx
, buffers
, color
, depth
, stencil
);
438 fd_clear_render_target(struct pipe_context
*pctx
, struct pipe_surface
*ps
,
439 const union pipe_color_union
*color
,
440 unsigned x
, unsigned y
, unsigned w
, unsigned h
,
441 bool render_condition_enabled
)
443 DBG("TODO: x=%u, y=%u, w=%u, h=%u", x
, y
, w
, h
);
447 fd_clear_depth_stencil(struct pipe_context
*pctx
, struct pipe_surface
*ps
,
448 unsigned buffers
, double depth
, unsigned stencil
,
449 unsigned x
, unsigned y
, unsigned w
, unsigned h
,
450 bool render_condition_enabled
)
452 DBG("TODO: buffers=%u, depth=%f, stencil=%u, x=%u, y=%u, w=%u, h=%u",
453 buffers
, depth
, stencil
, x
, y
, w
, h
);
457 fd_launch_grid(struct pipe_context
*pctx
, const struct pipe_grid_info
*info
)
459 struct fd_context
*ctx
= fd_context(pctx
);
460 struct fd_batch
*batch
, *save_batch
= NULL
;
463 batch
= fd_batch_create(ctx
);
464 fd_batch_reference(&save_batch
, ctx
->batch
);
465 fd_batch_reference(&ctx
->batch
, batch
);
467 mtx_lock(&ctx
->screen
->lock
);
469 /* Mark SSBOs as being written.. we don't actually know which ones are
470 * read vs written, so just assume the worst
472 foreach_bit(i
, ctx
->shaderbuf
[PIPE_SHADER_COMPUTE
].enabled_mask
)
473 resource_read(batch
, ctx
->shaderbuf
[PIPE_SHADER_COMPUTE
].sb
[i
].buffer
);
475 foreach_bit(i
, ctx
->shaderimg
[PIPE_SHADER_COMPUTE
].enabled_mask
) {
476 struct pipe_image_view
*img
=
477 &ctx
->shaderimg
[PIPE_SHADER_COMPUTE
].si
[i
];
478 if (img
->access
& PIPE_IMAGE_ACCESS_WRITE
)
479 resource_written(batch
, img
->resource
);
481 resource_read(batch
, img
->resource
);
485 foreach_bit(i
, ctx
->constbuf
[PIPE_SHADER_COMPUTE
].enabled_mask
)
486 resource_read(batch
, ctx
->constbuf
[PIPE_SHADER_COMPUTE
].cb
[i
].buffer
);
488 /* Mark textures as being read */
489 foreach_bit(i
, ctx
->tex
[PIPE_SHADER_COMPUTE
].valid_textures
)
490 resource_read(batch
, ctx
->tex
[PIPE_SHADER_COMPUTE
].textures
[i
]->texture
);
493 resource_read(batch
, info
->indirect
);
495 mtx_unlock(&ctx
->screen
->lock
);
497 ctx
->launch_grid(ctx
, info
);
499 fd_gmem_flush_compute(batch
);
501 fd_batch_reference(&ctx
->batch
, save_batch
);
502 fd_batch_reference(&save_batch
, NULL
);
506 fd_draw_init(struct pipe_context
*pctx
)
508 pctx
->draw_vbo
= fd_draw_vbo
;
509 pctx
->clear
= fd_clear
;
510 pctx
->clear_render_target
= fd_clear_render_target
;
511 pctx
->clear_depth_stencil
= fd_clear_depth_stencil
;
513 if (has_compute(fd_screen(pctx
->screen
))) {
514 pctx
->launch_grid
= fd_launch_grid
;