freedreno: enable a306
[mesa.git] / src / gallium / drivers / freedreno / freedreno_gmem.c
1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
2
3 /*
4 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
23 * SOFTWARE.
24 *
25 * Authors:
26 * Rob Clark <robclark@freedesktop.org>
27 */
28
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_inlines.h"
33 #include "util/u_format.h"
34
35 #include "freedreno_gmem.h"
36 #include "freedreno_context.h"
37 #include "freedreno_resource.h"
38 #include "freedreno_query_hw.h"
39 #include "freedreno_util.h"
40
41 /*
42 * GMEM is the small (ie. 256KiB for a200, 512KiB for a220, etc) tile buffer
43 * inside the GPU. All rendering happens to GMEM. Larger render targets
44 * are split into tiles that are small enough for the color (and depth and/or
45 * stencil, if enabled) buffers to fit within GMEM. Before rendering a tile,
46 * if there was not a clear invalidating the previous tile contents, we need
47 * to restore the previous tiles contents (system mem -> GMEM), and after all
48 * the draw calls, before moving to the next tile, we need to save the tile
49 * contents (GMEM -> system mem).
50 *
51 * The code in this file handles dealing with GMEM and tiling.
52 *
53 * The structure of the ringbuffer ends up being:
54 *
55 * +--<---<-- IB ---<---+---<---+---<---<---<--+
56 * | | | |
57 * v ^ ^ ^
58 * ------------------------------------------------------
59 * | clear/draw cmds | Tile0 | Tile1 | .... | TileN |
60 * ------------------------------------------------------
61 * ^
62 * |
63 * address submitted in issueibcmds
64 *
65 * Where the per-tile section handles scissor setup, mem2gmem restore (if
66 * needed), IB to draw cmds earlier in the ringbuffer, and then gmem2mem
67 * resolve.
68 */
69
70 static uint32_t bin_width(struct fd_context *ctx)
71 {
72 if (is_a4xx(ctx->screen))
73 return 1024;
74 if (is_a3xx(ctx->screen))
75 return 992;
76 return 512;
77 }
78
79 static uint32_t
80 total_size(uint8_t cbuf_cpp[], uint8_t zsbuf_cpp[2],
81 uint32_t bin_w, uint32_t bin_h, struct fd_gmem_stateobj *gmem)
82 {
83 uint32_t total = 0, i;
84
85 for (i = 0; i < 4; i++) {
86 if (cbuf_cpp[i]) {
87 gmem->cbuf_base[i] = align(total, 0x4000);
88 total = gmem->cbuf_base[i] + cbuf_cpp[i] * bin_w * bin_h;
89 }
90 }
91
92 if (zsbuf_cpp[0]) {
93 gmem->zsbuf_base[0] = align(total, 0x4000);
94 total = gmem->zsbuf_base[0] + zsbuf_cpp[0] * bin_w * bin_h;
95 }
96
97 if (zsbuf_cpp[1]) {
98 gmem->zsbuf_base[1] = align(total, 0x4000);
99 total = gmem->zsbuf_base[1] + zsbuf_cpp[1] * bin_w * bin_h;
100 }
101
102 return total;
103 }
104
105 static void
106 calculate_tiles(struct fd_context *ctx)
107 {
108 struct fd_gmem_stateobj *gmem = &ctx->gmem;
109 struct pipe_scissor_state *scissor = &ctx->max_scissor;
110 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
111 uint32_t gmem_size = ctx->screen->gmemsize_bytes;
112 uint32_t minx, miny, width, height;
113 uint32_t nbins_x = 1, nbins_y = 1;
114 uint32_t bin_w, bin_h;
115 uint32_t max_width = bin_width(ctx);
116 uint8_t cbuf_cpp[4] = {0}, zsbuf_cpp[2] = {0};
117 uint32_t i, j, t, xoff, yoff;
118 uint32_t tpp_x, tpp_y;
119 bool has_zs = !!(ctx->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL));
120
121 if (has_zs) {
122 struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
123 zsbuf_cpp[0] = rsc->cpp;
124 if (rsc->stencil)
125 zsbuf_cpp[1] = rsc->stencil->cpp;
126 }
127 for (i = 0; i < pfb->nr_cbufs; i++) {
128 if (pfb->cbufs[i])
129 cbuf_cpp[i] = util_format_get_blocksize(pfb->cbufs[i]->format);
130 else
131 cbuf_cpp[i] = 4;
132 }
133
134 if (!memcmp(gmem->zsbuf_cpp, zsbuf_cpp, sizeof(zsbuf_cpp)) &&
135 !memcmp(gmem->cbuf_cpp, cbuf_cpp, sizeof(cbuf_cpp)) &&
136 !memcmp(&gmem->scissor, scissor, sizeof(gmem->scissor))) {
137 /* everything is up-to-date */
138 return;
139 }
140
141 if (fd_mesa_debug & FD_DBG_NOSCIS) {
142 minx = 0;
143 miny = 0;
144 width = pfb->width;
145 height = pfb->height;
146 } else {
147 minx = scissor->minx & ~31; /* round down to multiple of 32 */
148 miny = scissor->miny & ~31;
149 width = scissor->maxx - minx;
150 height = scissor->maxy - miny;
151 }
152
153 bin_w = align(width, 32);
154 bin_h = align(height, 32);
155
156 /* first, find a bin width that satisfies the maximum width
157 * restrictions:
158 */
159 while (bin_w > max_width) {
160 nbins_x++;
161 bin_w = align(width / nbins_x, 32);
162 }
163
164 /* then find a bin width/height that satisfies the memory
165 * constraints:
166 */
167 DBG("binning input: cbuf cpp: %d %d %d %d, zsbuf cpp: %d; %dx%d",
168 cbuf_cpp[0], cbuf_cpp[1], cbuf_cpp[2], cbuf_cpp[3], zsbuf_cpp[0],
169 width, height);
170 while (total_size(cbuf_cpp, zsbuf_cpp, bin_w, bin_h, gmem) > gmem_size) {
171 if (bin_w > bin_h) {
172 nbins_x++;
173 bin_w = align(width / nbins_x, 32);
174 } else {
175 nbins_y++;
176 bin_h = align(height / nbins_y, 32);
177 }
178 }
179
180 DBG("using %d bins of size %dx%d", nbins_x*nbins_y, bin_w, bin_h);
181
182 gmem->scissor = *scissor;
183 memcpy(gmem->cbuf_cpp, cbuf_cpp, sizeof(cbuf_cpp));
184 memcpy(gmem->zsbuf_cpp, zsbuf_cpp, sizeof(zsbuf_cpp));
185 gmem->bin_h = bin_h;
186 gmem->bin_w = bin_w;
187 gmem->nbins_x = nbins_x;
188 gmem->nbins_y = nbins_y;
189 gmem->minx = minx;
190 gmem->miny = miny;
191 gmem->width = width;
192 gmem->height = height;
193
194 /*
195 * Assign tiles and pipes:
196 *
197 * At some point it might be worth playing with different
198 * strategies and seeing if that makes much impact on
199 * performance.
200 */
201
202 #define div_round_up(v, a) (((v) + (a) - 1) / (a))
203 /* figure out number of tiles per pipe: */
204 tpp_x = tpp_y = 1;
205 while (div_round_up(nbins_y, tpp_y) > 8)
206 tpp_y += 2;
207 while ((div_round_up(nbins_y, tpp_y) *
208 div_round_up(nbins_x, tpp_x)) > 8)
209 tpp_x += 1;
210
211 /* configure pipes: */
212 xoff = yoff = 0;
213 for (i = 0; i < ARRAY_SIZE(ctx->pipe); i++) {
214 struct fd_vsc_pipe *pipe = &ctx->pipe[i];
215
216 if (xoff >= nbins_x) {
217 xoff = 0;
218 yoff += tpp_y;
219 }
220
221 if (yoff >= nbins_y) {
222 break;
223 }
224
225 pipe->x = xoff;
226 pipe->y = yoff;
227 pipe->w = MIN2(tpp_x, nbins_x - xoff);
228 pipe->h = MIN2(tpp_y, nbins_y - yoff);
229
230 xoff += tpp_x;
231 }
232
233 for (; i < ARRAY_SIZE(ctx->pipe); i++) {
234 struct fd_vsc_pipe *pipe = &ctx->pipe[i];
235 pipe->x = pipe->y = pipe->w = pipe->h = 0;
236 }
237
238 #if 0 /* debug */
239 printf("%dx%d ... tpp=%dx%d\n", nbins_x, nbins_y, tpp_x, tpp_y);
240 for (i = 0; i < 8; i++) {
241 struct fd_vsc_pipe *pipe = &ctx->pipe[i];
242 printf("pipe[%d]: %ux%u @ %u,%u\n", i,
243 pipe->w, pipe->h, pipe->x, pipe->y);
244 }
245 #endif
246
247 /* configure tiles: */
248 t = 0;
249 yoff = miny;
250 for (i = 0; i < nbins_y; i++) {
251 uint32_t bw, bh;
252
253 xoff = minx;
254
255 /* clip bin height: */
256 bh = MIN2(bin_h, miny + height - yoff);
257
258 for (j = 0; j < nbins_x; j++) {
259 struct fd_tile *tile = &ctx->tile[t];
260 uint32_t n, p;
261
262 assert(t < ARRAY_SIZE(ctx->tile));
263
264 /* pipe number: */
265 p = ((i / tpp_y) * div_round_up(nbins_x, tpp_x)) + (j / tpp_x);
266
267 /* slot number: */
268 n = ((i % tpp_y) * tpp_x) + (j % tpp_x);
269
270 /* clip bin width: */
271 bw = MIN2(bin_w, minx + width - xoff);
272
273 tile->n = n;
274 tile->p = p;
275 tile->bin_w = bw;
276 tile->bin_h = bh;
277 tile->xoff = xoff;
278 tile->yoff = yoff;
279
280 t++;
281
282 xoff += bw;
283 }
284
285 yoff += bh;
286 }
287
288 #if 0 /* debug */
289 t = 0;
290 for (i = 0; i < nbins_y; i++) {
291 for (j = 0; j < nbins_x; j++) {
292 struct fd_tile *tile = &ctx->tile[t++];
293 printf("|p:%u n:%u|", tile->p, tile->n);
294 }
295 printf("\n");
296 }
297 #endif
298 }
299
300 static void
301 render_tiles(struct fd_context *ctx)
302 {
303 struct fd_gmem_stateobj *gmem = &ctx->gmem;
304 int i;
305
306 ctx->emit_tile_init(ctx);
307
308 if (ctx->restore)
309 ctx->stats.batch_restore++;
310
311 for (i = 0; i < (gmem->nbins_x * gmem->nbins_y); i++) {
312 struct fd_tile *tile = &ctx->tile[i];
313
314 DBG("bin_h=%d, yoff=%d, bin_w=%d, xoff=%d",
315 tile->bin_h, tile->yoff, tile->bin_w, tile->xoff);
316
317 ctx->emit_tile_prep(ctx, tile);
318
319 if (ctx->restore) {
320 fd_hw_query_set_stage(ctx, ctx->ring, FD_STAGE_MEM2GMEM);
321 ctx->emit_tile_mem2gmem(ctx, tile);
322 fd_hw_query_set_stage(ctx, ctx->ring, FD_STAGE_NULL);
323 }
324
325 ctx->emit_tile_renderprep(ctx, tile);
326
327 fd_hw_query_prepare_tile(ctx, i, ctx->ring);
328
329 /* emit IB to drawcmds: */
330 OUT_IB(ctx->ring, ctx->draw_start, ctx->draw_end);
331 fd_reset_wfi(ctx);
332
333 /* emit gmem2mem to transfer tile back to system memory: */
334 fd_hw_query_set_stage(ctx, ctx->ring, FD_STAGE_GMEM2MEM);
335 ctx->emit_tile_gmem2mem(ctx, tile);
336 fd_hw_query_set_stage(ctx, ctx->ring, FD_STAGE_NULL);
337 }
338 }
339
340 static void
341 render_sysmem(struct fd_context *ctx)
342 {
343 ctx->emit_sysmem_prep(ctx);
344
345 fd_hw_query_prepare_tile(ctx, 0, ctx->ring);
346
347 /* emit IB to drawcmds: */
348 OUT_IB(ctx->ring, ctx->draw_start, ctx->draw_end);
349 fd_reset_wfi(ctx);
350 }
351
352 void
353 fd_gmem_render_tiles(struct fd_context *ctx)
354 {
355 struct pipe_framebuffer_state *pfb = &ctx->framebuffer;
356 bool sysmem = false;
357
358 if (ctx->emit_sysmem_prep) {
359 if (ctx->cleared || ctx->gmem_reason || (ctx->num_draws > 5)) {
360 DBG("GMEM: cleared=%x, gmem_reason=%x, num_draws=%u",
361 ctx->cleared, ctx->gmem_reason, ctx->num_draws);
362 } else if (!(fd_mesa_debug & FD_DBG_NOBYPASS)) {
363 sysmem = true;
364 }
365 }
366
367 /* close out the draw cmds by making sure any active queries are
368 * paused:
369 */
370 fd_hw_query_set_stage(ctx, ctx->ring, FD_STAGE_NULL);
371
372 /* mark the end of the clear/draw cmds before emitting per-tile cmds: */
373 fd_ringmarker_mark(ctx->draw_end);
374 fd_ringmarker_mark(ctx->binning_end);
375
376 fd_reset_wfi(ctx);
377
378 ctx->stats.batch_total++;
379
380 if (sysmem) {
381 DBG("rendering sysmem (%s/%s)",
382 util_format_short_name(pipe_surface_format(pfb->cbufs[0])),
383 util_format_short_name(pipe_surface_format(pfb->zsbuf)));
384 fd_hw_query_prepare(ctx, 1);
385 render_sysmem(ctx);
386 ctx->stats.batch_sysmem++;
387 } else {
388 struct fd_gmem_stateobj *gmem = &ctx->gmem;
389 calculate_tiles(ctx);
390 DBG("rendering %dx%d tiles (%s/%s)", gmem->nbins_x, gmem->nbins_y,
391 util_format_short_name(pipe_surface_format(pfb->cbufs[0])),
392 util_format_short_name(pipe_surface_format(pfb->zsbuf)));
393 fd_hw_query_prepare(ctx, gmem->nbins_x * gmem->nbins_y);
394 render_tiles(ctx);
395 ctx->stats.batch_gmem++;
396 }
397
398 /* GPU executes starting from tile cmds, which IB back to draw cmds: */
399 fd_ringmarker_flush(ctx->draw_end);
400
401 /* mark start for next draw/binning cmds: */
402 fd_ringmarker_mark(ctx->draw_start);
403 fd_ringmarker_mark(ctx->binning_start);
404
405 fd_reset_wfi(ctx);
406
407 /* reset maximal bounds: */
408 ctx->max_scissor.minx = ctx->max_scissor.miny = ~0;
409 ctx->max_scissor.maxx = ctx->max_scissor.maxy = 0;
410
411 ctx->dirty = ~0;
412 }
413
414 /* tile needs restore if it isn't completely contained within the
415 * cleared scissor:
416 */
417 static bool
418 skip_restore(struct pipe_scissor_state *scissor, struct fd_tile *tile)
419 {
420 unsigned minx = tile->xoff;
421 unsigned maxx = tile->xoff + tile->bin_w;
422 unsigned miny = tile->yoff;
423 unsigned maxy = tile->yoff + tile->bin_h;
424 return (minx >= scissor->minx) && (maxx <= scissor->maxx) &&
425 (miny >= scissor->miny) && (maxy <= scissor->maxy);
426 }
427
428 /* When deciding whether a tile needs mem2gmem, we need to take into
429 * account the scissor rect(s) that were cleared. To simplify we only
430 * consider the last scissor rect for each buffer, since the common
431 * case would be a single clear.
432 */
433 bool
434 fd_gmem_needs_restore(struct fd_context *ctx, struct fd_tile *tile,
435 uint32_t buffers)
436 {
437 if (!(ctx->restore & buffers))
438 return false;
439
440 /* if buffers partially cleared, then slow-path to figure out
441 * if this particular tile needs restoring:
442 */
443 if ((buffers & FD_BUFFER_COLOR) &&
444 (ctx->partial_cleared & FD_BUFFER_COLOR) &&
445 skip_restore(&ctx->cleared_scissor.color, tile))
446 return false;
447 if ((buffers & FD_BUFFER_DEPTH) &&
448 (ctx->partial_cleared & FD_BUFFER_DEPTH) &&
449 skip_restore(&ctx->cleared_scissor.depth, tile))
450 return false;
451 if ((buffers & FD_BUFFER_STENCIL) &&
452 (ctx->partial_cleared & FD_BUFFER_STENCIL) &&
453 skip_restore(&ctx->cleared_scissor.stencil, tile))
454 return false;
455
456 return true;
457 }