1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_inlines.h"
33 #include "util/u_pack_color.h"
35 #include "freedreno_gmem.h"
36 #include "freedreno_context.h"
37 #include "freedreno_state.h"
38 #include "freedreno_program.h"
39 #include "freedreno_resource.h"
40 #include "freedreno_zsa.h"
41 #include "freedreno_util.h"
44 * GMEM is the small (ie. 256KiB for a200, 512KiB for a220, etc) tile buffer
45 * inside the GPU. All rendering happens to GMEM. Larger render targets
46 * are split into tiles that are small enough for the color (and depth and/or
47 * stencil, if enabled) buffers to fit within GMEM. Before rendering a tile,
48 * if there was not a clear invalidating the previous tile contents, we need
49 * to restore the previous tiles contents (system mem -> GMEM), and after all
50 * the draw calls, before moving to the next tile, we need to save the tile
51 * contents (GMEM -> system mem).
53 * The code in this file handles dealing with GMEM and tiling.
55 * The structure of the ringbuffer ends up being:
57 * +--<---<-- IB ---<---+---<---+---<---<---<--+
60 * ------------------------------------------------------
61 * | clear/draw cmds | Tile0 | Tile1 | .... | TileN |
62 * ------------------------------------------------------
65 * address submitted in issueibcmds
67 * Where the per-tile section handles scissor setup, mem2gmem restore (if
68 * needed), IB to draw cmds earlier in the ringbuffer, and then gmem2mem
72 /* transfer from gmem to system memory (ie. normal RAM) */
75 emit_gmem2mem_surf(struct fd_ringbuffer
*ring
, uint32_t swap
, uint32_t base
,
76 struct pipe_surface
*psurf
)
78 struct fd_resource
*rsc
= fd_resource(psurf
->texture
);
80 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
81 OUT_RING(ring
, CP_REG(REG_A2XX_RB_COLOR_INFO
));
82 OUT_RING(ring
, A2XX_RB_COLOR_INFO_SWAP(swap
) |
83 A2XX_RB_COLOR_INFO_BASE(base
/ 1024) |
84 A2XX_RB_COLOR_INFO_FORMAT(fd_pipe2color(psurf
->format
)));
86 OUT_PKT3(ring
, CP_SET_CONSTANT
, 5);
87 OUT_RING(ring
, CP_REG(REG_A2XX_RB_COPY_CONTROL
));
88 OUT_RING(ring
, 0x00000000); /* RB_COPY_CONTROL */
89 OUT_RELOC(ring
, rsc
->bo
, 0, 0); /* RB_COPY_DEST_BASE */
90 OUT_RING(ring
, rsc
->pitch
>> 5); /* RB_COPY_DEST_PITCH */
91 OUT_RING(ring
, /* RB_COPY_DEST_INFO */
92 A2XX_RB_COPY_DEST_INFO_FORMAT(fd_pipe2color(psurf
->format
)) |
93 A2XX_RB_COPY_DEST_INFO_LINEAR
|
94 A2XX_RB_COPY_DEST_INFO_SWAP(swap
) |
95 A2XX_RB_COPY_DEST_INFO_WRITE_RED
|
96 A2XX_RB_COPY_DEST_INFO_WRITE_GREEN
|
97 A2XX_RB_COPY_DEST_INFO_WRITE_BLUE
|
98 A2XX_RB_COPY_DEST_INFO_WRITE_ALPHA
);
100 OUT_PKT3(ring
, CP_WAIT_FOR_IDLE
, 1);
101 OUT_RING(ring
, 0x0000000);
103 OUT_PKT3(ring
, CP_DRAW_INDX
, 3);
104 OUT_RING(ring
, 0x00000000);
105 OUT_RING(ring
, DRAW(DI_PT_RECTLIST
, DI_SRC_SEL_AUTO_INDEX
,
106 INDEX_SIZE_IGN
, IGNORE_VISIBILITY
));
107 OUT_RING(ring
, 3); /* NumIndices */
111 emit_gmem2mem(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
112 uint32_t xoff
, uint32_t yoff
, uint32_t bin_w
, uint32_t bin_h
)
114 struct pipe_framebuffer_state
*pfb
= &ctx
->framebuffer
;
116 fd_emit_vertex_bufs(ring
, 0x9c, (struct fd_vertex_buf
[]) {
117 { .prsc
= ctx
->solid_vertexbuf
, .size
= 48 },
120 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
121 OUT_RING(ring
, CP_REG(REG_A2XX_VGT_INDX_OFFSET
));
124 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
125 OUT_RING(ring
, CP_REG(REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL
));
126 OUT_RING(ring
, 0x0000028f);
128 fd_program_emit(ring
, &ctx
->solid_prog
);
130 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
131 OUT_RING(ring
, CP_REG(REG_A2XX_PA_SC_AA_MASK
));
132 OUT_RING(ring
, 0x0000ffff);
134 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
135 OUT_RING(ring
, CP_REG(REG_A2XX_RB_DEPTHCONTROL
));
136 OUT_RING(ring
, A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE
);
138 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
139 OUT_RING(ring
, CP_REG(REG_A2XX_PA_SU_SC_MODE_CNTL
));
140 OUT_RING(ring
, A2XX_PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST
| /* PA_SU_SC_MODE_CNTL */
141 A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE(PC_DRAW_TRIANGLES
) |
142 A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE(PC_DRAW_TRIANGLES
));
144 OUT_PKT3(ring
, CP_SET_CONSTANT
, 3);
145 OUT_RING(ring
, CP_REG(REG_A2XX_PA_SC_WINDOW_SCISSOR_TL
));
146 OUT_RING(ring
, xy2d(0, 0)); /* PA_SC_WINDOW_SCISSOR_TL */
147 OUT_RING(ring
, xy2d(pfb
->width
, pfb
->height
)); /* PA_SC_WINDOW_SCISSOR_BR */
149 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
150 OUT_RING(ring
, CP_REG(REG_A2XX_PA_CL_VTE_CNTL
));
151 OUT_RING(ring
, A2XX_PA_CL_VTE_CNTL_VTX_W0_FMT
|
152 A2XX_PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA
|
153 A2XX_PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA
|
154 A2XX_PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA
|
155 A2XX_PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA
);
157 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
158 OUT_RING(ring
, CP_REG(REG_A2XX_PA_CL_CLIP_CNTL
));
159 OUT_RING(ring
, 0x00000000);
161 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
162 OUT_RING(ring
, CP_REG(REG_A2XX_RB_MODECONTROL
));
163 OUT_RING(ring
, A2XX_RB_MODECONTROL_EDRAM_MODE(EDRAM_COPY
));
165 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
166 OUT_RING(ring
, CP_REG(REG_A2XX_RB_COPY_DEST_OFFSET
));
167 OUT_RING(ring
, A2XX_RB_COPY_DEST_OFFSET_X(xoff
) |
168 A2XX_RB_COPY_DEST_OFFSET_Y(yoff
));
170 if (ctx
->resolve
& (FD_BUFFER_DEPTH
| FD_BUFFER_STENCIL
))
171 emit_gmem2mem_surf(ring
, 0, bin_w
* bin_h
, pfb
->zsbuf
);
173 if (ctx
->resolve
& FD_BUFFER_COLOR
)
174 emit_gmem2mem_surf(ring
, 1, 0, pfb
->cbufs
[0]);
176 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
177 OUT_RING(ring
, CP_REG(REG_A2XX_RB_MODECONTROL
));
178 OUT_RING(ring
, A2XX_RB_MODECONTROL_EDRAM_MODE(COLOR_DEPTH
));
181 /* transfer from system memory to gmem */
184 emit_mem2gmem_surf(struct fd_ringbuffer
*ring
, uint32_t swap
, uint32_t base
,
185 struct pipe_surface
*psurf
)
187 struct fd_resource
*rsc
= fd_resource(psurf
->texture
);
190 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
191 OUT_RING(ring
, CP_REG(REG_A2XX_RB_COLOR_INFO
));
192 OUT_RING(ring
, A2XX_RB_COLOR_INFO_SWAP(swap
) |
193 A2XX_RB_COLOR_INFO_BASE(base
) |
194 A2XX_RB_COLOR_INFO_FORMAT(fd_pipe2color(psurf
->format
)));
196 swiz
= fd_tex_swiz(psurf
->format
, PIPE_SWIZZLE_RED
, PIPE_SWIZZLE_GREEN
,
197 PIPE_SWIZZLE_BLUE
, PIPE_SWIZZLE_ALPHA
);
199 /* emit fb as a texture: */
200 OUT_PKT3(ring
, CP_SET_CONSTANT
, 7);
201 OUT_RING(ring
, 0x00010000);
202 OUT_RING(ring
, A2XX_SQ_TEX_0_CLAMP_X(SQ_TEX_WRAP
) |
203 A2XX_SQ_TEX_0_CLAMP_Y(SQ_TEX_WRAP
) |
204 A2XX_SQ_TEX_0_CLAMP_Z(SQ_TEX_WRAP
) |
205 A2XX_SQ_TEX_0_PITCH(rsc
->pitch
));
206 OUT_RELOC(ring
, rsc
->bo
, 0,
207 fd_pipe2surface(psurf
->format
) | 0x800);
208 OUT_RING(ring
, A2XX_SQ_TEX_2_WIDTH(psurf
->width
- 1) |
209 A2XX_SQ_TEX_2_HEIGHT(psurf
->height
- 1));
210 OUT_RING(ring
, 0x01000000 | // XXX
212 A2XX_SQ_TEX_3_XY_MAG_FILTER(SQ_TEX_FILTER_POINT
) |
213 A2XX_SQ_TEX_3_XY_MIN_FILTER(SQ_TEX_FILTER_POINT
));
214 OUT_RING(ring
, 0x00000000);
215 OUT_RING(ring
, 0x00000200);
217 OUT_PKT3(ring
, CP_DRAW_INDX
, 3);
218 OUT_RING(ring
, 0x00000000);
219 OUT_RING(ring
, DRAW(DI_PT_RECTLIST
, DI_SRC_SEL_AUTO_INDEX
,
220 INDEX_SIZE_IGN
, IGNORE_VISIBILITY
));
221 OUT_RING(ring
, 3); /* NumIndices */
225 emit_mem2gmem(struct fd_context
*ctx
, struct fd_ringbuffer
*ring
,
226 uint32_t xoff
, uint32_t yoff
, uint32_t bin_w
, uint32_t bin_h
)
228 struct pipe_framebuffer_state
*pfb
= &ctx
->framebuffer
;
229 float x0
, y0
, x1
, y1
;
231 fd_emit_vertex_bufs(ring
, 0x9c, (struct fd_vertex_buf
[]) {
232 { .prsc
= ctx
->solid_vertexbuf
, .size
= 48, .offset
= 0x30 },
233 { .prsc
= ctx
->solid_vertexbuf
, .size
= 32, .offset
= 0x60 },
236 /* write texture coordinates to vertexbuf: */
237 x0
= ((float)xoff
) / ((float)pfb
->width
);
238 x1
= ((float)xoff
+ bin_w
) / ((float)pfb
->width
);
239 y0
= ((float)yoff
) / ((float)pfb
->height
);
240 y1
= ((float)yoff
+ bin_h
) / ((float)pfb
->height
);
241 OUT_PKT3(ring
, CP_MEM_WRITE
, 9);
242 OUT_RELOC(ring
, fd_resource(ctx
->solid_vertexbuf
)->bo
, 0x60, 0);
243 OUT_RING(ring
, fui(x0
));
244 OUT_RING(ring
, fui(y0
));
245 OUT_RING(ring
, fui(x1
));
246 OUT_RING(ring
, fui(y0
));
247 OUT_RING(ring
, fui(x0
));
248 OUT_RING(ring
, fui(y1
));
249 OUT_RING(ring
, fui(x1
));
250 OUT_RING(ring
, fui(y1
));
252 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
253 OUT_RING(ring
, CP_REG(REG_A2XX_VGT_INDX_OFFSET
));
256 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
257 OUT_RING(ring
, CP_REG(REG_A2XX_VGT_VERTEX_REUSE_BLOCK_CNTL
));
258 OUT_RING(ring
, 0x0000003b);
260 fd_program_emit(ring
, &ctx
->blit_prog
);
262 OUT_PKT0(ring
, REG_A2XX_TC_CNTL_STATUS
, 1);
263 OUT_RING(ring
, A2XX_TC_CNTL_STATUS_L2_INVALIDATE
);
265 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
266 OUT_RING(ring
, CP_REG(REG_A2XX_RB_DEPTHCONTROL
));
267 OUT_RING(ring
, A2XX_RB_DEPTHCONTROL_EARLY_Z_ENABLE
);
269 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
270 OUT_RING(ring
, CP_REG(REG_A2XX_PA_SU_SC_MODE_CNTL
));
271 OUT_RING(ring
, A2XX_PA_SU_SC_MODE_CNTL_PROVOKING_VTX_LAST
|
272 A2XX_PA_SU_SC_MODE_CNTL_FRONT_PTYPE(PC_DRAW_TRIANGLES
) |
273 A2XX_PA_SU_SC_MODE_CNTL_BACK_PTYPE(PC_DRAW_TRIANGLES
));
275 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
276 OUT_RING(ring
, CP_REG(REG_A2XX_PA_SC_AA_MASK
));
277 OUT_RING(ring
, 0x0000ffff);
279 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
280 OUT_RING(ring
, CP_REG(REG_A2XX_RB_COLORCONTROL
));
281 OUT_RING(ring
, A2XX_RB_COLORCONTROL_ALPHA_FUNC(PIPE_FUNC_ALWAYS
) |
282 A2XX_RB_COLORCONTROL_BLEND_DISABLE
|
283 A2XX_RB_COLORCONTROL_ROP_CODE(12) |
284 A2XX_RB_COLORCONTROL_DITHER_MODE(DITHER_DISABLE
) |
285 A2XX_RB_COLORCONTROL_DITHER_TYPE(DITHER_PIXEL
));
287 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
288 OUT_RING(ring
, CP_REG(REG_A2XX_RB_BLEND_CONTROL
));
289 OUT_RING(ring
, A2XX_RB_BLEND_CONTROL_COLOR_SRCBLEND(FACTOR_ONE
) |
290 A2XX_RB_BLEND_CONTROL_COLOR_COMB_FCN(BLEND_DST_PLUS_SRC
) |
291 A2XX_RB_BLEND_CONTROL_COLOR_DESTBLEND(FACTOR_ZERO
) |
292 A2XX_RB_BLEND_CONTROL_ALPHA_SRCBLEND(FACTOR_ONE
) |
293 A2XX_RB_BLEND_CONTROL_ALPHA_COMB_FCN(BLEND_DST_PLUS_SRC
) |
294 A2XX_RB_BLEND_CONTROL_ALPHA_DESTBLEND(FACTOR_ZERO
));
296 OUT_PKT3(ring
, CP_SET_CONSTANT
, 3);
297 OUT_RING(ring
, CP_REG(REG_A2XX_PA_SC_WINDOW_SCISSOR_TL
));
298 OUT_RING(ring
, A2XX_PA_SC_WINDOW_OFFSET_DISABLE
|
299 xy2d(0,0)); /* PA_SC_WINDOW_SCISSOR_TL */
300 OUT_RING(ring
, xy2d(bin_w
, bin_h
)); /* PA_SC_WINDOW_SCISSOR_BR */
302 OUT_PKT3(ring
, CP_SET_CONSTANT
, 5);
303 OUT_RING(ring
, CP_REG(REG_A2XX_PA_CL_VPORT_XSCALE
));
304 OUT_RING(ring
, fui((float)bin_w
/2.0)); /* PA_CL_VPORT_XSCALE */
305 OUT_RING(ring
, fui((float)bin_w
/2.0)); /* PA_CL_VPORT_XOFFSET */
306 OUT_RING(ring
, fui(-(float)bin_h
/2.0)); /* PA_CL_VPORT_YSCALE */
307 OUT_RING(ring
, fui((float)bin_h
/2.0)); /* PA_CL_VPORT_YOFFSET */
309 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
310 OUT_RING(ring
, CP_REG(REG_A2XX_PA_CL_VTE_CNTL
));
311 OUT_RING(ring
, A2XX_PA_CL_VTE_CNTL_VTX_XY_FMT
|
312 A2XX_PA_CL_VTE_CNTL_VTX_Z_FMT
| // XXX check this???
313 A2XX_PA_CL_VTE_CNTL_VPORT_X_SCALE_ENA
|
314 A2XX_PA_CL_VTE_CNTL_VPORT_X_OFFSET_ENA
|
315 A2XX_PA_CL_VTE_CNTL_VPORT_Y_SCALE_ENA
|
316 A2XX_PA_CL_VTE_CNTL_VPORT_Y_OFFSET_ENA
);
318 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
319 OUT_RING(ring
, CP_REG(REG_A2XX_PA_CL_CLIP_CNTL
));
320 OUT_RING(ring
, 0x00000000);
322 if (ctx
->restore
& (FD_BUFFER_DEPTH
| FD_BUFFER_STENCIL
))
323 emit_mem2gmem_surf(ring
, 0, bin_w
* bin_h
, pfb
->zsbuf
);
325 if (ctx
->restore
& FD_BUFFER_COLOR
)
326 emit_mem2gmem_surf(ring
, 1, 0, pfb
->cbufs
[0]);
328 /* TODO blob driver seems to toss in a CACHE_FLUSH after each DRAW_INDX.. */
332 calculate_tiles(struct fd_context
*ctx
)
334 struct fd_gmem_stateobj
*gmem
= &ctx
->gmem
;
335 struct pipe_scissor_state
*scissor
= &ctx
->max_scissor
;
336 uint32_t cpp
= util_format_get_blocksize(ctx
->framebuffer
.cbufs
[0]->format
);
337 uint32_t gmem_size
= ctx
->screen
->gmemsize_bytes
;
338 uint32_t minx
, miny
, width
, height
;
339 uint32_t nbins_x
= 1, nbins_y
= 1;
340 uint32_t bin_w
, bin_h
;
341 uint32_t max_width
= 992;
343 if ((gmem
->cpp
== cpp
) &&
344 !memcmp(&gmem
->scissor
, scissor
, sizeof(gmem
->scissor
))) {
345 /* everything is up-to-date */
349 minx
= scissor
->minx
& ~31; /* round down to multiple of 32 */
350 miny
= scissor
->miny
& ~31;
351 width
= scissor
->maxx
- minx
;
352 height
= scissor
->maxy
- miny
;
354 // TODO we probably could optimize this a bit if we know that
355 // Z or stencil is not enabled for any of the draw calls..
356 // if (fd_stencil_enabled(ctx->zsa) || fd_depth_enabled(ctx->zsa)) {
361 bin_w
= ALIGN(width
, 32);
362 bin_h
= ALIGN(height
, 32);
364 /* first, find a bin width that satisfies the maximum width
367 while (bin_w
> max_width
) {
369 bin_w
= ALIGN(width
/ nbins_x
, 32);
372 /* then find a bin height that satisfies the memory constraints:
374 while ((bin_w
* bin_h
* cpp
) > gmem_size
) {
376 bin_h
= ALIGN(height
/ nbins_y
, 32);
379 DBG("using %d bins of size %dx%d", nbins_x
*nbins_y
, bin_w
, bin_h
);
381 gmem
->scissor
= *scissor
;
387 gmem
->nbins_x
= nbins_x
;
388 gmem
->nbins_y
= nbins_y
;
390 gmem
->height
= height
;
394 fd_gmem_render_tiles(struct pipe_context
*pctx
)
396 struct fd_context
*ctx
= fd_context(pctx
);
397 struct pipe_framebuffer_state
*pfb
= &ctx
->framebuffer
;
398 struct fd_gmem_stateobj
*gmem
= &ctx
->gmem
;
399 struct fd_ringbuffer
*ring
= ctx
->ring
;
400 enum a2xx_colorformatx colorformatx
= fd_pipe2color(pfb
->cbufs
[0]->format
);
401 uint32_t i
, timestamp
, yoff
= 0;
404 calculate_tiles(ctx
);
406 DBG("rendering %dx%d tiles (%s/%s)", gmem
->nbins_x
, gmem
->nbins_y
,
407 util_format_name(pfb
->cbufs
[0]->format
),
408 pfb
->zsbuf
? util_format_name(pfb
->zsbuf
->format
) : "none");
410 /* mark the end of the clear/draw cmds before emitting per-tile cmds: */
411 fd_ringmarker_mark(ctx
->draw_end
);
413 /* RB_SURFACE_INFO / RB_DEPTH_INFO can be emitted once per tile pass,
414 * but RB_COLOR_INFO gets overwritten by gmem2mem and mem2gmem and so
415 * needs to be emitted for each tile:
417 OUT_PKT3(ring
, CP_SET_CONSTANT
, 4);
418 OUT_RING(ring
, CP_REG(REG_A2XX_RB_SURFACE_INFO
));
419 OUT_RING(ring
, gmem
->bin_w
); /* RB_SURFACE_INFO */
420 OUT_RING(ring
, A2XX_RB_COLOR_INFO_SWAP(1) | /* RB_COLOR_INFO */
421 A2XX_RB_COLOR_INFO_FORMAT(colorformatx
));
422 reg
= A2XX_RB_DEPTH_INFO_DEPTH_BASE(ALIGN(gmem
->bin_w
* gmem
->bin_h
, 4));
424 reg
|= A2XX_RB_DEPTH_INFO_DEPTH_FORMAT(fd_pipe2depth(pfb
->zsbuf
->format
));
425 OUT_RING(ring
, reg
); /* RB_DEPTH_INFO */
428 for (i
= 0; i
< gmem
->nbins_y
; i
++) {
429 uint32_t j
, xoff
= gmem
->minx
;
430 uint32_t bh
= gmem
->bin_h
;
432 /* clip bin height: */
433 bh
= min(bh
, gmem
->height
- yoff
);
435 for (j
= 0; j
< gmem
->nbins_x
; j
++) {
436 uint32_t bw
= gmem
->bin_w
;
438 /* clip bin width: */
439 bw
= min(bw
, gmem
->width
- xoff
);
441 DBG("bin_h=%d, yoff=%d, bin_w=%d, xoff=%d",
444 /* setup screen scissor for current tile (same for mem2gmem): */
445 OUT_PKT3(ring
, CP_SET_CONSTANT
, 3);
446 OUT_RING(ring
, CP_REG(REG_A2XX_PA_SC_SCREEN_SCISSOR_TL
));
447 OUT_RING(ring
, xy2d(0,0)); /* PA_SC_SCREEN_SCISSOR_TL */
448 OUT_RING(ring
, xy2d(bw
, bh
)); /* PA_SC_SCREEN_SCISSOR_BR */
451 emit_mem2gmem(ctx
, ring
, xoff
, yoff
, bw
, bh
);
453 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
454 OUT_RING(ring
, CP_REG(REG_A2XX_RB_COLOR_INFO
));
455 OUT_RING(ring
, A2XX_RB_COLOR_INFO_SWAP(1) | /* RB_COLOR_INFO */
456 A2XX_RB_COLOR_INFO_FORMAT(colorformatx
));
458 /* setup window scissor and offset for current tile (different
461 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
462 OUT_RING(ring
, CP_REG(REG_A2XX_PA_SC_WINDOW_OFFSET
));
463 OUT_RING(ring
, A2XX_PA_SC_WINDOW_OFFSET_X(-xoff
) |
464 A2XX_PA_SC_WINDOW_OFFSET_Y(-yoff
));/* PA_SC_WINDOW_OFFSET */
466 /* emit IB to drawcmds: */
467 OUT_IB (ring
, ctx
->draw_start
, ctx
->draw_end
);
469 OUT_PKT3(ring
, CP_SET_CONSTANT
, 2);
470 OUT_RING(ring
, CP_REG(REG_A2XX_PA_SC_WINDOW_OFFSET
));
471 OUT_RING(ring
, 0x00000000); /* PA_SC_WINDOW_OFFSET */
473 /* emit gmem2mem to transfer tile back to system memory: */
474 emit_gmem2mem(ctx
, ring
, xoff
, yoff
, bw
, bh
);
482 /* GPU executes starting from tile cmds, which IB back to draw cmds: */
483 fd_ringmarker_flush(ctx
->draw_end
);
485 /* mark start for next draw cmds: */
486 fd_ringmarker_mark(ctx
->draw_start
);
488 /* update timestamps on render targets: */
489 fd_pipe_timestamp(ctx
->screen
->pipe
, ×tamp
);
490 fd_resource(pfb
->cbufs
[0]->texture
)->timestamp
= timestamp
;
492 fd_resource(pfb
->zsbuf
->texture
)->timestamp
= timestamp
;
494 /* reset maximal bounds: */
495 ctx
->max_scissor
.minx
= ctx
->max_scissor
.miny
= ~0;
496 ctx
->max_scissor
.maxx
= ctx
->max_scissor
.maxy
= 0;
498 /* Note that because the per-tile setup and mem2gmem/gmem2mem are emitted
499 * after the draw/clear calls, but executed before, we need to preemptively
500 * flag some state as dirty before the first draw/clear call.
502 * TODO maybe we need to mark all state as dirty to not worry about state
503 * being clobbered by other contexts?
505 ctx
->dirty
|= FD_DIRTY_ZSA
|
506 FD_DIRTY_RASTERIZER
|
507 FD_DIRTY_FRAMEBUFFER
|
508 FD_DIRTY_SAMPLE_MASK
|
513 /* probably only needed if we need to mem2gmem on the next
514 * draw.. but not sure if there is a good way to know?