1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_inlines.h"
33 #include "util/u_format.h"
35 #include "freedreno_gmem.h"
36 #include "freedreno_context.h"
37 #include "freedreno_resource.h"
38 #include "freedreno_util.h"
41 * GMEM is the small (ie. 256KiB for a200, 512KiB for a220, etc) tile buffer
42 * inside the GPU. All rendering happens to GMEM. Larger render targets
43 * are split into tiles that are small enough for the color (and depth and/or
44 * stencil, if enabled) buffers to fit within GMEM. Before rendering a tile,
45 * if there was not a clear invalidating the previous tile contents, we need
46 * to restore the previous tiles contents (system mem -> GMEM), and after all
47 * the draw calls, before moving to the next tile, we need to save the tile
48 * contents (GMEM -> system mem).
50 * The code in this file handles dealing with GMEM and tiling.
52 * The structure of the ringbuffer ends up being:
54 * +--<---<-- IB ---<---+---<---+---<---<---<--+
57 * ------------------------------------------------------
58 * | clear/draw cmds | Tile0 | Tile1 | .... | TileN |
59 * ------------------------------------------------------
62 * address submitted in issueibcmds
64 * Where the per-tile section handles scissor setup, mem2gmem restore (if
65 * needed), IB to draw cmds earlier in the ringbuffer, and then gmem2mem
69 static uint32_t bin_width(struct fd_context
*ctx
)
71 if (ctx
->screen
->gpu_id
>= 300)
77 calculate_tiles(struct fd_context
*ctx
)
79 struct fd_gmem_stateobj
*gmem
= &ctx
->gmem
;
80 struct pipe_scissor_state
*scissor
= &ctx
->max_scissor
;
81 struct pipe_framebuffer_state
*pfb
= &ctx
->framebuffer
;
82 uint32_t gmem_size
= ctx
->screen
->gmemsize_bytes
;
83 uint32_t minx
, miny
, width
, height
;
84 uint32_t nbins_x
= 1, nbins_y
= 1;
85 uint32_t bin_w
, bin_h
;
86 uint32_t max_width
= bin_width(ctx
);
88 uint32_t i
, j
, t
, xoff
, yoff
;
89 uint32_t tpp_x
, tpp_y
;
90 bool has_zs
= !!(ctx
->resolve
& (FD_BUFFER_DEPTH
| FD_BUFFER_STENCIL
));
93 cpp
= util_format_get_blocksize(pfb
->cbufs
[0]->format
);
95 if ((gmem
->cpp
== cpp
) && (gmem
->has_zs
== has_zs
) &&
96 !memcmp(&gmem
->scissor
, scissor
, sizeof(gmem
->scissor
))) {
97 /* everything is up-to-date */
101 /* if have depth/stencil, we need to leave room: */
107 if (fd_mesa_debug
& FD_DBG_DSCIS
) {
111 height
= pfb
->height
;
113 minx
= scissor
->minx
& ~31; /* round down to multiple of 32 */
114 miny
= scissor
->miny
& ~31;
115 width
= scissor
->maxx
- minx
;
116 height
= scissor
->maxy
- miny
;
119 bin_w
= align(width
, 32);
120 bin_h
= align(height
, 32);
122 /* first, find a bin width that satisfies the maximum width
125 while (bin_w
> max_width
) {
127 bin_w
= align(width
/ nbins_x
, 32);
130 /* then find a bin height that satisfies the memory constraints:
132 while ((bin_w
* bin_h
* cpp
) > gmem_size
) {
134 bin_h
= align(height
/ nbins_y
, 32);
137 DBG("using %d bins of size %dx%d", nbins_x
*nbins_y
, bin_w
, bin_h
);
139 gmem
->scissor
= *scissor
;
141 gmem
->has_zs
= has_zs
;
144 gmem
->nbins_x
= nbins_x
;
145 gmem
->nbins_y
= nbins_y
;
147 gmem
->height
= height
;
150 * Assign tiles and pipes:
152 * At some point it might be worth playing with different
153 * strategies and seeing if that makes much impact on
157 #define div_round_up(v, a) (((v) + (a) - 1) / (a))
158 /* figure out number of tiles per pipe: */
160 while (div_round_up(nbins_y
, tpp_y
) > 8)
162 while ((div_round_up(nbins_y
, tpp_y
) *
163 div_round_up(nbins_x
, tpp_x
)) > 8)
166 /* configure pipes: */
168 for (i
= 0; i
< ARRAY_SIZE(ctx
->pipe
); i
++) {
169 struct fd_vsc_pipe
*pipe
= &ctx
->pipe
[i
];
171 if (xoff
>= nbins_x
) {
176 if (yoff
>= nbins_y
) {
182 pipe
->w
= MIN2(tpp_x
, nbins_x
- xoff
);
183 pipe
->h
= MIN2(tpp_y
, nbins_y
- yoff
);
188 for (; i
< ARRAY_SIZE(ctx
->pipe
); i
++) {
189 struct fd_vsc_pipe
*pipe
= &ctx
->pipe
[i
];
190 pipe
->x
= pipe
->y
= pipe
->w
= pipe
->h
= 0;
194 printf("%dx%d ... tpp=%dx%d\n", nbins_x
, nbins_y
, tpp_x
, tpp_y
);
195 for (i
= 0; i
< 8; i
++) {
196 struct fd_vsc_pipe
*pipe
= &ctx
->pipe
[i
];
197 printf("pipe[%d]: %ux%u @ %u,%u\n", i
,
198 pipe
->w
, pipe
->h
, pipe
->x
, pipe
->y
);
202 /* configure tiles: */
205 for (i
= 0; i
< nbins_y
; i
++) {
210 /* clip bin height: */
211 bh
= MIN2(bin_h
, miny
+ height
- yoff
);
213 for (j
= 0; j
< nbins_x
; j
++) {
214 struct fd_tile
*tile
= &ctx
->tile
[t
];
217 assert(t
< ARRAY_SIZE(ctx
->tile
));
220 p
= ((i
/ tpp_y
) * div_round_up(nbins_x
, tpp_x
)) + (j
/ tpp_x
);
223 n
= ((i
% tpp_y
) * tpp_x
) + (j
% tpp_x
);
225 /* clip bin width: */
226 bw
= MIN2(bin_w
, minx
+ width
- xoff
);
245 for (i
= 0; i
< nbins_y
; i
++) {
246 for (j
= 0; j
< nbins_x
; j
++) {
247 struct fd_tile
*tile
= &ctx
->tile
[t
++];
248 printf("|p:%u n:%u|", tile
->p
, tile
->n
);
256 render_tiles(struct fd_context
*ctx
)
258 struct fd_gmem_stateobj
*gmem
= &ctx
->gmem
;
261 ctx
->emit_tile_init(ctx
);
264 ctx
->stats
.batch_restore
++;
266 for (i
= 0; i
< (gmem
->nbins_x
* gmem
->nbins_y
); i
++) {
267 struct fd_tile
*tile
= &ctx
->tile
[i
];
269 DBG("bin_h=%d, yoff=%d, bin_w=%d, xoff=%d",
270 tile
->bin_h
, tile
->yoff
, tile
->bin_w
, tile
->xoff
);
272 ctx
->emit_tile_prep(ctx
, tile
);
275 ctx
->emit_tile_mem2gmem(ctx
, tile
);
277 ctx
->emit_tile_renderprep(ctx
, tile
);
279 /* emit IB to drawcmds: */
280 OUT_IB(ctx
->ring
, ctx
->draw_start
, ctx
->draw_end
);
282 /* emit gmem2mem to transfer tile back to system memory: */
283 ctx
->emit_tile_gmem2mem(ctx
, tile
);
288 render_sysmem(struct fd_context
*ctx
)
290 ctx
->emit_sysmem_prep(ctx
);
292 /* emit IB to drawcmds: */
293 OUT_IB(ctx
->ring
, ctx
->draw_start
, ctx
->draw_end
);
297 fd_gmem_render_tiles(struct pipe_context
*pctx
)
299 struct fd_context
*ctx
= fd_context(pctx
);
300 struct pipe_framebuffer_state
*pfb
= &ctx
->framebuffer
;
301 uint32_t timestamp
= 0;
304 if (ctx
->emit_sysmem_prep
) {
305 if (ctx
->cleared
|| ctx
->gmem_reason
|| (ctx
->num_draws
> 5)) {
306 DBG("GMEM: cleared=%x, gmem_reason=%x, num_draws=%u",
307 ctx
->cleared
, ctx
->gmem_reason
, ctx
->num_draws
);
308 } else if (!(fd_mesa_debug
& FD_DBG_DBYPASS
)) {
313 /* mark the end of the clear/draw cmds before emitting per-tile cmds: */
314 fd_ringmarker_mark(ctx
->draw_end
);
315 fd_ringmarker_mark(ctx
->binning_end
);
317 ctx
->stats
.batch_total
++;
320 DBG("rendering sysmem (%s/%s)",
321 util_format_short_name(pipe_surface_format(pfb
->cbufs
[0])),
322 util_format_short_name(pipe_surface_format(pfb
->zsbuf
)));
324 ctx
->stats
.batch_sysmem
++;
326 struct fd_gmem_stateobj
*gmem
= &ctx
->gmem
;
327 calculate_tiles(ctx
);
328 DBG("rendering %dx%d tiles (%s/%s)", gmem
->nbins_x
, gmem
->nbins_y
,
329 util_format_short_name(pipe_surface_format(pfb
->cbufs
[0])),
330 util_format_short_name(pipe_surface_format(pfb
->zsbuf
)));
332 ctx
->stats
.batch_gmem
++;
335 /* GPU executes starting from tile cmds, which IB back to draw cmds: */
336 fd_ringmarker_flush(ctx
->draw_end
);
338 /* mark start for next draw/binning cmds: */
339 fd_ringmarker_mark(ctx
->draw_start
);
340 fd_ringmarker_mark(ctx
->binning_start
);
342 fd_reset_rmw_state(ctx
);
344 /* update timestamps on render targets: */
345 timestamp
= fd_ringbuffer_timestamp(ctx
->ring
);
347 fd_resource(pfb
->cbufs
[0]->texture
)->timestamp
= timestamp
;
349 fd_resource(pfb
->zsbuf
->texture
)->timestamp
= timestamp
;
351 /* reset maximal bounds: */
352 ctx
->max_scissor
.minx
= ctx
->max_scissor
.miny
= ~0;
353 ctx
->max_scissor
.maxx
= ctx
->max_scissor
.maxy
= 0;
355 /* Note that because the per-tile setup and mem2gmem/gmem2mem are emitted
356 * after the draw/clear calls, but executed before, we need to preemptively
357 * flag some state as dirty before the first draw/clear call.
359 * TODO maybe we need to mark all state as dirty to not worry about state
360 * being clobbered by other contexts?
362 ctx
->dirty
|= FD_DIRTY_ZSA
|
363 FD_DIRTY_RASTERIZER
|
364 FD_DIRTY_FRAMEBUFFER
|
365 FD_DIRTY_SAMPLE_MASK
|
370 /* probably only needed if we need to mem2gmem on the next
371 * draw.. but not sure if there is a good way to know?
377 if (fd_mesa_debug
& FD_DBG_DGMEM
)
378 ctx
->dirty
= 0xffffffff;