1 /* -*- mode: C; c-file-style: "k&r"; tab-width 4; indent-tabs-mode: t; -*- */
4 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Rob Clark <robclark@freedesktop.org>
29 #include "pipe/p_state.h"
30 #include "util/u_string.h"
31 #include "util/u_memory.h"
32 #include "util/u_inlines.h"
33 #include "util/u_format.h"
35 #include "freedreno_gmem.h"
36 #include "freedreno_context.h"
37 #include "freedreno_resource.h"
38 #include "freedreno_util.h"
41 * GMEM is the small (ie. 256KiB for a200, 512KiB for a220, etc) tile buffer
42 * inside the GPU. All rendering happens to GMEM. Larger render targets
43 * are split into tiles that are small enough for the color (and depth and/or
44 * stencil, if enabled) buffers to fit within GMEM. Before rendering a tile,
45 * if there was not a clear invalidating the previous tile contents, we need
46 * to restore the previous tiles contents (system mem -> GMEM), and after all
47 * the draw calls, before moving to the next tile, we need to save the tile
48 * contents (GMEM -> system mem).
50 * The code in this file handles dealing with GMEM and tiling.
52 * The structure of the ringbuffer ends up being:
54 * +--<---<-- IB ---<---+---<---+---<---<---<--+
57 * ------------------------------------------------------
58 * | clear/draw cmds | Tile0 | Tile1 | .... | TileN |
59 * ------------------------------------------------------
62 * address submitted in issueibcmds
64 * Where the per-tile section handles scissor setup, mem2gmem restore (if
65 * needed), IB to draw cmds earlier in the ringbuffer, and then gmem2mem
70 calculate_tiles(struct fd_context
*ctx
)
72 struct fd_gmem_stateobj
*gmem
= &ctx
->gmem
;
73 struct pipe_scissor_state
*scissor
= &ctx
->max_scissor
;
74 uint32_t cpp
= util_format_get_blocksize(ctx
->framebuffer
.cbufs
[0]->format
);
75 uint32_t gmem_size
= ctx
->screen
->gmemsize_bytes
;
76 uint32_t minx
, miny
, width
, height
;
77 uint32_t nbins_x
= 1, nbins_y
= 1;
78 uint32_t bin_w
, bin_h
;
79 uint32_t max_width
= 992;
81 if ((gmem
->cpp
== cpp
) &&
82 !memcmp(&gmem
->scissor
, scissor
, sizeof(gmem
->scissor
))) {
83 /* everything is up-to-date */
87 minx
= scissor
->minx
& ~31; /* round down to multiple of 32 */
88 miny
= scissor
->miny
& ~31;
89 width
= scissor
->maxx
- minx
;
90 height
= scissor
->maxy
- miny
;
92 // TODO we probably could optimize this a bit if we know that
93 // Z or stencil is not enabled for any of the draw calls..
94 // if (fd_stencil_enabled(ctx->zsa) || fd_depth_enabled(ctx->zsa)) {
99 bin_w
= align(width
, 32);
100 bin_h
= align(height
, 32);
102 /* first, find a bin width that satisfies the maximum width
105 while (bin_w
> max_width
) {
107 bin_w
= align(width
/ nbins_x
, 32);
110 /* then find a bin height that satisfies the memory constraints:
112 while ((bin_w
* bin_h
* cpp
) > gmem_size
) {
114 bin_h
= align(height
/ nbins_y
, 32);
117 DBG("using %d bins of size %dx%d", nbins_x
*nbins_y
, bin_w
, bin_h
);
119 gmem
->scissor
= *scissor
;
125 gmem
->nbins_x
= nbins_x
;
126 gmem
->nbins_y
= nbins_y
;
128 gmem
->height
= height
;
133 fd_gmem_render_tiles(struct pipe_context
*pctx
)
135 struct fd_context
*ctx
= fd_context(pctx
);
136 struct pipe_framebuffer_state
*pfb
= &ctx
->framebuffer
;
137 struct fd_gmem_stateobj
*gmem
= &ctx
->gmem
;
138 uint32_t i
, timestamp
, yoff
= 0;
140 calculate_tiles(ctx
);
142 DBG("rendering %dx%d tiles (%s/%s)", gmem
->nbins_x
, gmem
->nbins_y
,
143 util_format_name(pfb
->cbufs
[0]->format
),
144 pfb
->zsbuf
? util_format_name(pfb
->zsbuf
->format
) : "none");
146 /* mark the end of the clear/draw cmds before emitting per-tile cmds: */
147 fd_ringmarker_mark(ctx
->draw_end
);
151 ctx
->emit_tile_init(ctx
);
153 for (i
= 0; i
< gmem
->nbins_y
; i
++) {
154 uint32_t j
, xoff
= gmem
->minx
;
155 uint32_t bh
= gmem
->bin_h
;
157 /* clip bin height: */
158 bh
= MIN2(bh
, gmem
->height
- yoff
);
160 for (j
= 0; j
< gmem
->nbins_x
; j
++) {
161 uint32_t bw
= gmem
->bin_w
;
163 /* clip bin width: */
164 bw
= MIN2(bw
, gmem
->width
- xoff
);
166 DBG("bin_h=%d, yoff=%d, bin_w=%d, xoff=%d",
169 ctx
->emit_tile_prep(ctx
, xoff
, yoff
, bw
, bh
);
172 ctx
->emit_tile_mem2gmem(ctx
, xoff
, yoff
, bw
, bh
);
174 ctx
->emit_tile_renderprep(ctx
, xoff
, yoff
, bw
, bh
);
176 /* emit IB to drawcmds: */
177 OUT_IB(ctx
->ring
, ctx
->draw_start
, ctx
->draw_end
);
179 /* emit gmem2mem to transfer tile back to system memory: */
180 ctx
->emit_tile_gmem2mem(ctx
, xoff
, yoff
, bw
, bh
);
188 /* GPU executes starting from tile cmds, which IB back to draw cmds: */
189 fd_ringmarker_flush(ctx
->draw_end
);
191 /* mark start for next draw cmds: */
192 fd_ringmarker_mark(ctx
->draw_start
);
194 /* update timestamps on render targets: */
195 timestamp
= fd_ringbuffer_timestamp(ctx
->ring
);
196 fd_resource(pfb
->cbufs
[0]->texture
)->timestamp
= timestamp
;
198 fd_resource(pfb
->zsbuf
->texture
)->timestamp
= timestamp
;
200 /* reset maximal bounds: */
201 ctx
->max_scissor
.minx
= ctx
->max_scissor
.miny
= ~0;
202 ctx
->max_scissor
.maxx
= ctx
->max_scissor
.maxy
= 0;
204 /* Note that because the per-tile setup and mem2gmem/gmem2mem are emitted
205 * after the draw/clear calls, but executed before, we need to preemptively
206 * flag some state as dirty before the first draw/clear call.
208 * TODO maybe we need to mark all state as dirty to not worry about state
209 * being clobbered by other contexts?
211 ctx
->dirty
|= FD_DIRTY_ZSA
|
212 FD_DIRTY_RASTERIZER
|
213 FD_DIRTY_FRAMEBUFFER
|
214 FD_DIRTY_SAMPLE_MASK
|
219 /* probably only needed if we need to mem2gmem on the next
220 * draw.. but not sure if there is a good way to know?
226 if (fd_mesa_debug
& FD_DBG_DGMEM
)
227 ctx
->dirty
= 0xffffffff;